nvme.h revision 252271
1189251Ssam/*- 2189251Ssam * Copyright (C) 2012 Intel Corporation 3252726Srpaulo * All rights reserved. 4189251Ssam * 5252726Srpaulo * Redistribution and use in source and binary forms, with or without 6252726Srpaulo * modification, are permitted provided that the following conditions 7189251Ssam * are met: 8189251Ssam * 1. Redistributions of source code must retain the above copyright 9189251Ssam * notice, this list of conditions and the following disclaimer. 10189251Ssam * 2. Redistributions in binary form must reproduce the above copyright 11189251Ssam * notice, this list of conditions and the following disclaimer in the 12189251Ssam * documentation and/or other materials provided with the distribution. 13189251Ssam * 14189251Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15189251Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16189251Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17189251Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18189251Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19189251Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20189251Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21189251Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22189251Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23189251Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24252726Srpaulo * SUCH DAMAGE. 25189251Ssam * 26252726Srpaulo * $FreeBSD: head/sys/dev/nvme/nvme.h 252271 2013-06-26 23:27:17Z jimharris $ 27252726Srpaulo */ 28189251Ssam 29189251Ssam#ifndef __NVME_H__ 30189251Ssam#define __NVME_H__ 31189251Ssam 32189251Ssam#ifdef _KERNEL 33189251Ssam#include <sys/types.h> 34189251Ssam#endif 35189251Ssam 36189251Ssam#include <sys/param.h> 37189251Ssam 38189251Ssam#define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 39252726Srpaulo#define NVME_RESET_CONTROLLER _IO('n', 1) 40189251Ssam 41189251Ssam#define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 42189251Ssam#define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 43189251Ssam 44252726Srpaulo/* 45252726Srpaulo * Use to mark a command to apply to all namespaces, or to retrieve global 46189251Ssam * log pages. 47189251Ssam */ 48189251Ssam#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 49189251Ssam 50189251Ssam#define NVME_MAX_XFER_SIZE MAXPHYS 51189251Ssam 52189251Ssamunion cap_lo_register { 53189251Ssam uint32_t raw; 54189251Ssam struct { 55189251Ssam /** maximum queue entries supported */ 56189251Ssam uint32_t mqes : 16; 57189251Ssam 58189251Ssam /** contiguous queues required */ 59189251Ssam uint32_t cqr : 1; 60189251Ssam 61189251Ssam /** arbitration mechanism supported */ 62189251Ssam uint32_t ams : 2; 63189251Ssam 64189251Ssam uint32_t reserved1 : 5; 65189251Ssam 66189251Ssam /** timeout */ 67189251Ssam uint32_t to : 8; 68189251Ssam } bits __packed; 69189251Ssam} __packed; 70189251Ssam 71189251Ssamunion cap_hi_register { 72189251Ssam uint32_t raw; 73252726Srpaulo struct { 74252726Srpaulo /** doorbell stride */ 75189251Ssam uint32_t dstrd : 4; 76189251Ssam 77189251Ssam uint32_t reserved3 : 1; 78189251Ssam 79189251Ssam /** command sets supported */ 80189251Ssam uint32_t css_nvm : 1; 81189251Ssam 82189251Ssam uint32_t css_reserved : 3; 83189251Ssam uint32_t reserved2 : 7; 84189251Ssam 85189251Ssam /** memory page size minimum */ 86189251Ssam uint32_t mpsmin : 4; 87252726Srpaulo 88189251Ssam /** memory page size maximum */ 89189251Ssam uint32_t mpsmax : 4; 90189251Ssam 91189251Ssam uint32_t reserved1 : 8; 92189251Ssam } bits __packed; 93189251Ssam} __packed; 94189251Ssam 95189251Ssamunion cc_register { 96189251Ssam uint32_t raw; 97252726Srpaulo struct { 98252726Srpaulo /** enable */ 99189251Ssam uint32_t en : 1; 100252726Srpaulo 101252726Srpaulo uint32_t reserved1 : 3; 102189251Ssam 103252726Srpaulo /** i/o command set selected */ 104189251Ssam uint32_t css : 3; 105 106 /** memory page size */ 107 uint32_t mps : 4; 108 109 /** arbitration mechanism selected */ 110 uint32_t ams : 3; 111 112 /** shutdown notification */ 113 uint32_t shn : 2; 114 115 /** i/o submission queue entry size */ 116 uint32_t iosqes : 4; 117 118 /** i/o completion queue entry size */ 119 uint32_t iocqes : 4; 120 121 uint32_t reserved2 : 8; 122 } bits __packed; 123} __packed; 124 125enum shn_value { 126 NVME_SHN_NORMAL = 0x1, 127 NVME_SHN_ABRUPT = 0x2, 128}; 129 130union csts_register { 131 uint32_t raw; 132 struct { 133 /** ready */ 134 uint32_t rdy : 1; 135 136 /** controller fatal status */ 137 uint32_t cfs : 1; 138 139 /** shutdown status */ 140 uint32_t shst : 2; 141 142 uint32_t reserved1 : 28; 143 } bits __packed; 144} __packed; 145 146enum shst_value { 147 NVME_SHST_NORMAL = 0x0, 148 NVME_SHST_OCCURRING = 0x1, 149 NVME_SHST_COMPLETE = 0x2, 150}; 151 152union aqa_register { 153 uint32_t raw; 154 struct { 155 /** admin submission queue size */ 156 uint32_t asqs : 12; 157 158 uint32_t reserved1 : 4; 159 160 /** admin completion queue size */ 161 uint32_t acqs : 12; 162 163 uint32_t reserved2 : 4; 164 } bits __packed; 165} __packed; 166 167struct nvme_registers 168{ 169 /** controller capabilities */ 170 union cap_lo_register cap_lo; 171 union cap_hi_register cap_hi; 172 173 uint32_t vs; /* version */ 174 uint32_t intms; /* interrupt mask set */ 175 uint32_t intmc; /* interrupt mask clear */ 176 177 /** controller configuration */ 178 union cc_register cc; 179 180 uint32_t reserved1; 181 uint32_t csts; /* controller status */ 182 uint32_t reserved2; 183 184 /** admin queue attributes */ 185 union aqa_register aqa; 186 187 uint64_t asq; /* admin submission queue base addr */ 188 uint64_t acq; /* admin completion queue base addr */ 189 uint32_t reserved3[0x3f2]; 190 191 struct { 192 uint32_t sq_tdbl; /* submission queue tail doorbell */ 193 uint32_t cq_hdbl; /* completion queue head doorbell */ 194 } doorbell[1] __packed; 195} __packed; 196 197struct nvme_command 198{ 199 /* dword 0 */ 200 uint16_t opc : 8; /* opcode */ 201 uint16_t fuse : 2; /* fused operation */ 202 uint16_t rsvd1 : 6; 203 uint16_t cid; /* command identifier */ 204 205 /* dword 1 */ 206 uint32_t nsid; /* namespace identifier */ 207 208 /* dword 2-3 */ 209 uint32_t rsvd2; 210 uint32_t rsvd3; 211 212 /* dword 4-5 */ 213 uint64_t mptr; /* metadata pointer */ 214 215 /* dword 6-7 */ 216 uint64_t prp1; /* prp entry 1 */ 217 218 /* dword 8-9 */ 219 uint64_t prp2; /* prp entry 2 */ 220 221 /* dword 10-15 */ 222 uint32_t cdw10; /* command-specific */ 223 uint32_t cdw11; /* command-specific */ 224 uint32_t cdw12; /* command-specific */ 225 uint32_t cdw13; /* command-specific */ 226 uint32_t cdw14; /* command-specific */ 227 uint32_t cdw15; /* command-specific */ 228} __packed; 229 230struct nvme_status { 231 232 uint16_t p : 1; /* phase tag */ 233 uint16_t sc : 8; /* status code */ 234 uint16_t sct : 3; /* status code type */ 235 uint16_t rsvd2 : 2; 236 uint16_t m : 1; /* more */ 237 uint16_t dnr : 1; /* do not retry */ 238} __packed; 239 240struct nvme_completion { 241 242 /* dword 0 */ 243 uint32_t cdw0; /* command-specific */ 244 245 /* dword 1 */ 246 uint32_t rsvd1; 247 248 /* dword 2 */ 249 uint16_t sqhd; /* submission queue head pointer */ 250 uint16_t sqid; /* submission queue identifier */ 251 252 /* dword 3 */ 253 uint16_t cid; /* command identifier */ 254 struct nvme_status status; 255} __packed; 256 257struct nvme_dsm_range { 258 259 uint32_t attributes; 260 uint32_t length; 261 uint64_t starting_lba; 262} __packed; 263 264/* status code types */ 265enum nvme_status_code_type { 266 NVME_SCT_GENERIC = 0x0, 267 NVME_SCT_COMMAND_SPECIFIC = 0x1, 268 NVME_SCT_MEDIA_ERROR = 0x2, 269 /* 0x3-0x6 - reserved */ 270 NVME_SCT_VENDOR_SPECIFIC = 0x7, 271}; 272 273/* generic command status codes */ 274enum nvme_generic_command_status_code { 275 NVME_SC_SUCCESS = 0x00, 276 NVME_SC_INVALID_OPCODE = 0x01, 277 NVME_SC_INVALID_FIELD = 0x02, 278 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 279 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 280 NVME_SC_ABORTED_POWER_LOSS = 0x05, 281 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 282 NVME_SC_ABORTED_BY_REQUEST = 0x07, 283 NVME_SC_ABORTED_SQ_DELETION = 0x08, 284 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 285 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 286 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 287 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 288 289 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 290 NVME_SC_CAPACITY_EXCEEDED = 0x81, 291 NVME_SC_NAMESPACE_NOT_READY = 0x82, 292}; 293 294/* command specific status codes */ 295enum nvme_command_specific_status_code { 296 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 297 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 298 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 299 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 300 /* 0x04 - reserved */ 301 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 302 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 303 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 304 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 305 NVME_SC_INVALID_LOG_PAGE = 0x09, 306 NVME_SC_INVALID_FORMAT = 0x0a, 307 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 308 309 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 310 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 311 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 312}; 313 314/* media error status codes */ 315enum nvme_media_error_status_code { 316 NVME_SC_WRITE_FAULTS = 0x80, 317 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 318 NVME_SC_GUARD_CHECK_ERROR = 0x82, 319 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 320 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 321 NVME_SC_COMPARE_FAILURE = 0x85, 322 NVME_SC_ACCESS_DENIED = 0x86, 323}; 324 325/* admin opcodes */ 326enum nvme_admin_opcode { 327 NVME_OPC_DELETE_IO_SQ = 0x00, 328 NVME_OPC_CREATE_IO_SQ = 0x01, 329 NVME_OPC_GET_LOG_PAGE = 0x02, 330 /* 0x03 - reserved */ 331 NVME_OPC_DELETE_IO_CQ = 0x04, 332 NVME_OPC_CREATE_IO_CQ = 0x05, 333 NVME_OPC_IDENTIFY = 0x06, 334 /* 0x07 - reserved */ 335 NVME_OPC_ABORT = 0x08, 336 NVME_OPC_SET_FEATURES = 0x09, 337 NVME_OPC_GET_FEATURES = 0x0a, 338 /* 0x0b - reserved */ 339 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 340 /* 0x0d-0x0f - reserved */ 341 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 342 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 343 344 NVME_OPC_FORMAT_NVM = 0x80, 345 NVME_OPC_SECURITY_SEND = 0x81, 346 NVME_OPC_SECURITY_RECEIVE = 0x82, 347}; 348 349/* nvme nvm opcodes */ 350enum nvme_nvm_opcode { 351 NVME_OPC_FLUSH = 0x00, 352 NVME_OPC_WRITE = 0x01, 353 NVME_OPC_READ = 0x02, 354 /* 0x03 - reserved */ 355 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 356 NVME_OPC_COMPARE = 0x05, 357 /* 0x06-0x07 - reserved */ 358 NVME_OPC_DATASET_MANAGEMENT = 0x09, 359}; 360 361enum nvme_feature { 362 /* 0x00 - reserved */ 363 NVME_FEAT_ARBITRATION = 0x01, 364 NVME_FEAT_POWER_MANAGEMENT = 0x02, 365 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 366 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 367 NVME_FEAT_ERROR_RECOVERY = 0x05, 368 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 369 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 370 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 371 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 372 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 373 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 374 /* 0x0C-0x7F - reserved */ 375 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 376 /* 0x81-0xBF - command set specific (reserved) */ 377 /* 0xC0-0xFF - vendor specific */ 378}; 379 380enum nvme_dsm_attribute { 381 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 382 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 383 NVME_DSM_ATTR_DEALLOCATE = 0x4, 384}; 385 386struct nvme_controller_data { 387 388 /* bytes 0-255: controller capabilities and features */ 389 390 /** pci vendor id */ 391 uint16_t vid; 392 393 /** pci subsystem vendor id */ 394 uint16_t ssvid; 395 396 /** serial number */ 397 int8_t sn[20]; 398 399 /** model number */ 400 int8_t mn[40]; 401 402 /** firmware revision */ 403 uint8_t fr[8]; 404 405 /** recommended arbitration burst */ 406 uint8_t rab; 407 408 /** ieee oui identifier */ 409 uint8_t ieee[3]; 410 411 /** multi-interface capabilities */ 412 uint8_t mic; 413 414 /** maximum data transfer size */ 415 uint8_t mdts; 416 417 uint8_t reserved1[178]; 418 419 /* bytes 256-511: admin command set attributes */ 420 421 /** optional admin command support */ 422 struct { 423 /* supports security send/receive commands */ 424 uint16_t security : 1; 425 426 /* supports format nvm command */ 427 uint16_t format : 1; 428 429 /* supports firmware activate/download commands */ 430 uint16_t firmware : 1; 431 432 uint16_t oacs_rsvd : 13; 433 } __packed oacs; 434 435 /** abort command limit */ 436 uint8_t acl; 437 438 /** asynchronous event request limit */ 439 uint8_t aerl; 440 441 /** firmware updates */ 442 struct { 443 /* first slot is read-only */ 444 uint8_t slot1_ro : 1; 445 446 /* number of firmware slots */ 447 uint8_t num_slots : 3; 448 449 uint8_t frmw_rsvd : 4; 450 } __packed frmw; 451 452 /** log page attributes */ 453 struct { 454 /* per namespace smart/health log page */ 455 uint8_t ns_smart : 1; 456 457 uint8_t lpa_rsvd : 7; 458 } __packed lpa; 459 460 /** error log page entries */ 461 uint8_t elpe; 462 463 /** number of power states supported */ 464 uint8_t npss; 465 466 /** admin vendor specific command configuration */ 467 struct { 468 /* admin vendor specific commands use spec format */ 469 uint8_t spec_format : 1; 470 471 uint8_t avscc_rsvd : 7; 472 } __packed avscc; 473 474 uint8_t reserved2[247]; 475 476 /* bytes 512-703: nvm command set attributes */ 477 478 /** submission queue entry size */ 479 struct { 480 uint8_t min : 4; 481 uint8_t max : 4; 482 } __packed sqes; 483 484 /** completion queue entry size */ 485 struct { 486 uint8_t min : 4; 487 uint8_t max : 4; 488 } __packed cqes; 489 490 uint8_t reserved3[2]; 491 492 /** number of namespaces */ 493 uint32_t nn; 494 495 /** optional nvm command support */ 496 struct { 497 uint16_t compare : 1; 498 uint16_t write_unc : 1; 499 uint16_t dsm: 1; 500 uint16_t reserved: 13; 501 } __packed oncs; 502 503 /** fused operation support */ 504 uint16_t fuses; 505 506 /** format nvm attributes */ 507 uint8_t fna; 508 509 /** volatile write cache */ 510 struct { 511 uint8_t present : 1; 512 uint8_t reserved : 7; 513 } __packed vwc; 514 515 /* TODO: flesh out remaining nvm command set attributes */ 516 uint8_t reserved4[178]; 517 518 /* bytes 704-2047: i/o command set attributes */ 519 uint8_t reserved5[1344]; 520 521 /* bytes 2048-3071: power state descriptors */ 522 uint8_t reserved6[1024]; 523 524 /* bytes 3072-4095: vendor specific */ 525 uint8_t reserved7[1024]; 526} __packed __aligned(4); 527 528struct nvme_namespace_data { 529 530 /** namespace size */ 531 uint64_t nsze; 532 533 /** namespace capacity */ 534 uint64_t ncap; 535 536 /** namespace utilization */ 537 uint64_t nuse; 538 539 /** namespace features */ 540 struct { 541 /** thin provisioning */ 542 uint8_t thin_prov : 1; 543 uint8_t reserved1 : 7; 544 } __packed nsfeat; 545 546 /** number of lba formats */ 547 uint8_t nlbaf; 548 549 /** formatted lba size */ 550 struct { 551 uint8_t format : 4; 552 uint8_t extended : 1; 553 uint8_t reserved2 : 3; 554 } __packed flbas; 555 556 /** metadata capabilities */ 557 struct { 558 /* metadata can be transferred as part of data prp list */ 559 uint8_t extended : 1; 560 561 /* metadata can be transferred with separate metadata pointer */ 562 uint8_t pointer : 1; 563 564 uint8_t reserved3 : 6; 565 } __packed mc; 566 567 /** end-to-end data protection capabilities */ 568 struct { 569 /* protection information type 1 */ 570 uint8_t pit1 : 1; 571 572 /* protection information type 2 */ 573 uint8_t pit2 : 1; 574 575 /* protection information type 3 */ 576 uint8_t pit3 : 1; 577 578 /* first eight bytes of metadata */ 579 uint8_t md_start : 1; 580 581 /* last eight bytes of metadata */ 582 uint8_t md_end : 1; 583 } __packed dpc; 584 585 /** end-to-end data protection type settings */ 586 struct { 587 /* protection information type */ 588 uint8_t pit : 3; 589 590 /* 1 == protection info transferred at start of metadata */ 591 /* 0 == protection info transferred at end of metadata */ 592 uint8_t md_start : 1; 593 594 uint8_t reserved4 : 4; 595 } __packed dps; 596 597 uint8_t reserved5[98]; 598 599 /** lba format support */ 600 struct { 601 /** metadata size */ 602 uint32_t ms : 16; 603 604 /** lba data size */ 605 uint32_t lbads : 8; 606 607 /** relative performance */ 608 uint32_t rp : 2; 609 610 uint32_t reserved6 : 6; 611 } __packed lbaf[16]; 612 613 uint8_t reserved6[192]; 614 615 uint8_t vendor_specific[3712]; 616} __packed __aligned(4); 617 618enum nvme_log_page { 619 620 /* 0x00 - reserved */ 621 NVME_LOG_ERROR = 0x01, 622 NVME_LOG_HEALTH_INFORMATION = 0x02, 623 NVME_LOG_FIRMWARE_SLOT = 0x03, 624 /* 0x04-0x7F - reserved */ 625 /* 0x80-0xBF - I/O command set specific */ 626 /* 0xC0-0xFF - vendor specific */ 627}; 628 629struct nvme_error_information_entry { 630 631 uint64_t error_count; 632 uint16_t sqid; 633 uint16_t cid; 634 struct nvme_status status; 635 uint16_t error_location; 636 uint64_t lba; 637 uint32_t nsid; 638 uint8_t vendor_specific; 639 uint8_t reserved[35]; 640} __packed __aligned(4); 641 642union nvme_critical_warning_state { 643 644 uint8_t raw; 645 646 struct { 647 uint8_t available_spare : 1; 648 uint8_t temperature : 1; 649 uint8_t device_reliability : 1; 650 uint8_t read_only : 1; 651 uint8_t volatile_memory_backup : 1; 652 uint8_t reserved : 3; 653 } __packed bits; 654} __packed; 655 656struct nvme_health_information_page { 657 658 union nvme_critical_warning_state critical_warning; 659 660 uint16_t temperature; 661 uint8_t available_spare; 662 uint8_t available_spare_threshold; 663 uint8_t percentage_used; 664 665 uint8_t reserved[26]; 666 667 /* 668 * Note that the following are 128-bit values, but are 669 * defined as an array of 2 64-bit values. 670 */ 671 /* Data Units Read is always in 512-byte units. */ 672 uint64_t data_units_read[2]; 673 /* Data Units Written is always in 512-byte units. */ 674 uint64_t data_units_written[2]; 675 /* For NVM command set, this includes Compare commands. */ 676 uint64_t host_read_commands[2]; 677 uint64_t host_write_commands[2]; 678 /* Controller Busy Time is reported in minutes. */ 679 uint64_t controller_busy_time[2]; 680 uint64_t power_cycles[2]; 681 uint64_t power_on_hours[2]; 682 uint64_t unsafe_shutdowns[2]; 683 uint64_t media_errors[2]; 684 uint64_t num_error_info_log_entries[2]; 685 686 uint8_t reserved2[320]; 687} __packed __aligned(4); 688 689struct nvme_firmware_page { 690 691 struct { 692 uint8_t slot : 3; /* slot for current FW */ 693 uint8_t reserved : 5; 694 } __packed afi; 695 696 uint8_t reserved[7]; 697 uint64_t revision[7]; /* revisions for 7 slots */ 698 uint8_t reserved2[448]; 699} __packed __aligned(4); 700 701#define NVME_TEST_MAX_THREADS 128 702 703struct nvme_io_test { 704 705 enum nvme_nvm_opcode opc; 706 uint32_t size; 707 uint32_t time; /* in seconds */ 708 uint32_t num_threads; 709 uint32_t flags; 710 uint32_t io_completed[NVME_TEST_MAX_THREADS]; 711}; 712 713enum nvme_io_test_flags { 714 715 /* 716 * Specifies whether dev_refthread/dev_relthread should be 717 * called during NVME_BIO_TEST. Ignored for other test 718 * types. 719 */ 720 NVME_TEST_FLAG_REFTHREAD = 0x1, 721}; 722 723struct nvme_pt_command { 724 725 /* 726 * cmd is used to specify a passthrough command to a controller or 727 * namespace. 728 * 729 * The following fields from cmd may be specified by the caller: 730 * * opc (opcode) 731 * * nsid (namespace id) - for admin commands only 732 * * cdw10-cdw15 733 * 734 * Remaining fields must be set to 0 by the caller. 735 */ 736 struct nvme_command cmd; 737 738 /* 739 * cpl returns completion status for the passthrough command 740 * specified by cmd. 741 * 742 * The following fields will be filled out by the driver, for 743 * consumption by the caller: 744 * * cdw0 745 * * status (except for phase) 746 * 747 * Remaining fields will be set to 0 by the driver. 748 */ 749 struct nvme_completion cpl; 750 751 /* buf is the data buffer associated with this passthrough command. */ 752 void * buf; 753 754 /* 755 * len is the length of the data buffer associated with this 756 * passthrough command. 757 */ 758 uint32_t len; 759 760 /* 761 * is_read = 1 if the passthrough command will read data into the 762 * supplied buffer. 763 * 764 * is_read = 0 if the passthrough command will write data into the 765 * supplied buffer. 766 */ 767 uint32_t is_read; 768 769 /* 770 * driver_lock is used by the driver only. It must be set to 0 771 * by the caller. 772 */ 773 struct mtx * driver_lock; 774}; 775 776#define nvme_completion_is_error(cpl) \ 777 ((cpl)->status.sc != 0 || (cpl)->status.sct != 0) 778 779#ifdef _KERNEL 780 781struct bio; 782 783struct nvme_namespace; 784struct nvme_controller; 785struct nvme_consumer; 786 787typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 788 789typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 790typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 791typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 792 uint32_t, void *, uint32_t); 793typedef void (*nvme_cons_fail_fn_t)(void *); 794 795enum nvme_namespace_flags { 796 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 797 NVME_NS_FLUSH_SUPPORTED = 0x2, 798}; 799 800int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 801 struct nvme_pt_command *pt, 802 uint32_t nsid, int is_user_buffer, 803 int is_admin_cmd); 804 805/* Admin functions */ 806void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 807 uint8_t feature, uint32_t cdw11, 808 void *payload, uint32_t payload_size, 809 nvme_cb_fn_t cb_fn, void *cb_arg); 810void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 811 uint8_t feature, uint32_t cdw11, 812 void *payload, uint32_t payload_size, 813 nvme_cb_fn_t cb_fn, void *cb_arg); 814void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 815 uint8_t log_page, uint32_t nsid, 816 void *payload, uint32_t payload_size, 817 nvme_cb_fn_t cb_fn, void *cb_arg); 818 819/* NVM I/O functions */ 820int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 821 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 822 void *cb_arg); 823int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 824 nvme_cb_fn_t cb_fn, void *cb_arg); 825int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 826 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 827 void *cb_arg); 828int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 829 nvme_cb_fn_t cb_fn, void *cb_arg); 830int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 831 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 832 void *cb_arg); 833int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 834 void *cb_arg); 835 836/* Registration functions */ 837struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 838 nvme_cons_ctrlr_fn_t ctrlr_fn, 839 nvme_cons_async_fn_t async_fn, 840 nvme_cons_fail_fn_t fail_fn); 841void nvme_unregister_consumer(struct nvme_consumer *consumer); 842 843/* Controller helper functions */ 844device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 845const struct nvme_controller_data * 846 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 847 848/* Namespace helper functions */ 849uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 850uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 851uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 852uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 853uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 854const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 855const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 856const struct nvme_namespace_data * 857 nvme_ns_get_data(struct nvme_namespace *ns); 858 859int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 860 nvme_cb_fn_t cb_fn); 861 862#endif /* _KERNEL */ 863 864#endif /* __NVME_H__ */ 865