nvme.h revision 249421
1240616Sjimharris/*- 2240616Sjimharris * Copyright (C) 2012 Intel Corporation 3240616Sjimharris * All rights reserved. 4240616Sjimharris * 5240616Sjimharris * Redistribution and use in source and binary forms, with or without 6240616Sjimharris * modification, are permitted provided that the following conditions 7240616Sjimharris * are met: 8240616Sjimharris * 1. Redistributions of source code must retain the above copyright 9240616Sjimharris * notice, this list of conditions and the following disclaimer. 10240616Sjimharris * 2. Redistributions in binary form must reproduce the above copyright 11240616Sjimharris * notice, this list of conditions and the following disclaimer in the 12240616Sjimharris * documentation and/or other materials provided with the distribution. 13240616Sjimharris * 14240616Sjimharris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15240616Sjimharris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16240616Sjimharris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17240616Sjimharris * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18240616Sjimharris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19240616Sjimharris * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20240616Sjimharris * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21240616Sjimharris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22240616Sjimharris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23240616Sjimharris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24240616Sjimharris * SUCH DAMAGE. 25240616Sjimharris * 26240616Sjimharris * $FreeBSD: head/sys/dev/nvme/nvme.h 249421 2013-04-12 17:52:17Z jimharris $ 27240616Sjimharris */ 28240616Sjimharris 29240616Sjimharris#ifndef __NVME_H__ 30240616Sjimharris#define __NVME_H__ 31240616Sjimharris 32240616Sjimharris#ifdef _KERNEL 33240616Sjimharris#include <sys/types.h> 34240616Sjimharris#endif 35240616Sjimharris 36240616Sjimharris#define NVME_IDENTIFY_CONTROLLER _IOR('n', 0, struct nvme_controller_data) 37240616Sjimharris#define NVME_IDENTIFY_NAMESPACE _IOR('n', 1, struct nvme_namespace_data) 38240616Sjimharris#define NVME_IO_TEST _IOWR('n', 2, struct nvme_io_test) 39240616Sjimharris#define NVME_BIO_TEST _IOWR('n', 4, struct nvme_io_test) 40248746Sjimharris#define NVME_RESET_CONTROLLER _IO('n', 5) 41249421Sjimharris#define NVME_PASSTHROUGH_CMD _IOWR('n', 6, struct nvme_pt_command) 42240616Sjimharris 43240616Sjimharris/* 44240616Sjimharris * Use to mark a command to apply to all namespaces, or to retrieve global 45240616Sjimharris * log pages. 46240616Sjimharris */ 47240616Sjimharris#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 48240616Sjimharris 49240616Sjimharrisunion cap_lo_register { 50240616Sjimharris uint32_t raw; 51240616Sjimharris struct { 52240616Sjimharris /** maximum queue entries supported */ 53240616Sjimharris uint32_t mqes : 16; 54240616Sjimharris 55240616Sjimharris /** contiguous queues required */ 56240616Sjimharris uint32_t cqr : 1; 57240616Sjimharris 58240616Sjimharris /** arbitration mechanism supported */ 59240616Sjimharris uint32_t ams : 2; 60240616Sjimharris 61240616Sjimharris uint32_t reserved1 : 5; 62240616Sjimharris 63240616Sjimharris /** timeout */ 64240616Sjimharris uint32_t to : 8; 65240616Sjimharris } bits __packed; 66240616Sjimharris} __packed; 67240616Sjimharris 68240616Sjimharrisunion cap_hi_register { 69240616Sjimharris uint32_t raw; 70240616Sjimharris struct { 71240616Sjimharris /** doorbell stride */ 72240616Sjimharris uint32_t dstrd : 4; 73240616Sjimharris 74240616Sjimharris uint32_t reserved3 : 1; 75240616Sjimharris 76240616Sjimharris /** command sets supported */ 77240616Sjimharris uint32_t css_nvm : 1; 78240616Sjimharris 79240616Sjimharris uint32_t css_reserved : 3; 80240616Sjimharris uint32_t reserved2 : 7; 81240616Sjimharris 82240616Sjimharris /** memory page size minimum */ 83240616Sjimharris uint32_t mpsmin : 4; 84240616Sjimharris 85240616Sjimharris /** memory page size maximum */ 86240616Sjimharris uint32_t mpsmax : 4; 87240616Sjimharris 88240616Sjimharris uint32_t reserved1 : 8; 89240616Sjimharris } bits __packed; 90240616Sjimharris} __packed; 91240616Sjimharris 92240616Sjimharrisunion cc_register { 93240616Sjimharris uint32_t raw; 94240616Sjimharris struct { 95240616Sjimharris /** enable */ 96240616Sjimharris uint32_t en : 1; 97240616Sjimharris 98240616Sjimharris uint32_t reserved1 : 3; 99240616Sjimharris 100240616Sjimharris /** i/o command set selected */ 101240616Sjimharris uint32_t css : 3; 102240616Sjimharris 103240616Sjimharris /** memory page size */ 104240616Sjimharris uint32_t mps : 4; 105240616Sjimharris 106240616Sjimharris /** arbitration mechanism selected */ 107240616Sjimharris uint32_t ams : 3; 108240616Sjimharris 109240616Sjimharris /** shutdown notification */ 110240616Sjimharris uint32_t shn : 2; 111240616Sjimharris 112240616Sjimharris /** i/o submission queue entry size */ 113240616Sjimharris uint32_t iosqes : 4; 114240616Sjimharris 115240616Sjimharris /** i/o completion queue entry size */ 116240616Sjimharris uint32_t iocqes : 4; 117240616Sjimharris 118240616Sjimharris uint32_t reserved2 : 8; 119240616Sjimharris } bits __packed; 120240616Sjimharris} __packed; 121240616Sjimharris 122240616Sjimharrisenum shn_value { 123240616Sjimharris NVME_SHN_NORMAL = 0x1, 124240616Sjimharris NVME_SHN_ABRUPT = 0x2, 125240616Sjimharris}; 126240616Sjimharris 127240616Sjimharrisunion csts_register { 128240616Sjimharris uint32_t raw; 129240616Sjimharris struct { 130240616Sjimharris /** ready */ 131240616Sjimharris uint32_t rdy : 1; 132240616Sjimharris 133240616Sjimharris /** controller fatal status */ 134240616Sjimharris uint32_t cfs : 1; 135240616Sjimharris 136240616Sjimharris /** shutdown status */ 137240616Sjimharris uint32_t shst : 2; 138240616Sjimharris 139240616Sjimharris uint32_t reserved1 : 28; 140240616Sjimharris } bits __packed; 141240616Sjimharris} __packed; 142240616Sjimharris 143240616Sjimharrisenum shst_value { 144240616Sjimharris NVME_SHST_NORMAL = 0x0, 145240616Sjimharris NVME_SHST_OCCURRING = 0x1, 146240616Sjimharris NVME_SHST_COMPLETE = 0x2, 147240616Sjimharris}; 148240616Sjimharris 149240616Sjimharrisunion aqa_register { 150240616Sjimharris uint32_t raw; 151240616Sjimharris struct { 152240616Sjimharris /** admin submission queue size */ 153240616Sjimharris uint32_t asqs : 12; 154240616Sjimharris 155240616Sjimharris uint32_t reserved1 : 4; 156240616Sjimharris 157240616Sjimharris /** admin completion queue size */ 158240616Sjimharris uint32_t acqs : 12; 159240616Sjimharris 160240616Sjimharris uint32_t reserved2 : 4; 161240616Sjimharris } bits __packed; 162240616Sjimharris} __packed; 163240616Sjimharris 164240616Sjimharrisstruct nvme_registers 165240616Sjimharris{ 166240616Sjimharris /** controller capabilities */ 167240616Sjimharris union cap_lo_register cap_lo; 168240616Sjimharris union cap_hi_register cap_hi; 169240616Sjimharris 170240616Sjimharris uint32_t vs; /* version */ 171240616Sjimharris uint32_t intms; /* interrupt mask set */ 172240616Sjimharris uint32_t intmc; /* interrupt mask clear */ 173240616Sjimharris 174240616Sjimharris /** controller configuration */ 175240616Sjimharris union cc_register cc; 176240616Sjimharris 177240616Sjimharris uint32_t reserved1; 178240616Sjimharris uint32_t csts; /* controller status */ 179240616Sjimharris uint32_t reserved2; 180240616Sjimharris 181240616Sjimharris /** admin queue attributes */ 182240616Sjimharris union aqa_register aqa; 183240616Sjimharris 184240616Sjimharris uint64_t asq; /* admin submission queue base addr */ 185240616Sjimharris uint64_t acq; /* admin completion queue base addr */ 186240616Sjimharris uint32_t reserved3[0x3f2]; 187240616Sjimharris 188240616Sjimharris struct { 189240616Sjimharris uint32_t sq_tdbl; /* submission queue tail doorbell */ 190240616Sjimharris uint32_t cq_hdbl; /* completion queue head doorbell */ 191240616Sjimharris } doorbell[1] __packed; 192240616Sjimharris} __packed; 193240616Sjimharris 194240616Sjimharrisstruct nvme_command 195240616Sjimharris{ 196240616Sjimharris /* dword 0 */ 197240616Sjimharris uint16_t opc : 8; /* opcode */ 198240616Sjimharris uint16_t fuse : 2; /* fused operation */ 199240616Sjimharris uint16_t rsvd1 : 6; 200240616Sjimharris uint16_t cid; /* command identifier */ 201240616Sjimharris 202240616Sjimharris /* dword 1 */ 203240616Sjimharris uint32_t nsid; /* namespace identifier */ 204240616Sjimharris 205240616Sjimharris /* dword 2-3 */ 206240616Sjimharris uint32_t rsvd2; 207240616Sjimharris uint32_t rsvd3; 208240616Sjimharris 209240616Sjimharris /* dword 4-5 */ 210240616Sjimharris uint64_t mptr; /* metadata pointer */ 211240616Sjimharris 212240616Sjimharris /* dword 6-7 */ 213240616Sjimharris uint64_t prp1; /* prp entry 1 */ 214240616Sjimharris 215240616Sjimharris /* dword 8-9 */ 216240616Sjimharris uint64_t prp2; /* prp entry 2 */ 217240616Sjimharris 218240616Sjimharris /* dword 10-15 */ 219240616Sjimharris uint32_t cdw10; /* command-specific */ 220240616Sjimharris uint32_t cdw11; /* command-specific */ 221240616Sjimharris uint32_t cdw12; /* command-specific */ 222240616Sjimharris uint32_t cdw13; /* command-specific */ 223240616Sjimharris uint32_t cdw14; /* command-specific */ 224240616Sjimharris uint32_t cdw15; /* command-specific */ 225240616Sjimharris} __packed; 226240616Sjimharris 227248756Sjimharrisstruct nvme_status { 228248756Sjimharris 229248756Sjimharris uint16_t p : 1; /* phase tag */ 230248756Sjimharris uint16_t sc : 8; /* status code */ 231248756Sjimharris uint16_t sct : 3; /* status code type */ 232248756Sjimharris uint16_t rsvd2 : 2; 233248756Sjimharris uint16_t m : 1; /* more */ 234248756Sjimharris uint16_t dnr : 1; /* do not retry */ 235248756Sjimharris} __packed; 236248756Sjimharris 237240616Sjimharrisstruct nvme_completion { 238240616Sjimharris 239240616Sjimharris /* dword 0 */ 240248756Sjimharris uint32_t cdw0; /* command-specific */ 241240616Sjimharris 242240616Sjimharris /* dword 1 */ 243248756Sjimharris uint32_t rsvd1; 244240616Sjimharris 245240616Sjimharris /* dword 2 */ 246248756Sjimharris uint16_t sqhd; /* submission queue head pointer */ 247248756Sjimharris uint16_t sqid; /* submission queue identifier */ 248240616Sjimharris 249240616Sjimharris /* dword 3 */ 250248756Sjimharris uint16_t cid; /* command identifier */ 251248756Sjimharris struct nvme_status status; 252240616Sjimharris} __packed; 253240616Sjimharris 254240616Sjimharrisstruct nvme_dsm_range { 255240616Sjimharris 256240616Sjimharris uint32_t attributes; 257240616Sjimharris uint32_t length; 258240616Sjimharris uint64_t starting_lba; 259240616Sjimharris} __packed; 260240616Sjimharris 261240616Sjimharris/* status code types */ 262240616Sjimharrisenum nvme_status_code_type { 263240616Sjimharris NVME_SCT_GENERIC = 0x0, 264240616Sjimharris NVME_SCT_COMMAND_SPECIFIC = 0x1, 265240616Sjimharris NVME_SCT_MEDIA_ERROR = 0x2, 266240616Sjimharris /* 0x3-0x6 - reserved */ 267240616Sjimharris NVME_SCT_VENDOR_SPECIFIC = 0x7, 268240616Sjimharris}; 269240616Sjimharris 270240616Sjimharris/* generic command status codes */ 271240616Sjimharrisenum nvme_generic_command_status_code { 272240616Sjimharris NVME_SC_SUCCESS = 0x00, 273240616Sjimharris NVME_SC_INVALID_OPCODE = 0x01, 274240616Sjimharris NVME_SC_INVALID_FIELD = 0x02, 275240616Sjimharris NVME_SC_COMMAND_ID_CONFLICT = 0x03, 276240616Sjimharris NVME_SC_DATA_TRANSFER_ERROR = 0x04, 277240616Sjimharris NVME_SC_ABORTED_POWER_LOSS = 0x05, 278240616Sjimharris NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 279240616Sjimharris NVME_SC_ABORTED_BY_REQUEST = 0x07, 280240616Sjimharris NVME_SC_ABORTED_SQ_DELETION = 0x08, 281240616Sjimharris NVME_SC_ABORTED_FAILED_FUSED = 0x09, 282240616Sjimharris NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 283240616Sjimharris NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 284240616Sjimharris NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 285240616Sjimharris 286240616Sjimharris NVME_SC_LBA_OUT_OF_RANGE = 0x80, 287240616Sjimharris NVME_SC_CAPACITY_EXCEEDED = 0x81, 288240616Sjimharris NVME_SC_NAMESPACE_NOT_READY = 0x82, 289240616Sjimharris}; 290240616Sjimharris 291240616Sjimharris/* command specific status codes */ 292240616Sjimharrisenum nvme_command_specific_status_code { 293240616Sjimharris NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 294240616Sjimharris NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 295240616Sjimharris NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 296240616Sjimharris NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 297240616Sjimharris /* 0x04 - reserved */ 298240616Sjimharris NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 299240616Sjimharris NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 300240616Sjimharris NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 301240616Sjimharris NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 302240616Sjimharris NVME_SC_INVALID_LOG_PAGE = 0x09, 303240616Sjimharris NVME_SC_INVALID_FORMAT = 0x0a, 304240616Sjimharris NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 305240616Sjimharris 306240616Sjimharris NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 307240616Sjimharris NVME_SC_INVALID_PROTECTION_INFO = 0x81, 308240616Sjimharris NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 309240616Sjimharris}; 310240616Sjimharris 311240616Sjimharris/* media error status codes */ 312240616Sjimharrisenum nvme_media_error_status_code { 313240616Sjimharris NVME_SC_WRITE_FAULTS = 0x80, 314240616Sjimharris NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 315240616Sjimharris NVME_SC_GUARD_CHECK_ERROR = 0x82, 316240616Sjimharris NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 317240616Sjimharris NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 318240616Sjimharris NVME_SC_COMPARE_FAILURE = 0x85, 319240616Sjimharris NVME_SC_ACCESS_DENIED = 0x86, 320240616Sjimharris}; 321240616Sjimharris 322240616Sjimharris/* admin opcodes */ 323240616Sjimharrisenum nvme_admin_opcode { 324240616Sjimharris NVME_OPC_DELETE_IO_SQ = 0x00, 325240616Sjimharris NVME_OPC_CREATE_IO_SQ = 0x01, 326240616Sjimharris NVME_OPC_GET_LOG_PAGE = 0x02, 327240616Sjimharris /* 0x03 - reserved */ 328240616Sjimharris NVME_OPC_DELETE_IO_CQ = 0x04, 329240616Sjimharris NVME_OPC_CREATE_IO_CQ = 0x05, 330240616Sjimharris NVME_OPC_IDENTIFY = 0x06, 331240616Sjimharris /* 0x07 - reserved */ 332240616Sjimharris NVME_OPC_ABORT = 0x08, 333240616Sjimharris NVME_OPC_SET_FEATURES = 0x09, 334240616Sjimharris NVME_OPC_GET_FEATURES = 0x0a, 335240616Sjimharris /* 0x0b - reserved */ 336240616Sjimharris NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 337240616Sjimharris /* 0x0d-0x0f - reserved */ 338240616Sjimharris NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 339240616Sjimharris NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 340240616Sjimharris 341240616Sjimharris NVME_OPC_FORMAT_NVM = 0x80, 342240616Sjimharris NVME_OPC_SECURITY_SEND = 0x81, 343240616Sjimharris NVME_OPC_SECURITY_RECEIVE = 0x82, 344240616Sjimharris}; 345240616Sjimharris 346240616Sjimharris/* nvme nvm opcodes */ 347240616Sjimharrisenum nvme_nvm_opcode { 348240616Sjimharris NVME_OPC_FLUSH = 0x00, 349240616Sjimharris NVME_OPC_WRITE = 0x01, 350240616Sjimharris NVME_OPC_READ = 0x02, 351240616Sjimharris /* 0x03 - reserved */ 352240616Sjimharris NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 353240616Sjimharris NVME_OPC_COMPARE = 0x05, 354240616Sjimharris /* 0x06-0x07 - reserved */ 355240616Sjimharris NVME_OPC_DATASET_MANAGEMENT = 0x09, 356240616Sjimharris}; 357240616Sjimharris 358240616Sjimharrisenum nvme_feature { 359240616Sjimharris /* 0x00 - reserved */ 360240616Sjimharris NVME_FEAT_ARBITRATION = 0x01, 361240616Sjimharris NVME_FEAT_POWER_MANAGEMENT = 0x02, 362240616Sjimharris NVME_FEAT_LBA_RANGE_TYPE = 0x03, 363240616Sjimharris NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 364240616Sjimharris NVME_FEAT_ERROR_RECOVERY = 0x05, 365240616Sjimharris NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 366240616Sjimharris NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 367240616Sjimharris NVME_FEAT_INTERRUPT_COALESCING = 0x08, 368240616Sjimharris NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 369240616Sjimharris NVME_FEAT_WRITE_ATOMICITY = 0x0A, 370248737Sjimharris NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 371240616Sjimharris /* 0x0C-0x7F - reserved */ 372240616Sjimharris NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 373240616Sjimharris /* 0x81-0xBF - command set specific (reserved) */ 374240616Sjimharris /* 0xC0-0xFF - vendor specific */ 375240616Sjimharris}; 376240616Sjimharris 377240616Sjimharrisenum nvme_dsm_attribute { 378240616Sjimharris NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 379240616Sjimharris NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 380240616Sjimharris NVME_DSM_ATTR_DEALLOCATE = 0x4, 381240616Sjimharris}; 382240616Sjimharris 383240616Sjimharrisstruct nvme_controller_data { 384240616Sjimharris 385240616Sjimharris /* bytes 0-255: controller capabilities and features */ 386240616Sjimharris 387240616Sjimharris /** pci vendor id */ 388240616Sjimharris uint16_t vid; 389240616Sjimharris 390240616Sjimharris /** pci subsystem vendor id */ 391240616Sjimharris uint16_t ssvid; 392240616Sjimharris 393240616Sjimharris /** serial number */ 394240616Sjimharris int8_t sn[20]; 395240616Sjimharris 396240616Sjimharris /** model number */ 397240616Sjimharris int8_t mn[40]; 398240616Sjimharris 399240616Sjimharris /** firmware revision */ 400240616Sjimharris uint8_t fr[8]; 401240616Sjimharris 402240616Sjimharris /** recommended arbitration burst */ 403240616Sjimharris uint8_t rab; 404240616Sjimharris 405240616Sjimharris /** ieee oui identifier */ 406240616Sjimharris uint8_t ieee[3]; 407240616Sjimharris 408240616Sjimharris /** multi-interface capabilities */ 409240616Sjimharris uint8_t mic; 410240616Sjimharris 411240616Sjimharris /** maximum data transfer size */ 412240616Sjimharris uint8_t mdts; 413240616Sjimharris 414240616Sjimharris uint8_t reserved1[178]; 415240616Sjimharris 416240616Sjimharris /* bytes 256-511: admin command set attributes */ 417240616Sjimharris 418240616Sjimharris /** optional admin command support */ 419240616Sjimharris struct { 420240616Sjimharris /* supports security send/receive commands */ 421240616Sjimharris uint16_t security : 1; 422240616Sjimharris 423240616Sjimharris /* supports format nvm command */ 424240616Sjimharris uint16_t format : 1; 425240616Sjimharris 426240616Sjimharris /* supports firmware activate/download commands */ 427240616Sjimharris uint16_t firmware : 1; 428240616Sjimharris 429240616Sjimharris uint16_t oacs_rsvd : 13; 430240616Sjimharris } __packed oacs; 431240616Sjimharris 432240616Sjimharris /** abort command limit */ 433240616Sjimharris uint8_t acl; 434240616Sjimharris 435240616Sjimharris /** asynchronous event request limit */ 436240616Sjimharris uint8_t aerl; 437240616Sjimharris 438240616Sjimharris /** firmware updates */ 439240616Sjimharris struct { 440240616Sjimharris /* first slot is read-only */ 441240616Sjimharris uint8_t slot1_ro : 1; 442240616Sjimharris 443240616Sjimharris /* number of firmware slots */ 444240616Sjimharris uint8_t num_slots : 3; 445240616Sjimharris 446240616Sjimharris uint8_t frmw_rsvd : 4; 447240616Sjimharris } __packed frmw; 448240616Sjimharris 449240616Sjimharris /** log page attributes */ 450240616Sjimharris struct { 451240616Sjimharris /* per namespace smart/health log page */ 452240616Sjimharris uint8_t ns_smart : 1; 453240616Sjimharris 454240616Sjimharris uint8_t lpa_rsvd : 7; 455240616Sjimharris } __packed lpa; 456240616Sjimharris 457240616Sjimharris /** error log page entries */ 458240616Sjimharris uint8_t elpe; 459240616Sjimharris 460240616Sjimharris /** number of power states supported */ 461240616Sjimharris uint8_t npss; 462240616Sjimharris 463240616Sjimharris /** admin vendor specific command configuration */ 464240616Sjimharris struct { 465240616Sjimharris /* admin vendor specific commands use spec format */ 466240616Sjimharris uint8_t spec_format : 1; 467240616Sjimharris 468240616Sjimharris uint8_t avscc_rsvd : 7; 469240616Sjimharris } __packed avscc; 470240616Sjimharris 471240616Sjimharris uint8_t reserved2[247]; 472240616Sjimharris 473240616Sjimharris /* bytes 512-703: nvm command set attributes */ 474240616Sjimharris 475240616Sjimharris /** submission queue entry size */ 476240616Sjimharris struct { 477240616Sjimharris uint8_t min : 4; 478240616Sjimharris uint8_t max : 4; 479240616Sjimharris } __packed sqes; 480240616Sjimharris 481240616Sjimharris /** completion queue entry size */ 482240616Sjimharris struct { 483240616Sjimharris uint8_t min : 4; 484240616Sjimharris uint8_t max : 4; 485240616Sjimharris } __packed cqes; 486240616Sjimharris 487240616Sjimharris uint8_t reserved3[2]; 488240616Sjimharris 489240616Sjimharris /** number of namespaces */ 490240616Sjimharris uint32_t nn; 491240616Sjimharris 492240616Sjimharris /** optional nvm command support */ 493240616Sjimharris struct { 494240616Sjimharris uint16_t compare : 1; 495240616Sjimharris uint16_t write_unc : 1; 496240616Sjimharris uint16_t dsm: 1; 497240616Sjimharris uint16_t reserved: 13; 498240616Sjimharris } __packed oncs; 499240616Sjimharris 500240616Sjimharris /** fused operation support */ 501240616Sjimharris uint16_t fuses; 502240616Sjimharris 503240616Sjimharris /** format nvm attributes */ 504240616Sjimharris uint8_t fna; 505240616Sjimharris 506240616Sjimharris /** volatile write cache */ 507240616Sjimharris struct { 508240616Sjimharris uint8_t present : 1; 509240616Sjimharris uint8_t reserved : 7; 510240616Sjimharris } __packed vwc; 511240616Sjimharris 512240616Sjimharris /* TODO: flesh out remaining nvm command set attributes */ 513240616Sjimharris uint8_t reserved4[178]; 514240616Sjimharris 515240616Sjimharris /* bytes 704-2047: i/o command set attributes */ 516240616Sjimharris uint8_t reserved5[1344]; 517240616Sjimharris 518240616Sjimharris /* bytes 2048-3071: power state descriptors */ 519240616Sjimharris uint8_t reserved6[1024]; 520240616Sjimharris 521240616Sjimharris /* bytes 3072-4095: vendor specific */ 522240616Sjimharris uint8_t reserved7[1024]; 523240671Sjimharris} __packed __aligned(4); 524240616Sjimharris 525240616Sjimharrisstruct nvme_namespace_data { 526240616Sjimharris 527240616Sjimharris /** namespace size */ 528240616Sjimharris uint64_t nsze; 529240616Sjimharris 530240616Sjimharris /** namespace capacity */ 531240616Sjimharris uint64_t ncap; 532240616Sjimharris 533240616Sjimharris /** namespace utilization */ 534240616Sjimharris uint64_t nuse; 535240616Sjimharris 536240616Sjimharris /** namespace features */ 537240616Sjimharris struct { 538240616Sjimharris /** thin provisioning */ 539240616Sjimharris uint8_t thin_prov : 1; 540240616Sjimharris uint8_t reserved1 : 7; 541240616Sjimharris } __packed nsfeat; 542240616Sjimharris 543240616Sjimharris /** number of lba formats */ 544240616Sjimharris uint8_t nlbaf; 545240616Sjimharris 546240616Sjimharris /** formatted lba size */ 547240616Sjimharris struct { 548240616Sjimharris uint8_t format : 4; 549240616Sjimharris uint8_t extended : 1; 550240616Sjimharris uint8_t reserved2 : 3; 551240616Sjimharris } __packed flbas; 552240616Sjimharris 553240616Sjimharris /** metadata capabilities */ 554240616Sjimharris struct { 555240616Sjimharris /* metadata can be transferred as part of data prp list */ 556240616Sjimharris uint8_t extended : 1; 557240616Sjimharris 558240616Sjimharris /* metadata can be transferred with separate metadata pointer */ 559240616Sjimharris uint8_t pointer : 1; 560240616Sjimharris 561240616Sjimharris uint8_t reserved3 : 6; 562240616Sjimharris } __packed mc; 563240616Sjimharris 564240616Sjimharris /** end-to-end data protection capabilities */ 565240616Sjimharris struct { 566240616Sjimharris /* protection information type 1 */ 567240616Sjimharris uint8_t pit1 : 1; 568240616Sjimharris 569240616Sjimharris /* protection information type 2 */ 570240616Sjimharris uint8_t pit2 : 1; 571240616Sjimharris 572240616Sjimharris /* protection information type 3 */ 573240616Sjimharris uint8_t pit3 : 1; 574240616Sjimharris 575240616Sjimharris /* first eight bytes of metadata */ 576240616Sjimharris uint8_t md_start : 1; 577240616Sjimharris 578240616Sjimharris /* last eight bytes of metadata */ 579240616Sjimharris uint8_t md_end : 1; 580240616Sjimharris } __packed dpc; 581240616Sjimharris 582240616Sjimharris /** end-to-end data protection type settings */ 583240616Sjimharris struct { 584240616Sjimharris /* protection information type */ 585240616Sjimharris uint8_t pit : 3; 586240616Sjimharris 587240616Sjimharris /* 1 == protection info transferred at start of metadata */ 588240616Sjimharris /* 0 == protection info transferred at end of metadata */ 589240616Sjimharris uint8_t md_start : 1; 590240616Sjimharris 591240616Sjimharris uint8_t reserved4 : 4; 592240616Sjimharris } __packed dps; 593240616Sjimharris 594240616Sjimharris uint8_t reserved5[98]; 595240616Sjimharris 596240616Sjimharris /** lba format support */ 597240616Sjimharris struct { 598240616Sjimharris /** metadata size */ 599240616Sjimharris uint32_t ms : 16; 600240616Sjimharris 601240616Sjimharris /** lba data size */ 602240616Sjimharris uint32_t lbads : 8; 603240616Sjimharris 604240616Sjimharris /** relative performance */ 605240616Sjimharris uint32_t rp : 2; 606240616Sjimharris 607240616Sjimharris uint32_t reserved6 : 6; 608240616Sjimharris } __packed lbaf[16]; 609240616Sjimharris 610240616Sjimharris uint8_t reserved6[192]; 611240616Sjimharris 612240616Sjimharris uint8_t vendor_specific[3712]; 613240671Sjimharris} __packed __aligned(4); 614240616Sjimharris 615240616Sjimharrisenum nvme_log_page { 616240616Sjimharris 617240616Sjimharris /* 0x00 - reserved */ 618240616Sjimharris NVME_LOG_ERROR = 0x01, 619240616Sjimharris NVME_LOG_HEALTH_INFORMATION = 0x02, 620240616Sjimharris NVME_LOG_FIRMWARE_SLOT = 0x03, 621240616Sjimharris /* 0x04-0x7F - reserved */ 622240616Sjimharris /* 0x80-0xBF - I/O command set specific */ 623240616Sjimharris /* 0xC0-0xFF - vendor specific */ 624240616Sjimharris}; 625240616Sjimharris 626248757Sjimharrisstruct nvme_error_information_entry { 627248757Sjimharris 628248757Sjimharris uint64_t error_count; 629248757Sjimharris uint16_t sqid; 630248757Sjimharris uint16_t cid; 631248757Sjimharris struct nvme_status status; 632248757Sjimharris uint16_t error_location; 633248757Sjimharris uint64_t lba; 634248757Sjimharris uint32_t nsid; 635248757Sjimharris uint8_t vendor_specific; 636248757Sjimharris uint8_t reserved[35]; 637248757Sjimharris} __packed __aligned(4); 638248757Sjimharris 639240616Sjimharrisunion nvme_critical_warning_state { 640240616Sjimharris 641240616Sjimharris uint8_t raw; 642240616Sjimharris 643240616Sjimharris struct { 644240616Sjimharris uint8_t available_spare : 1; 645240616Sjimharris uint8_t temperature : 1; 646240616Sjimharris uint8_t device_reliability : 1; 647240616Sjimharris uint8_t read_only : 1; 648240616Sjimharris uint8_t volatile_memory_backup : 1; 649240616Sjimharris uint8_t reserved : 3; 650240616Sjimharris } __packed bits; 651240616Sjimharris} __packed; 652240616Sjimharris 653240616Sjimharrisstruct nvme_health_information_page { 654240616Sjimharris 655240616Sjimharris union nvme_critical_warning_state critical_warning; 656240616Sjimharris 657240616Sjimharris uint16_t temperature; 658240616Sjimharris uint8_t available_spare; 659240616Sjimharris uint8_t available_spare_threshold; 660240616Sjimharris uint8_t percentage_used; 661240616Sjimharris 662240616Sjimharris uint8_t reserved[26]; 663240616Sjimharris 664240616Sjimharris /* 665240616Sjimharris * Note that the following are 128-bit values, but are 666240616Sjimharris * defined as an array of 2 64-bit values. 667240616Sjimharris */ 668240616Sjimharris /* Data Units Read is always in 512-byte units. */ 669240616Sjimharris uint64_t data_units_read[2]; 670240616Sjimharris /* Data Units Written is always in 512-byte units. */ 671240616Sjimharris uint64_t data_units_written[2]; 672240616Sjimharris /* For NVM command set, this includes Compare commands. */ 673240616Sjimharris uint64_t host_read_commands[2]; 674240616Sjimharris uint64_t host_write_commands[2]; 675240616Sjimharris /* Controller Busy Time is reported in minutes. */ 676240616Sjimharris uint64_t controller_busy_time[2]; 677240616Sjimharris uint64_t power_cycles[2]; 678240616Sjimharris uint64_t power_on_hours[2]; 679240616Sjimharris uint64_t unsafe_shutdowns[2]; 680240616Sjimharris uint64_t media_errors[2]; 681240616Sjimharris uint64_t num_error_info_log_entries[2]; 682240616Sjimharris 683240616Sjimharris uint8_t reserved2[320]; 684240671Sjimharris} __packed __aligned(4); 685240616Sjimharris 686248758Sjimharrisstruct nvme_firmware_page { 687248758Sjimharris 688248758Sjimharris struct { 689248758Sjimharris uint8_t slot : 3; /* slot for current FW */ 690248758Sjimharris uint8_t reserved : 5; 691248758Sjimharris } __packed afi; 692248758Sjimharris 693248758Sjimharris uint8_t reserved[7]; 694248758Sjimharris uint64_t revision[7]; /* revisions for 7 slots */ 695248758Sjimharris uint8_t reserved2[448]; 696248758Sjimharris} __packed __aligned(4); 697248758Sjimharris 698240616Sjimharris#define NVME_TEST_MAX_THREADS 128 699240616Sjimharris 700240616Sjimharrisstruct nvme_io_test { 701240616Sjimharris 702240616Sjimharris enum nvme_nvm_opcode opc; 703240616Sjimharris uint32_t size; 704240616Sjimharris uint32_t time; /* in seconds */ 705240616Sjimharris uint32_t num_threads; 706240616Sjimharris uint32_t flags; 707240616Sjimharris uint32_t io_completed[NVME_TEST_MAX_THREADS]; 708240616Sjimharris}; 709240616Sjimharris 710240616Sjimharrisenum nvme_io_test_flags { 711240616Sjimharris 712240616Sjimharris /* 713240616Sjimharris * Specifies whether dev_refthread/dev_relthread should be 714240616Sjimharris * called during NVME_BIO_TEST. Ignored for other test 715240616Sjimharris * types. 716240616Sjimharris */ 717240616Sjimharris NVME_TEST_FLAG_REFTHREAD = 0x1, 718240616Sjimharris}; 719240616Sjimharris 720249421Sjimharrisstruct nvme_pt_command { 721249421Sjimharris 722249421Sjimharris /* 723249421Sjimharris * cmd is used to specify a passthrough command to a controller or 724249421Sjimharris * namespace. 725249421Sjimharris * 726249421Sjimharris * The following fields from cmd may be specified by the caller: 727249421Sjimharris * * opc (opcode) 728249421Sjimharris * * nsid (namespace id) - for admin commands only 729249421Sjimharris * * cdw10-cdw15 730249421Sjimharris * 731249421Sjimharris * Remaining fields must be set to 0 by the caller. 732249421Sjimharris */ 733249421Sjimharris struct nvme_command cmd; 734249421Sjimharris 735249421Sjimharris /* 736249421Sjimharris * cpl returns completion status for the passthrough command 737249421Sjimharris * specified by cmd. 738249421Sjimharris * 739249421Sjimharris * The following fields will be filled out by the driver, for 740249421Sjimharris * consumption by the caller: 741249421Sjimharris * * cdw0 742249421Sjimharris * * status (except for phase) 743249421Sjimharris * 744249421Sjimharris * Remaining fields will be set to 0 by the driver. 745249421Sjimharris */ 746249421Sjimharris struct nvme_completion cpl; 747249421Sjimharris 748249421Sjimharris /* buf is the data buffer associated with this passthrough command. */ 749249421Sjimharris void * buf; 750249421Sjimharris 751249421Sjimharris /* 752249421Sjimharris * len is the length of the data buffer associated with this 753249421Sjimharris * passthrough command. 754249421Sjimharris */ 755249421Sjimharris uint32_t len; 756249421Sjimharris 757249421Sjimharris /* 758249421Sjimharris * is_read = 1 if the passthrough command will read data into the 759249421Sjimharris * supplied buffer. 760249421Sjimharris * 761249421Sjimharris * is_read = 0 if the passthrough command will write data into the 762249421Sjimharris * supplied buffer. 763249421Sjimharris */ 764249421Sjimharris uint32_t is_read; 765249421Sjimharris 766249421Sjimharris /* 767249421Sjimharris * driver_lock is used by the driver only. It must be set to 0 768249421Sjimharris * by the caller. 769249421Sjimharris */ 770249421Sjimharris struct mtx * driver_lock; 771249421Sjimharris}; 772249421Sjimharris 773248756Sjimharris#define nvme_completion_is_error(cpl) \ 774248756Sjimharris ((cpl)->status.sc != 0 || (cpl)->status.sct != 0) 775248756Sjimharris 776240616Sjimharris#ifdef _KERNEL 777240616Sjimharris 778240616Sjimharrisstruct bio; 779240616Sjimharris 780240616Sjimharrisstruct nvme_namespace; 781248738Sjimharrisstruct nvme_controller; 782240616Sjimharrisstruct nvme_consumer; 783240616Sjimharris 784240616Sjimharristypedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 785240616Sjimharris 786248738Sjimharristypedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 787248738Sjimharristypedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 788248760Sjimharristypedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 789248760Sjimharris uint32_t, void *, uint32_t); 790248767Sjimharristypedef void (*nvme_cons_fail_fn_t)(void *); 791248738Sjimharris 792240616Sjimharrisenum nvme_namespace_flags { 793240616Sjimharris NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 794240616Sjimharris NVME_NS_FLUSH_SUPPORTED = 0x2, 795240616Sjimharris}; 796240616Sjimharris 797249421Sjimharrisint nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 798249421Sjimharris struct nvme_pt_command *pt, 799249421Sjimharris uint32_t nsid, int is_user_buffer, 800249421Sjimharris int is_admin_cmd); 801249421Sjimharris 802248739Sjimharris/* Admin functions */ 803248739Sjimharrisvoid nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 804248739Sjimharris uint8_t feature, uint32_t cdw11, 805248739Sjimharris void *payload, uint32_t payload_size, 806248739Sjimharris nvme_cb_fn_t cb_fn, void *cb_arg); 807248739Sjimharrisvoid nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 808248739Sjimharris uint8_t feature, uint32_t cdw11, 809248739Sjimharris void *payload, uint32_t payload_size, 810248739Sjimharris nvme_cb_fn_t cb_fn, void *cb_arg); 811248740Sjimharrisvoid nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 812248740Sjimharris uint8_t log_page, uint32_t nsid, 813248740Sjimharris void *payload, uint32_t payload_size, 814248740Sjimharris nvme_cb_fn_t cb_fn, void *cb_arg); 815248739Sjimharris 816240616Sjimharris/* NVM I/O functions */ 817241657Sjimharrisint nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 818240616Sjimharris uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 819240616Sjimharris void *cb_arg); 820248977Sjimharrisint nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 821248977Sjimharris nvme_cb_fn_t cb_fn, void *cb_arg); 822241657Sjimharrisint nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 823240616Sjimharris uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 824240616Sjimharris void *cb_arg); 825248977Sjimharrisint nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 826248977Sjimharris nvme_cb_fn_t cb_fn, void *cb_arg); 827241657Sjimharrisint nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 828240616Sjimharris uint8_t num_ranges, nvme_cb_fn_t cb_fn, 829240616Sjimharris void *cb_arg); 830241657Sjimharrisint nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 831240616Sjimharris void *cb_arg); 832240616Sjimharris 833240616Sjimharris/* Registration functions */ 834248738Sjimharrisstruct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 835248738Sjimharris nvme_cons_ctrlr_fn_t ctrlr_fn, 836248767Sjimharris nvme_cons_async_fn_t async_fn, 837248767Sjimharris nvme_cons_fail_fn_t fail_fn); 838240616Sjimharrisvoid nvme_unregister_consumer(struct nvme_consumer *consumer); 839240616Sjimharris 840248738Sjimharris/* Controller helper functions */ 841248738Sjimharrisdevice_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 842248747Sjimharrisconst struct nvme_controller_data * 843248747Sjimharris nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 844248738Sjimharris 845240616Sjimharris/* Namespace helper functions */ 846240616Sjimharrisuint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 847240616Sjimharrisuint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 848240616Sjimharrisuint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 849240616Sjimharrisuint64_t nvme_ns_get_size(struct nvme_namespace *ns); 850240616Sjimharrisuint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 851240616Sjimharrisconst char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 852240616Sjimharrisconst char * nvme_ns_get_model_number(struct nvme_namespace *ns); 853248747Sjimharrisconst struct nvme_namespace_data * 854248747Sjimharris nvme_ns_get_data(struct nvme_namespace *ns); 855240616Sjimharris 856240616Sjimharrisint nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 857240616Sjimharris nvme_cb_fn_t cb_fn); 858240616Sjimharris 859240616Sjimharris#endif /* _KERNEL */ 860240616Sjimharris 861240616Sjimharris#endif /* __NVME_H__ */ 862