ncr53c500reg.h revision 139749
167468Snon/* $FreeBSD: head/sys/dev/ncv/ncr53c500reg.h 139749 2005-01-06 01:43:34Z imp $ */ 279697Snon/* $NecBSD: ncr53c500reg.h,v 1.5.14.1 2001/06/08 06:27:44 honda Exp $ */ 367468Snon/* $NetBSD$ */ 467468Snon 5139749Simp/*- 667468Snon * [NetBSD for NEC PC-98 series] 767468Snon * Copyright (c) 1995, 1996, 1997, 1998 867468Snon * NetBSD/pc98 porting staff. All rights reserved. 967468Snon * Copyright (c) 1995, 1996, 1997, 1998 1067468Snon * Naofumi HONDA. All rights reserved. 1167468Snon * Copyright (c) 1995, 1996, 1997, 1998 1267468Snon * Kouichi Matsuda. All rights reserved. 1367468Snon * 1467468Snon * Redistribution and use in source and binary forms, with or without 1567468Snon * modification, are permitted provided that the following conditions 1667468Snon * are met: 1767468Snon * 1. Redistributions of source code must retain the above copyright 1867468Snon * notice, this list of conditions and the following disclaimer. 1967468Snon * 2. Redistributions in binary form must reproduce the above copyright 2067468Snon * notice, this list of conditions and the following disclaimer in the 2167468Snon * documentation and/or other materials provided with the distribution. 2267468Snon * 3. The name of the author may not be used to endorse or promote products 2367468Snon * derived from this software without specific prior written permission. 2467468Snon * 2567468Snon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2667468Snon * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 2767468Snon * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 2867468Snon * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 2967468Snon * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 3067468Snon * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 3167468Snon * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3267468Snon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3367468Snon * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 3467468Snon * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3567468Snon * POSSIBILITY OF SUCH DAMAGE. 3667468Snon */ 3767468Snon 3867468Snon#ifndef _NCR53C500REG_H_ 3967468Snon#define _NCR53C500REG_H_ 4067468Snon 4167468Snon/* Control Register Set 0 */ 4267468Snon#define NCVIOSZ 0x10 4367468Snon 4467468Snon#define cr0_tclsb 0x00 /* RW - Transfer Count Low */ 4567468Snon#define cr0_tcmsb 0x01 /* RW - Transfer Count Mid */ 4667468Snon#define cr0_sfifo 0x02 /* RW - FIFO data */ 4767468Snon#define cr0_cmd 0x03 /* RW - Command (2 deep) */ 4867468Snon#define cr0_stat 0x04 /* RO - Status */ 4967468Snon#define cr0_dstid 0x04 /* WO - Select/Reselect Bus ID */ 5067468Snon#define cr0_istat 0x05 /* RO - Interrupt */ 5167468Snon#define cr0_srtout 0x05 /* WO - Select/Reselect Timeout */ 5267468Snon#define cr0_seq 0x06 /* RO - Sequence Step */ 5367468Snon#define cr0_period 0x06 /* WO - Synch Transfer Period */ 5467468Snon#define cr0_sffl 0x07 /* RO - FIFO FLags */ 5567468Snon#define cr0_offs 0x07 /* WO - Synch Ofset */ 5667468Snon#define cr0_cfg1 0x08 /* RW - Configuration #1 */ 5767468Snon#define cr0_clk 0x09 /* WO - Clock Conversion Factor */ 5867468Snon#define cr0_tst 0x0a /* WO - Test (Chip Test Only) */ 5967468Snon#define cr0_cfg2 0x0b /* RW - Configuration #2 */ 6067468Snon#define cr0_cfg3 0x0c /* RW - Configuration #3 */ 6167468Snon#define cr0_cfg4 0x0d /* RW - Configuration #4 */ 6267468Snon#define cr0_tchsb 0x0e /* RW - Transfer Count High */ 6367468Snon#define cr0_fifo_bottom 0x0f /* WO - FIFO bottom */ 6467468Snon 6567468Snon/* Control Register Set 1 */ 6667468Snon#define cr1_jumper 0x00 /* RW - Jumper Sense Port */ 6767468Snon#define cr1_sram_ptr 0x01 /* RW - SRAM Address Pointer */ 6867468Snon#define cr1_sram_data 0x02 /* RW - SRAM Data */ 6967468Snon#define cr1_fdata 0x04 /* RW - PIO FIFO */ 7067468Snon#define cr1_fstat 0x08 /* RW - PIO Status */ 7167468Snon#define cr1_atacmd 0x09 /* RW - ATA Command/Status */ 7267468Snon#define cr1_ataerr 0x0a /* RW - ATA Features/Error */ 7367468Snon#define cr1_pflag 0x0b /* RW - PIO Flag Interrupt Enable */ 7467468Snon#define cr1_cfg5 0x0d /* RW - Configuration #5 */ 7567468Snon#define cr1_sig 0x0e /* RO - Signature */ 7667468Snon#define cr1_cfg6 0x0f /* RW - Configuration #6 */ 7767468Snon 7867468Snon/* atacmd (MPS110 ONLY) */ 7967468Snon#define ATACMD_POWDOWN 0x2d 8067468Snon#define ATACMD_ENGAGE 0x24 8167468Snon 8267468Snon/* cr0_sffl regster */ 8367468Snon#define CR0_SFFLR_BMASK 0x1f /* scsi fifo byte mask */ 8467468Snon 8567468Snon/* cfg4 */ 8667468Snon#define C4_ANE 0x04 8767468Snon 8867468Snon/* cfg2 */ 8967468Snon#define C2_SCSI2 0x08 /* SCSI-2 Enable */ 9067468Snon#define C2_FE 0x40 /* Features Enable */ 9167468Snon 9267468Snon/* cfg1 */ 9367468Snon#define C1_SLOW 0x80 /* Slow Cable Mode */ 9467468Snon#define C1_SRR 0x40 /* SCSI Reset Rep Int Dis */ 9567468Snon#define C1_PARENB 0x10 /* Enable Parity Check */ 9667468Snon 9767468Snon/* clk factor */ 9867468Snon#define CLK_40M_F 0x00 9967468Snon#define CLK_25M_F 0x05 10067468Snon#define CLK_30M_F 0x06 10167468Snon#define CLK_35M_F 0x07 10267468Snon 10367468Snon/* interrupt status register */ 10467468Snon#define INTR_SBR 0x80 /* SCSI Bus Reset */ 10567468Snon#define INTR_ILL 0x40 /* Illegal Command */ 10667468Snon#define INTR_DIS 0x20 /* Disconnect */ 10767468Snon#define INTR_BS 0x10 /* Bus Service */ 10867468Snon#define INTR_FC 0x08 /* Function Complete */ 10967468Snon#define INTR_RESEL 0x04 /* Reselected */ 11067468Snon#define INTR_SELATN 0x02 /* Select with ATN */ 11167468Snon#define INTR_SEL 0x01 /* Selected */ 11267468Snon#define INTR_RESELECT (INTR_RESEL | INTR_FC) 11367468Snon 11467468Snon/* status register */ 11567468Snon#define STAT_INT 0x80 /* Interrupt */ 11667468Snon#define STAT_GE 0x40 /* Gross Error */ 11767468Snon#define STAT_PE 0x20 /* Parity Error */ 11867468Snon#define STAT_TC 0x10 /* Terminal Count */ 11967468Snon 12067468Snon/* phase bits */ 12167468Snon#define IOI 0x01 12267468Snon#define CDI 0x02 12367468Snon#define MSGI 0x04 12467468Snon 12567468Snon/* Information transfer phases */ 12667468Snon#define DATA_OUT_PHASE (0) 12767468Snon#define DATA_IN_PHASE (IOI) 12867468Snon#define COMMAND_PHASE (CDI) 12967468Snon#define STATUS_PHASE (CDI|IOI) 13067468Snon#define MESSAGE_OUT_PHASE (MSGI|CDI) 13167468Snon#define MESSAGE_IN_PHASE (MSGI|CDI|IOI) 13267468Snon 13367468Snon#define PHASE_MASK (MSGI|CDI|IOI) 13467468Snon 13567468Snon/* fifo status register */ 13667468Snon#define FIFO_SMASK 0x1e 13767468Snon#define FIFO_E 0x10 /* fifo empty */ 13867468Snon#define FIFO_B 0x00 /* there exists any */ 13967468Snon#define FIFO_1 0x08 /* 1/3 <= bytes < 2/3 */ 14067468Snon#define FIFO_2 0x04 /* 2/3 <= bytes < full */ 14167468Snon#define FIFO_F 0x02 /* full */ 14267468Snon#define FIFO_EN 0x01 /* fifo direction */ 14367468Snon#define FIFO_BRK 0x40 /* phase miss */ 14467468Snon 14567468Snon#define FIFO_F_SZ 128 14667468Snon#define FIFO_1_SZ 44 14767468Snon#define FIFO_2_SZ 84 14867468Snon 14967468Snon/* pflags */ 15067468Snon#define PFR_WRITE 0x01 15167468Snon 15267468Snon/* Commands */ 15367468Snon#define CMD_DMA 0x80 /* DMA Bit */ 15467468Snon#define CMD_NOP 0x00 /* No Operation */ 15567468Snon#define CMD_FLUSH 0x01 /* Flush FIFO */ 15667468Snon#define CMD_RSTCHIP 0x02 /* Reset Chip */ 15767468Snon#define CMD_RSTSCSI 0x03 /* Reset SCSI Bus */ 15867468Snon#define CMD_RESEL 0x40 /* Reselect Sequence */ 15967468Snon#define CMD_SELNATN 0x41 /* Select without ATN */ 16067468Snon#define CMD_SELATN 0x42 /* Select with ATN */ 16167468Snon#define CMD_SELATNS 0x43 /* Select with ATN & Stop */ 16267468Snon#define CMD_ENSEL 0x44 /* Enable (Re)Selection */ 16367468Snon#define CMD_DISSEL 0x45 /* Disable (Re)Selection */ 16467468Snon#define CMD_SELATN3 0x46 /* Select with ATN3 */ 16567468Snon#define CMD_RESEL3 0x47 /* Reselect3 Sequence */ 16667468Snon#define CMD_SNDMSG 0x20 /* Send Message */ 16767468Snon#define CMD_SNDSTAT 0x21 /* Send Status */ 16867468Snon#define CMD_SNDDATA 0x22 /* Send Data */ 16967468Snon#define CMD_DISCSEQ 0x23 /* Disconnect Sequence */ 17067468Snon#define CMD_TERMSEQ 0x24 /* Terminate Sequence */ 17167468Snon#define CMD_TCCS 0x25 /* Target Command Comp Seq */ 17267468Snon#define CMD_DISC 0x27 /* Disconnect */ 17367468Snon#define CMD_RECMSG 0x28 /* Receive Message */ 17467468Snon#define CMD_RECCMD 0x29 /* Receive Command */ 17567468Snon#define CMD_RECDATA 0x2a /* Receive Data */ 17667468Snon#define CMD_RECCSEQ 0x2b /* Receive Command Sequence */ 17767468Snon#define CMD_ABORT 0x04 /* Target Abort DMA */ 17867468Snon#define CMD_TRANS 0x10 /* Transfer Information */ 17967468Snon#define CMD_ICCS 0x11 /* Initiator Cmd Comp Seq */ 18067468Snon#define CMD_MSGOK 0x12 /* Message Accepted */ 18167468Snon#define CMD_TRPAD 0x18 /* Transfer Pad */ 18267468Snon#define CMD_SETATN 0x1a /* Set ATN */ 18367468Snon#define CMD_RSTATN 0x1b /* Reset ATN */ 18467468Snon 18567468Snon/* Default timeout */ 18667468Snon#define SEL_TOUT 0xa3 18767468Snon#endif /* !_NCR53C500REG_H_ */ 188