if_mwl_pci.c revision 198366
1267843Sdelphij/*-
2267843Sdelphij * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
3330569Sgordon * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
4267843Sdelphij * All rights reserved.
5267843Sdelphij *
6267843Sdelphij * Redistribution and use in source and binary forms, with or without
7267843Sdelphij * modification, are permitted provided that the following conditions
8267843Sdelphij * are met:
9267843Sdelphij * 1. Redistributions of source code must retain the above copyright
10267843Sdelphij *    notice, this list of conditions and the following disclaimer,
11267843Sdelphij *    without modification.
12267843Sdelphij * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13267843Sdelphij *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14330569Sgordon *    redistribution must be conditioned upon including a substantially
15330569Sgordon *    similar Disclaimer requirement for further binary redistribution.
16330569Sgordon *
17267843Sdelphij * NO WARRANTY
18267843Sdelphij * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19267843Sdelphij * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20267843Sdelphij * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21267843Sdelphij * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22330569Sgordon * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23330569Sgordon * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24330569Sgordon * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25330569Sgordon * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26330569Sgordon * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27330569Sgordon * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28330569Sgordon * THE POSSIBILITY OF SUCH DAMAGES.
29267843Sdelphij */
30267843Sdelphij
31267843Sdelphij#include <sys/cdefs.h>
32267843Sdelphij#ifdef __FreeBSD__
33267843Sdelphij__FBSDID("$FreeBSD: head/sys/dev/mwl/if_mwl_pci.c 198366 2009-10-22 12:48:17Z rpaulo $");
34267843Sdelphij#endif
35330569Sgordon
36267843Sdelphij/*
37267843Sdelphij * PCI front-end for the Marvell Wireless LAN controller driver.
38330569Sgordon */
39267843Sdelphij
40267843Sdelphij#include <sys/param.h>
41330569Sgordon#include <sys/systm.h>
42267843Sdelphij#include <sys/module.h>
43267843Sdelphij#include <sys/kernel.h>
44267843Sdelphij#include <sys/lock.h>
45267843Sdelphij#include <sys/mutex.h>
46330569Sgordon#include <sys/errno.h>
47330569Sgordon
48330569Sgordon#include <machine/bus.h>
49330569Sgordon#include <machine/resource.h>
50330569Sgordon#include <sys/bus.h>
51330569Sgordon#include <sys/rman.h>
52330569Sgordon
53330569Sgordon#include <sys/socket.h>
54267843Sdelphij
55330569Sgordon#include <net/if.h>
56330569Sgordon#include <net/if_media.h>
57330569Sgordon#include <net/if_arp.h>
58330569Sgordon
59330569Sgordon#include <net80211/ieee80211_var.h>
60330569Sgordon
61330569Sgordon#include <dev/mwl/if_mwlvar.h>
62330569Sgordon
63330569Sgordon#include <dev/pci/pcivar.h>
64330569Sgordon#include <dev/pci/pcireg.h>
65330569Sgordon
66330569Sgordon/*
67330569Sgordon * PCI glue.
68330569Sgordon */
69330569Sgordon
70330569Sgordonstruct mwl_pci_softc {
71330569Sgordon	struct mwl_softc	sc_sc;
72330569Sgordon	struct resource		*sc_sr0;	/* BAR0 memory resource */
73330569Sgordon	struct resource		*sc_sr1;	/* BAR1 memory resource */
74330569Sgordon	struct resource		*sc_irq;	/* irq resource */
75330569Sgordon	void			*sc_ih;		/* interrupt handler */
76330569Sgordon};
77330569Sgordon
78330569Sgordon#define	BS_BAR0	0x10
79330569Sgordon#define	BS_BAR1	0x14
80330569Sgordon
81330569Sgordonstruct mwl_pci_ident {
82330569Sgordon	uint16_t	vendor;
83330569Sgordon	uint16_t	device;
84330569Sgordon	const char	*name;
85330569Sgordon};
86330569Sgordon
87330569Sgordonstatic const struct mwl_pci_ident mwl_pci_ids[] = {
88330569Sgordon	{ 0x11ab, 0x2a02, "Marvell 88W8363" },
89330569Sgordon	{ 0x11ab, 0x2a03, "Marvell 88W8363" },
90330569Sgordon	{ 0x11ab, 0x2a0a, "Marvell 88W8363" },
91330569Sgordon	{ 0x11ab, 0x2a0b, "Marvell 88W8363" },
92330569Sgordon	{ 0x11ab, 0x2a0c, "Marvell 88W8363" },
93330569Sgordon	{ 0x11ab, 0x2a21, "Marvell 88W8363" },
94330569Sgordon	{ 0x11ab, 0x2a24, "Marvell 88W8363" },
95330569Sgordon
96330569Sgordon	{ 0, 0, NULL }
97330569Sgordon};
98330569Sgordon
99330569Sgordonconst static struct mwl_pci_ident *
100330569Sgordonmwl_pci_lookup(int vendor, int device)
101330569Sgordon{
102330569Sgordon	const struct mwl_pci_ident *ident;
103330569Sgordon
104330569Sgordon	for (ident = mwl_pci_ids; ident->name != NULL; ident++)
105330569Sgordon		if (vendor == ident->vendor && device == ident->device)
106330569Sgordon			return ident;
107330569Sgordon	return NULL;
108330569Sgordon}
109330569Sgordon
110330569Sgordonstatic int
111330569Sgordonmwl_pci_probe(device_t dev)
112330569Sgordon{
113330569Sgordon	const struct mwl_pci_ident *ident;
114330569Sgordon
115330569Sgordon	ident = mwl_pci_lookup(pci_get_vendor(dev), pci_get_device(dev));
116330569Sgordon	if (ident != NULL) {
117330569Sgordon		device_set_desc(dev, ident->name);
118330569Sgordon		return BUS_PROBE_DEFAULT;
119330569Sgordon	}
120330569Sgordon	return ENXIO;
121330569Sgordon}
122330569Sgordon
123330569Sgordonstatic u_int32_t
124330569Sgordonmwl_pci_setup(device_t dev)
125330569Sgordon{
126330569Sgordon	u_int32_t cmd;
127330569Sgordon
128330569Sgordon	/*
129330569Sgordon	 * Enable memory mapping and bus mastering.
130330569Sgordon	 */
131330569Sgordon	cmd = pci_read_config(dev, PCIR_COMMAND, 4);
132330569Sgordon	cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
133330569Sgordon	pci_write_config(dev, PCIR_COMMAND, cmd, 4);
134330569Sgordon	cmd = pci_read_config(dev, PCIR_COMMAND, 4);
135330569Sgordon	if ((cmd & PCIM_CMD_MEMEN) == 0) {
136330569Sgordon		device_printf(dev, "failed to enable memory mapping\n");
137330569Sgordon		return 0;
138330569Sgordon	}
139330569Sgordon	if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
140330569Sgordon		device_printf(dev, "failed to enable bus mastering\n");
141330569Sgordon		return 0;
142330569Sgordon	}
143330569Sgordon	return 1;
144330569Sgordon}
145330569Sgordon
146330569Sgordonstatic int
147330569Sgordonmwl_pci_attach(device_t dev)
148330569Sgordon{
149330569Sgordon	struct mwl_pci_softc *psc = device_get_softc(dev);
150330569Sgordon	struct mwl_softc *sc = &psc->sc_sc;
151330569Sgordon	int rid, error = ENXIO;
152330569Sgordon
153330569Sgordon	sc->sc_dev = dev;
154330569Sgordon
155330569Sgordon	/*
156330569Sgordon	 * Enable memory mapping and bus mastering.
157330569Sgordon	 */
158330569Sgordon	if (!mwl_pci_setup(dev))
159330569Sgordon		return 0;
160330569Sgordon	/*
161330569Sgordon	 * Setup memory-mapping of PCI registers.
162330569Sgordon	 */
163330569Sgordon	rid = BS_BAR0;
164330569Sgordon	psc->sc_sr0 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
165330569Sgordon					    RF_ACTIVE);
166330569Sgordon	if (psc->sc_sr0 == NULL) {
167330569Sgordon		device_printf(dev, "cannot map BAR0 register space\n");
168330569Sgordon		goto bad;
169330569Sgordon	}
170330569Sgordon	rid = BS_BAR1;
171330569Sgordon	psc->sc_sr1 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
172330569Sgordon					    RF_ACTIVE);
173330569Sgordon	if (psc->sc_sr1 == NULL) {
174330569Sgordon		device_printf(dev, "cannot map BAR1 register space\n");
175330569Sgordon		goto bad1;
176330569Sgordon	}
177330569Sgordon	sc->sc_invalid = 1;
178330569Sgordon
179330569Sgordon	/*
180330569Sgordon	 * Arrange interrupt line.
181330569Sgordon	 */
182330569Sgordon	rid = 0;
183330569Sgordon	psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
184330569Sgordon					     RF_SHAREABLE|RF_ACTIVE);
185330569Sgordon	if (psc->sc_irq == NULL) {
186330569Sgordon		device_printf(dev, "could not map interrupt\n");
187330569Sgordon		goto bad2;
188330569Sgordon	}
189330569Sgordon	if (bus_setup_intr(dev, psc->sc_irq,
190330569Sgordon			   INTR_TYPE_NET | INTR_MPSAFE,
191330569Sgordon			   NULL, mwl_intr, sc, &psc->sc_ih)) {
192330569Sgordon		device_printf(dev, "could not establish interrupt\n");
193330569Sgordon		goto bad3;
194330569Sgordon	}
195330569Sgordon
196330569Sgordon	/*
197330569Sgordon	 * Setup DMA descriptor area.
198330569Sgordon	 */
199330569Sgordon	if (bus_dma_tag_create(bus_get_dma_tag(dev),	/* parent */
200330569Sgordon			       1, 0,			/* alignment, bounds */
201330569Sgordon			       BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
202330569Sgordon			       BUS_SPACE_MAXADDR,	/* highaddr */
203330569Sgordon			       NULL, NULL,		/* filter, filterarg */
204330569Sgordon			       BUS_SPACE_MAXADDR,	/* maxsize */
205330569Sgordon			       MWL_TXDESC,		/* nsegments */
206267843Sdelphij			       BUS_SPACE_MAXADDR,	/* maxsegsize */
207267843Sdelphij			       0,			/* flags */
208267843Sdelphij			       NULL,			/* lockfunc */
209267843Sdelphij			       NULL,			/* lockarg */
210267843Sdelphij			       &sc->sc_dmat)) {
211330569Sgordon		device_printf(dev, "cannot allocate DMA tag\n");
212330569Sgordon		goto bad4;
213267843Sdelphij	}
214267843Sdelphij
215	/*
216	 * Finish off the attach.
217	 */
218	MWL_LOCK_INIT(sc);
219	sc->sc_io0t = rman_get_bustag(psc->sc_sr0);
220	sc->sc_io0h = rman_get_bushandle(psc->sc_sr0);
221	sc->sc_io1t = rman_get_bustag(psc->sc_sr1);
222	sc->sc_io1h = rman_get_bushandle(psc->sc_sr1);
223	if (mwl_attach(pci_get_device(dev), sc) == 0)
224		return (0);
225
226	MWL_LOCK_DESTROY(sc);
227	bus_dma_tag_destroy(sc->sc_dmat);
228bad4:
229	bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
230bad3:
231	bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
232bad2:
233	bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR1, psc->sc_sr1);
234bad1:
235	bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR0, psc->sc_sr0);
236bad:
237	return (error);
238}
239
240static int
241mwl_pci_detach(device_t dev)
242{
243	struct mwl_pci_softc *psc = device_get_softc(dev);
244	struct mwl_softc *sc = &psc->sc_sc;
245
246	/* check if device was removed */
247	sc->sc_invalid = !bus_child_present(dev);
248
249	mwl_detach(sc);
250
251	bus_generic_detach(dev);
252	bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
253	bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
254
255	bus_dma_tag_destroy(sc->sc_dmat);
256	bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR1, psc->sc_sr1);
257	bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR0, psc->sc_sr0);
258
259	MWL_LOCK_DESTROY(sc);
260
261	return (0);
262}
263
264static int
265mwl_pci_shutdown(device_t dev)
266{
267	struct mwl_pci_softc *psc = device_get_softc(dev);
268
269	mwl_shutdown(&psc->sc_sc);
270	return (0);
271}
272
273static int
274mwl_pci_suspend(device_t dev)
275{
276	struct mwl_pci_softc *psc = device_get_softc(dev);
277
278	mwl_suspend(&psc->sc_sc);
279
280	return (0);
281}
282
283static int
284mwl_pci_resume(device_t dev)
285{
286	struct mwl_pci_softc *psc = device_get_softc(dev);
287
288	if (!mwl_pci_setup(dev))
289		return ENXIO;
290
291	mwl_resume(&psc->sc_sc);
292
293	return (0);
294}
295
296static device_method_t mwl_pci_methods[] = {
297	/* Device interface */
298	DEVMETHOD(device_probe,		mwl_pci_probe),
299	DEVMETHOD(device_attach,	mwl_pci_attach),
300	DEVMETHOD(device_detach,	mwl_pci_detach),
301	DEVMETHOD(device_shutdown,	mwl_pci_shutdown),
302	DEVMETHOD(device_suspend,	mwl_pci_suspend),
303	DEVMETHOD(device_resume,	mwl_pci_resume),
304
305	{ 0,0 }
306};
307static driver_t mwl_pci_driver = {
308	"mwl",
309	mwl_pci_methods,
310	sizeof (struct mwl_pci_softc)
311};
312static	devclass_t mwl_devclass;
313DRIVER_MODULE(mwl, pci, mwl_pci_driver, mwl_devclass, 0, 0);
314MODULE_VERSION(mwl, 1);
315MODULE_DEPEND(mwl, wlan, 1, 1, 1);		/* 802.11 media layer */
316MODULE_DEPEND(mwl, mwlfw_fw, 1, 1, 1);		/* firmware */
317