mvs.h revision 207536
1/*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/mvs/mvs.h 207536 2010-05-02 19:28:30Z mav $ 27 */ 28 29#include "mvs_if.h" 30 31/* Chip registers */ 32#define CHIP_PCIEIC 0x1900 /* PCIe Interrupt Cause */ 33#define CHIP_PCIEIM 0x1910 /* PCIe Interrupt Mask */ 34#define CHIP_PCIIC 0x1d58 /* PCI Interrupt Cause */ 35#define CHIP_PCIIM 0x1d5c /* PCI Interrupt Mask */ 36#define CHIP_MIC 0x1d60 /* Main Interrupt Cause */ 37#define CHIP_MIM 0x1d64 /* Main Interrupt Mask */ 38#define CHIP_SOC_MIC 0x20 /* SoC Main Interrupt Cause */ 39#define CHIP_SOC_MIM 0x24 /* SoC Main Interrupt Mask */ 40#define IC_ERR_IRQ (1 << 0) /* shift by (2 * port #) */ 41#define IC_DONE_IRQ (1 << 1) /* shift by (2 * port #) */ 42#define IC_HC0 0x000001ff /* bits 0-8 = HC0 */ 43#define IC_HC_SHIFT 9 /* HC1 shift */ 44#define IC_HC1 (IC_HC0 << IC_HC_SHIFT) /* 9-17 = HC1 */ 45#define IC_ERR_HC0 0x00000055 /* HC0 ERR_IRQ */ 46#define IC_DONE_HC0 0x000000aa /* HC0 DONE_IRQ */ 47#define IC_ERR_HC1 (IC_ERR_HC0 << IC_HC_SHIFT) /* HC1 ERR_IRQ */ 48#define IC_DONE_HC1 (IC_DONE_HC0 << IC_HC_SHIFT) /* HC1 DONE_IRQ */ 49#define IC_HC0_COAL_DONE (1 << 8) /* HC0 IRQ coalescing */ 50#define IC_HC1_COAL_DONE (1 << 17) /* HC1 IRQ coalescing */ 51#define IC_PCI_ERR (1 << 18) 52#define IC_TRAN_COAL_LO_DONE (1 << 19) /* transaction coalescing */ 53#define IC_TRAN_COAL_HI_DONE (1 << 20) /* transaction coalescing */ 54#define IC_ALL_PORTS_COAL_DONE (1 << 21) /* GEN_II(E) IRQ coalescing */ 55#define IC_GPIO_INT (1 << 22) 56#define IC_SELF_INT (1 << 23) 57#define IC_TWSI_INT (1 << 24) 58#define IC_MAIN_RSVD (0xfe000000) /* bits 31-25 */ 59#define IC_MAIN_RSVD_5 (0xfff10000) /* bits 31-19 */ 60#define IC_MAIN_RSVD_SOC (0xfffffec0) /* bits 31-9, 7-6 */ 61 62#define CHIP_SOC_LED 0x2C /* SoC LED Configuration */ 63 64/* Chip CCC registers */ 65#define CHIP_ICC 0x18008 66#define CHIP_ICC_ALL_PORTS (1 << 4) /* all ports irq event */ 67#define CHIP_ICT 0x180cc 68#define CHIP_ITT 0x180d0 69#define CHIP_TRAN_COAL_CAUSE_LO 0x18088 70#define CHIP_TRAN_COAL_CAUSE_HI 0x1808c 71 72/* Host Controller registers */ 73#define HC_SIZE 0x10000 74#define HC_OFFSET 0x20000 75#define HC_BASE(hc) ((hc) * HC_SIZE + HC_OFFSET) 76 77#define HC_CFG 0x0 /* Configuration */ 78#define HC_CFG_TIMEOUT_MASK (0xff << 0) 79#define HC_CFG_NODMABS (1 << 8) 80#define HC_CFG_NOEDMABS (1 << 9) 81#define HC_CFG_NOPRDBS (1 << 10) 82#define HC_CFG_TIMEOUTEN (1 << 16) /* Timer Enable */ 83#define HC_CFG_COALDIS(p) (1 << ((p) + 24))/* Coalescing Disable*/ 84#define HC_RQOP 0x4 /* Request Queue Out-Pointer */ 85#define HC_RQIP 0x8 /* Response Queue In-Pointer */ 86#define HC_ICT 0xc /* Interrupt Coalescing Threshold */ 87#define HC_ICT_SAICOALT_MASK 0x000000ff 88#define HC_ITT 0x10 /* Interrupt Time Threshold */ 89#define HC_ITT_SAITMTH_MASK 0x00ffffff 90#define HC_IC 0x14 /* Interrupt Cause */ 91#define HC_IC_DONE(p) (1 << (p)) /* SaCrpb/DMA Done */ 92#define HC_IC_COAL (1 << 4) /* Intr Coalescing */ 93#define HC_IC_DEV(p) (1 << ((p) + 8)) /* Device Intr */ 94 95/* Port registers */ 96#define PORT_SIZE 0x2000 97#define PORT_OFFSET 0x2000 98#define PORT_BASE(hc) ((hc) * PORT_SIZE + PORT_OFFSET) 99 100#define EDMA_CFG 0x0 /* Configuration */ 101#define EDMA_CFG_RESERVED (0x1f << 0) /* Queue len ? */ 102#define EDMA_CFG_ESATANATVCMDQUE (1 << 5) 103#define EDMA_CFG_ERDBSZ (1 << 8) 104#define EDMA_CFG_EQUE (1 << 9) 105#define EDMA_CFG_ERDBSZEXT (1 << 11) 106#define EDMA_CFG_RESERVED2 (1 << 12) 107#define EDMA_CFG_EWRBUFFERLEN (1 << 13) 108#define EDMA_CFG_EDEVERR (1 << 14) 109#define EDMA_CFG_EEDMAFBS (1 << 16) 110#define EDMA_CFG_ECUTTHROUGHEN (1 << 17) 111#define EDMA_CFG_EEARLYCOMPLETIONEN (1 << 18) 112#define EDMA_CFG_EEDMAQUELEN (1 << 19) 113#define EDMA_CFG_EHOSTQUEUECACHEEN (1 << 22) 114#define EDMA_CFG_EMASKRXPM (1 << 23) 115#define EDMA_CFG_RESUMEDIS (1 << 24) 116#define EDMA_CFG_EDMAFBS (1 << 26) 117#define EDMA_T 0x4 /* Timer */ 118#define EDMA_IEC 0x8 /* Interrupt Error Cause */ 119#define EDMA_IEM 0xc /* Interrupt Error Mask */ 120#define EDMA_IE_EDEVERR (1 << 2) /* EDMA Device Error */ 121#define EDMA_IE_EDEVDIS (1 << 3) /* EDMA Dev Disconn */ 122#define EDMA_IE_EDEVCON (1 << 4) /* EDMA Dev Conn */ 123#define EDMA_IE_SERRINT (1 << 5) 124#define EDMA_IE_ESELFDIS (1 << 7) /* EDMA Self Disable */ 125#define EDMA_IE_ETRANSINT (1 << 8) /* Transport Layer */ 126#define EDMA_IE_EIORDYERR (1 << 12) /* EDMA IORdy Error */ 127#define EDMA_IE_LINKXERR_SATACRC (1 << 0) /* SATA CRC error */ 128#define EDMA_IE_LINKXERR_INTERNALFIFO (1 << 1) /* internal FIFO err */ 129#define EDMA_IE_LINKXERR_LINKLAYERRESET (1 << 2) 130 /* Link Layer is reset by the reception of SYNC primitive from device */ 131#define EDMA_IE_LINKXERR_OTHERERRORS (1 << 3) 132 /* 133 * Link state errors, coding errors, or running disparity errors occur 134 * during FIS reception. 135 */ 136#define EDMA_IE_LINKTXERR_FISTXABORTED (1 << 4) /* FIS Tx is aborted */ 137#define EDMA_IE_LINKCTLRXERR(x) ((x) << 13) /* Link Ctrl Recv Err */ 138#define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */ 139#define EDMA_IE_LINKCTLTXERR(x) ((x) << 21) /* Link Ctrl Tx Error */ 140#define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */ 141#define EDMA_IE_TRANSPROTERR (1 << 31) /* Transport Proto E */ 142#define EDMA_IE_TRANSIENT (EDMA_IE_LINKCTLRXERR(0x0b) | \ 143 EDMA_IE_LINKCTLTXERR(0x1f)) 144 /* Non-fatal Errors */ 145#define EDMA_REQQBAH 0x10 /* Request Queue Base Address High */ 146#define EDMA_REQQIP 0x14 /* Request Queue In-Pointer */ 147#define EDMA_REQQOP 0x18 /* Request Queue Out-Pointer */ 148#define EDMA_REQQP_ERQQP_SHIFT 5 149#define EDMA_REQQP_ERQQP_MASK 0x000003e0 150#define EDMA_REQQP_ERQQBAP_MASK 0x00000c00 151#define EDMA_REQQP_ERQQBA_MASK 0xfffff000 152#define EDMA_RESQBAH 0x1c /* Response Queue Base Address High */ 153#define EDMA_RESQIP 0x20 /* Response Queue In-Pointer */ 154#define EDMA_RESQOP 0x24 /* Response Queue Out-Pointer */ 155#define EDMA_RESQP_ERPQP_SHIFT 3 156#define EDMA_RESQP_ERPQP_MASK 0x000000f8 157#define EDMA_RESQP_ERPQBAP_MASK 0x00000300 158#define EDMA_RESQP_ERPQBA_MASK 0xfffffc00 159#define EDMA_CMD 0x28 /* Command */ 160#define EDMA_CMD_EENEDMA (1 << 0) /* Enable EDMA */ 161#define EDMA_CMD_EDSEDMA (1 << 1) /* Disable EDMA */ 162#define EDMA_CMD_EATARST (1 << 2) /* ATA Device Reset */ 163#define EDMA_CMD_EEDMAFRZ (1 << 4) /* EDMA Freeze */ 164#define EDMA_TC 0x2c /* Test Control */ 165#define EDMA_S 0x30 /* Status */ 166#define EDMA_S_EDEVQUETAG(s) ((s) & 0x0000001f) 167#define EDMA_S_EDEVDIR_WRITE (0 << 5) 168#define EDMA_S_EDEVDIR_READ (1 << 5) 169#define EDMA_S_ECACHEEMPTY (1 << 6) 170#define EDMA_S_EDMAIDLE (1 << 7) 171#define EDMA_S_ESTATE(s) (((s) & 0x0000ff00) >> 8) 172#define EDMA_S_EIOID(s) (((s) & 0x003f0000) >> 16) 173#define EDMA_IORT 0x34 /* IORdy Timeout */ 174#define EDMA_CDT 0x40 /* Command Delay Threshold */ 175#define EDMA_HC 0x60 /* Halt Condition */ 176#define EDMA_UNKN_RESD 0x6C /* Unknown register */ 177#define EDMA_CQDCQOS(x) (0x90 + ((x) << 2) 178 /* NCQ Done/TCQ Outstanding Status */ 179 180/* ATA register defines */ 181#define ATA_DATA 0x100 /* (RW) data */ 182#define ATA_FEATURE 0x104 /* (W) feature */ 183#define ATA_F_DMA 0x01 /* enable DMA */ 184#define ATA_F_OVL 0x02 /* enable overlap */ 185#define ATA_ERROR 0x104 /* (R) error */ 186#define ATA_E_ILI 0x01 /* illegal length */ 187#define ATA_E_NM 0x02 /* no media */ 188#define ATA_E_ABORT 0x04 /* command aborted */ 189#define ATA_E_MCR 0x08 /* media change request */ 190#define ATA_E_IDNF 0x10 /* ID not found */ 191#define ATA_E_MC 0x20 /* media changed */ 192#define ATA_E_UNC 0x40 /* uncorrectable data */ 193#define ATA_E_ICRC 0x80 /* UDMA crc error */ 194#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 195#define ATA_COUNT 0x108 /* (W) sector count */ 196#define ATA_IREASON 0x108 /* (R) interrupt reason */ 197#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 198#define ATA_I_IN 0x02 /* read (1) | write (0) */ 199#define ATA_I_RELEASE 0x04 /* released bus (1) */ 200#define ATA_I_TAGMASK 0xf8 /* tag mask */ 201#define ATA_SECTOR 0x10c /* (RW) sector # */ 202#define ATA_CYL_LSB 0x110 /* (RW) cylinder# LSB */ 203#define ATA_CYL_MSB 0x114 /* (RW) cylinder# MSB */ 204#define ATA_DRIVE 0x118 /* (W) Sector/Drive/Head */ 205#define ATA_D_LBA 0x40 /* use LBA addressing */ 206#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 207#define ATA_COMMAND 0x11c /* (W) command */ 208#define ATA_STATUS 0x11c /* (R) status */ 209#define ATA_S_ERROR 0x01 /* error */ 210#define ATA_S_INDEX 0x02 /* index */ 211#define ATA_S_CORR 0x04 /* data corrected */ 212#define ATA_S_DRQ 0x08 /* data request */ 213#define ATA_S_DSC 0x10 /* drive seek completed */ 214#define ATA_S_SERVICE 0x10 /* drive needs service */ 215#define ATA_S_DWF 0x20 /* drive write fault */ 216#define ATA_S_DMA 0x20 /* DMA ready */ 217#define ATA_S_READY 0x40 /* drive ready */ 218#define ATA_S_BUSY 0x80 /* busy */ 219#define ATA_CONTROL 0x120 /* (W) control */ 220#define ATA_A_IDS 0x02 /* disable interrupts */ 221#define ATA_A_RESET 0x04 /* RESET controller */ 222#define ATA_A_4BIT 0x08 /* 4 head bits */ 223#define ATA_A_HOB 0x80 /* High Order Byte enable */ 224#define ATA_ALTSTAT 0x120 /* (R) alternate status */ 225#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 226#define ATAPI_P_WRITE (ATA_S_DRQ) 227#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 228#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 229#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 230#define ATAPI_P_ABORT 0 231 232/* Basic DMA Registers */ 233#define DMA_C 0x224 /* Basic DMA Command */ 234#define DMA_C_START (1 << 0) 235#define DMA_C_READ (1 << 3) 236#define DMA_C_DREGIONVALID (1 << 8) 237#define DMA_C_DREGIONLAST (1 << 9) 238#define DMA_C_CONTFROMPREV (1 << 10) 239#define DMA_C_DRBC(n) (((n) & 0xffff) << 16) 240#define DMA_S 0x228 /* Basic DMA Status */ 241#define DMA_S_ACT (1 << 0) /* Active */ 242#define DMA_S_ERR (1 << 1) /* Error */ 243#define DMA_S_PAUSED (1 << 2) /* Paused */ 244#define DMA_S_LAST (1 << 3) /* Last */ 245#define DMA_DTLBA 0x22c /* Descriptor Table Low Base Address */ 246#define DMA_DTLBA_MASK 0xfffffff0 247#define DMA_DTHBA 0x230 /* Descriptor Table High Base Address */ 248#define DMA_DRLA 0x234 /* Data Region Low Address */ 249#define DMA_DRHA 0x238 /* Data Region High Address */ 250 251/* Serial-ATA Registers */ 252#define SATA_SS 0x300 /* SStatus */ 253#define SATA_SS_DET_MASK 0x0000000f 254#define SATA_SS_DET_NO_DEVICE 0x00000000 255#define SATA_SS_DET_DEV_PRESENT 0x00000001 256#define SATA_SS_DET_PHY_ONLINE 0x00000003 257#define SATA_SS_DET_PHY_OFFLINE 0x00000004 258 259#define SATA_SS_SPD_MASK 0x000000f0 260#define SATA_SS_SPD_NO_SPEED 0x00000000 261#define SATA_SS_SPD_GEN1 0x00000010 262#define SATA_SS_SPD_GEN2 0x00000020 263#define SATA_SS_SPD_GEN3 0x00000040 264 265#define SATA_SS_IPM_MASK 0x00000f00 266#define SATA_SS_IPM_NO_DEVICE 0x00000000 267#define SATA_SS_IPM_ACTIVE 0x00000100 268#define SATA_SS_IPM_PARTIAL 0x00000200 269#define SATA_SS_IPM_SLUMBER 0x00000600 270#define SATA_SE 0x304 /* SError */ 271#define SATA_SEIM 0x340 /* SError Interrupt Mask */ 272#define SATA_SE_DATA_CORRECTED 0x00000001 273#define SATA_SE_COMM_CORRECTED 0x00000002 274#define SATA_SE_DATA_ERR 0x00000100 275#define SATA_SE_COMM_ERR 0x00000200 276#define SATA_SE_PROT_ERR 0x00000400 277#define SATA_SE_HOST_ERR 0x00000800 278#define SATA_SE_PHY_CHANGED 0x00010000 279#define SATA_SE_PHY_IERROR 0x00020000 280#define SATA_SE_COMM_WAKE 0x00040000 281#define SATA_SE_DECODE_ERR 0x00080000 282#define SATA_SE_PARITY_ERR 0x00100000 283#define SATA_SE_CRC_ERR 0x00200000 284#define SATA_SE_HANDSHAKE_ERR 0x00400000 285#define SATA_SE_LINKSEQ_ERR 0x00800000 286#define SATA_SE_TRANSPORT_ERR 0x01000000 287#define SATA_SE_UNKNOWN_FIS 0x02000000 288#define SATA_SC 0x308 /* SControl */ 289#define SATA_SC_DET_MASK 0x0000000f 290#define SATA_SC_DET_IDLE 0x00000000 291#define SATA_SC_DET_RESET 0x00000001 292#define SATA_SC_DET_DISABLE 0x00000004 293 294#define SATA_SC_SPD_MASK 0x000000f0 295#define SATA_SC_SPD_NO_SPEED 0x00000000 296#define SATA_SC_SPD_SPEED_GEN1 0x00000010 297#define SATA_SC_SPD_SPEED_GEN2 0x00000020 298#define SATA_SC_SPD_SPEED_GEN3 0x00000040 299 300#define SATA_SC_IPM_MASK 0x00000f00 301#define SATA_SC_IPM_NONE 0x00000000 302#define SATA_SC_IPM_DIS_PARTIAL 0x00000100 303#define SATA_SC_IPM_DIS_SLUMBER 0x00000200 304 305#define SATA_SC_SPM_MASK 0x0000f000 306#define SATA_SC_SPM_NONE 0x00000000 307#define SATA_SC_SPM_PARTIAL 0x00001000 308#define SATA_SC_SPM_SLUMBER 0x00002000 309#define SATA_SC_SPM_ACTIVE 0x00004000 310#define SATA_LTM 0x30c /* LTMode */ 311#define SATA_PHYM3 0x310 /* PHY Mode 3 */ 312#define SATA_PHYM4 0x314 /* PHY Mode 4 */ 313#define SATA_PHYM1 0x32c /* PHY Mode 1 */ 314#define SATA_PHYM2 0x330 /* PHY Mode 2 */ 315#define SATA_BISTC 0x334 /* BIST Control */ 316#define SATA_BISTDW1 0x338 /* BIST DW1 */ 317#define SATA_BISTDW2 0x33c /* BIST DW2 */ 318#define SATA_SATAICFG 0x050 /* Serial-ATA Interface Configuration */ 319#define SATA_SATAICFG_REFCLKCNF_20MHZ (0 << 0) 320#define SATA_SATAICFG_REFCLKCNF_25MHZ (1 << 0) 321#define SATA_SATAICFG_REFCLKCNF_30MHZ (2 << 0) 322#define SATA_SATAICFG_REFCLKCNF_40MHZ (3 << 0) 323#define SATA_SATAICFG_REFCLKCNF_MASK (3 << 0) 324#define SATA_SATAICFG_REFCLKDIV_1 (0 << 2) 325#define SATA_SATAICFG_REFCLKDIV_2 (1 << 2) /* Used 20 or 25MHz */ 326#define SATA_SATAICFG_REFCLKDIV_4 (2 << 2) /* Used 40MHz */ 327#define SATA_SATAICFG_REFCLKDIV_3 (3 << 2) /* Used 30MHz */ 328#define SATA_SATAICFG_REFCLKDIV_MASK (3 << 2) 329#define SATA_SATAICFG_REFCLKFEEDDIV_50 (0 << 4) /* or 100, when Gen2En is 1 */ 330#define SATA_SATAICFG_REFCLKFEEDDIV_60 (1 << 4) /* or 120. Used 25MHz */ 331#define SATA_SATAICFG_REFCLKFEEDDIV_75 (2 << 4) /* or 150. Used 20MHz */ 332#define SATA_SATAICFG_REFCLKFEEDDIV_90 (3 << 4) /* or 180 */ 333#define SATA_SATAICFG_REFCLKFEEDDIV_MASK (3 << 4) 334#define SATA_SATAICFG_PHYSSCEN (1 << 6) 335#define SATA_SATAICFG_GEN2EN (1 << 7) 336#define SATA_SATAICFG_COMMEN (1 << 8) 337#define SATA_SATAICFG_PHYSHUTDOWN (1 << 9) 338#define SATA_SATAICFG_TARGETMODE (1 << 10) /* 1 = Initiator */ 339#define SATA_SATAICFG_COMCHANNEL (1 << 11) 340#define SATA_SATAICFG_IGNOREBSY (1 << 24) 341#define SATA_SATAICFG_LINKRSTEN (1 << 25) 342#define SATA_SATAICFG_CMDRETXDS (1 << 26) 343#define SATA_SATAICTL 0x344 /* Serial-ATA Interface Control */ 344#define SATA_SATAICTL_PMPTX_MASK 0x0000000f 345#define SATA_SATAICTL_PMPTX_SHIFT 0 346#define SATA_SATAICTL_VUM (1 << 8) 347#define SATA_SATAICTL_VUS (1 << 9) 348#define SATA_SATAICTL_EDMAACT (1 << 16) 349#define SATA_SATAICTL_CLEARSTAT (1 << 24) 350#define SATA_SATAICTL_SRST (1 << 25) 351#define SATA_SATAITC 0x348 /* Serial-ATA Interface Test Control */ 352#define SATA_SATAIS 0x34c /* Serial-ATA Interface Status */ 353#define SATA_VU 0x35c /* Vendor Unique */ 354#define SATA_FISC 0x360 /* FIS Configuration */ 355#define SATA_FISC_FISWAIT4RDYEN_B0 (1 << 0) /* Device to Host FIS */ 356#define SATA_FISC_FISWAIT4RDYEN_B1 (1 << 1) /* SDB FIS rcv with <N>bit 0 */ 357#define SATA_FISC_FISWAIT4RDYEN_B2 (1 << 2) /* DMA Activate FIS */ 358#define SATA_FISC_FISWAIT4RDYEN_B3 (1 << 3) /* DMA Setup FIS */ 359#define SATA_FISC_FISWAIT4RDYEN_B4 (1 << 4) /* Data FIS first DW */ 360#define SATA_FISC_FISWAIT4RDYEN_B5 (1 << 5) /* Data FIS entire FIS */ 361#define SATA_FISC_FISWAIT4HOSTRDYEN_B0 (1 << 8) 362 /* Device to Host FIS with <ERR> or <DF> */ 363#define SATA_FISC_FISWAIT4HOSTRDYEN_B1 (1 << 9) /* SDB FIS rcv with <N>bit */ 364#define SATA_FISC_FISWAIT4HOSTRDYEN_B2 (1 << 10) /* SDB FIS rcv with <ERR> */ 365#define SATA_FISC_FISWAIT4HOSTRDYEN_B3 (1 << 11) /* BIST Acivate FIS */ 366#define SATA_FISC_FISWAIT4HOSTRDYEN_B4 (1 << 12) /* PIO Setup FIS */ 367#define SATA_FISC_FISWAIT4HOSTRDYEN_B5 (1 << 13) /* Data FIS with Link error */ 368#define SATA_FISC_FISWAIT4HOSTRDYEN_B6 (1 << 14) /* Unrecognized FIS type */ 369#define SATA_FISC_FISWAIT4HOSTRDYEN_B7 (1 << 15) /* Any FIS */ 370#define SATA_FISC_FISDMAACTIVATESYNCRESP (1 << 16) 371#define SATA_FISC_FISUNRECTYPECONT (1 << 17) 372#define SATA_FISIC 0x364 /* FIS Interrupt Cause */ 373#define SATA_FISIM 0x368 /* FIS Interrupt Mask */ 374#define SATA_FISDW0 0x370 /* FIS DW0 */ 375#define SATA_FISDW1 0x374 /* FIS DW1 */ 376#define SATA_FISDW2 0x378 /* FIS DW2 */ 377#define SATA_FISDW3 0x37c /* FIS DW3 */ 378#define SATA_FISDW4 0x380 /* FIS DW4 */ 379#define SATA_FISDW5 0x384 /* FIS DW5 */ 380#define SATA_FISDW6 0x388 /* FIS DW6 */ 381 382#define MVS_MAX_PORTS 8 383#define MVS_MAX_SLOTS 32 384 385/* Pessimistic prognosis on number of required S/G entries */ 386#define MVS_SG_ENTRIES (btoc(MAXPHYS) + 1) 387 388/* EDMA Command Request Block (CRQB) Data */ 389struct mvs_crqb { 390 uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */ 391 uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */ 392 uint16_t ctrlflg; /* Control Flags */ 393#define MVS_CRQB_READ 0x0001 394#define MVS_CRQB_TAG_MASK 0x003e 395#define MVS_CRQB_TAG_SHIFT 1 396#define MVS_CRQB_PMP_MASK 0xf000 397#define MVS_CRQB_PMP_SHIFT 12 398 uint8_t cmd[22]; 399} __packed; 400 401struct mvs_crqb_gen2e { 402 uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */ 403 uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */ 404 uint32_t ctrlflg; /* Control Flags */ 405#define MVS_CRQB2E_READ 0x00000001 406#define MVS_CRQB2E_DTAG_MASK 0x0000003e 407#define MVS_CRQB2E_DTAG_SHIFT 1 408#define MVS_CRQB2E_PMP_MASK 0x0000f000 409#define MVS_CRQB2E_PMP_SHIFT 12 410#define MVS_CRQB2E_CPRD 0x00010000 411#define MVS_CRQB2E_HTAG_MASK 0x003e0000 412#define MVS_CRQB2E_HTAG_SHIFT 17 413 uint32_t drbc; /* Data Region Byte Count */ 414 uint8_t cmd[16]; 415} __packed; 416 417/* EDMA Phisical Region Descriptors (ePRD) Table Data Structure */ 418struct mvs_eprd { 419 uint32_t prdbal; /* Address bits[31:1] */ 420 uint32_t bytecount; /* Byte Count */ 421#define MVS_EPRD_MASK 0x0000ffff /* max 64KB */ 422#define MVS_EPRD_MAX (MVS_EPRD_MASK + 1) 423#define MVS_EPRD_EOF 0x80000000 424 uint32_t prdbah; /* Address bits[63:32] */ 425 uint32_t resv; 426} __packed; 427 428/* Command request blocks. 32 commands. First 1Kbyte aligned. */ 429#define MVS_CRQB_OFFSET 0 430#define MVS_CRQB_SIZE 32 /* sizeof(struct mvs_crqb) */ 431#define MVS_CRQB_MASK 0x000003e0 432#define MVS_CRQB_SHIFT 5 433#define MVS_CRQB_TO_ADDR(slot) ((slot) << MVS_CRQB_SHIFT) 434#define MVS_ADDR_TO_CRQB(addr) (((addr) & MVS_CRQB_MASK) >> MVS_CRQB_SHIFT) 435/* ePRD blocks. Up to 32 commands, Each 16byte aligned. */ 436#define MVS_EPRD_OFFSET (MVS_CRQB_OFFSET + MVS_CRQB_SIZE * MVS_MAX_SLOTS) 437#define MVS_EPRD_SIZE (MVS_SG_ENTRIES * 16) /* sizeof(struct mvs_eprd) */ 438/* Request work area. */ 439#define MVS_WORKRQ_SIZE (MVS_EPRD_OFFSET + MVS_EPRD_SIZE * MVS_MAX_SLOTS) 440 441/* EDMA Command Response Block (CRPB) Data */ 442struct mvs_crpb { 443 uint16_t id; /* CRPB ID */ 444#define MVS_CRPB_TAG_MASK 0x001F 445#define MVS_CRPB_TAG_SHIFT 0 446 uint16_t rspflg; /* CPRB Response Flags */ 447#define MVS_CRPB_EDMASTS_MASK 0x007F 448#define MVS_CRPB_EDMASTS_SHIFT 0 449#define MVS_CRPB_ATASTS_MASK 0xFF00 450#define MVS_CRPB_ATASTS_SHIFT 8 451 uint32_t ts; /* CPRB Time Stamp */ 452} __packed; 453 454/* Command response blocks. 32 commands. First 256byte aligned. */ 455#define MVS_CRPB_OFFSET 0 456#define MVS_CRPB_SIZE sizeof(struct mvs_crpb) 457#define MVS_CRPB_MASK 0x000000f8 458#define MVS_CRPB_SHIFT 3 459#define MVS_CRPB_TO_ADDR(slot) ((slot) << MVS_CRPB_SHIFT) 460#define MVS_ADDR_TO_CRPB(addr) (((addr) & MVS_CRPB_MASK) >> MVS_CRPB_SHIFT) 461/* Request work area. */ 462#define MVS_WORKRP_SIZE (MVS_CRPB_OFFSET + MVS_CRPB_SIZE * MVS_MAX_SLOTS) 463 464/* misc defines */ 465#define ATA_IRQ_RID 0 466#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 467 468struct ata_dmaslot { 469 bus_dmamap_t data_map; /* Data DMA map */ 470 bus_addr_t addr; /* Data address */ 471 uint16_t len; /* Data size */ 472}; 473 474/* structure holding DMA related information */ 475struct mvs_dma { 476 bus_dma_tag_t workrq_tag; /* Request workspace DMA tag */ 477 bus_dmamap_t workrq_map; /* Request workspace DMA map */ 478 uint8_t *workrq; /* Request workspace */ 479 bus_addr_t workrq_bus; /* Request bus address */ 480 bus_dma_tag_t workrp_tag; /* Reply workspace DMA tag */ 481 bus_dmamap_t workrp_map; /* Reply workspace DMA map */ 482 uint8_t *workrp; /* Reply workspace */ 483 bus_addr_t workrp_bus; /* Reply bus address */ 484 bus_dma_tag_t data_tag; /* Data DMA tag */ 485}; 486 487enum mvs_slot_states { 488 MVS_SLOT_EMPTY, 489 MVS_SLOT_LOADING, 490 MVS_SLOT_RUNNING, 491 MVS_SLOT_EXECUTING 492}; 493 494struct mvs_slot { 495 device_t dev; /* Device handle */ 496 int slot; /* Number of this slot */ 497 int tag; /* Used command tag */ 498 enum mvs_slot_states state; /* Slot state */ 499 union ccb *ccb; /* CCB occupying slot */ 500 struct ata_dmaslot dma; /* DMA data of this slot */ 501 struct callout timeout; /* Execution timeout */ 502}; 503 504struct mvs_device { 505 int revision; 506 int mode; 507 u_int bytecount; 508 u_int atapi; 509 u_int tags; 510 u_int caps; 511}; 512 513enum mvs_edma_mode { 514 MVS_EDMA_UNKNOWN, 515 MVS_EDMA_OFF, 516 MVS_EDMA_ON, 517 MVS_EDMA_QUEUED, 518 MVS_EDMA_NCQ, 519}; 520 521/* structure describing an ATA channel */ 522struct mvs_channel { 523 device_t dev; /* Device handle */ 524 int unit; /* Physical channel */ 525 struct resource *r_mem; /* Memory of this channel */ 526 struct resource *r_irq; /* Interrupt of this channel */ 527 void *ih; /* Interrupt handle */ 528 struct mvs_dma dma; /* DMA data */ 529 struct cam_sim *sim; 530 struct cam_path *path; 531 int quirks; 532#define MVS_Q_GENI 1 533#define MVS_Q_GENII 2 534#define MVS_Q_GENIIE 4 535#define MVS_Q_SOC 8 536#define MVS_Q_CT 16 537 int pm_level; /* power management level */ 538 539 struct mvs_slot slot[MVS_MAX_SLOTS]; 540 union ccb *hold[MVS_MAX_SLOTS]; 541 int holdtag[MVS_MAX_SLOTS]; /* Tags used for holden commands. */ 542 struct mtx mtx; /* state lock */ 543 int devices; /* What is present */ 544 int pm_present; /* PM presence reported */ 545 enum mvs_edma_mode curr_mode; /* Current EDMA mode */ 546 int fbs_enabled; /* FIS-based switching enabled */ 547 uint32_t oslots; /* Occupied slots */ 548 uint32_t otagspd[16]; /* Occupied device tags */ 549 uint32_t rslots; /* Running slots */ 550 uint32_t aslots; /* Slots with atomic commands */ 551 uint32_t eslots; /* Slots in error */ 552 uint32_t toslots; /* Slots in timeout */ 553 int numrslots; /* Number of running slots */ 554 int numrslotspd[16];/* Number of running slots per dev */ 555 int numpslots; /* Number of PIO slots */ 556 int numdslots; /* Number of DMA slots */ 557 int numtslots; /* Number of NCQ slots */ 558 int numtslotspd[16];/* Number of NCQ slots per dev */ 559 int numhslots; /* Number of holden slots */ 560 int readlog; /* Our READ LOG active */ 561 int fatalerr; /* Fatal error happend */ 562 int lastslot; /* Last used slot */ 563 int taggedtarget; /* Last tagged target */ 564 int out_idx; /* Next written CRQB */ 565 int in_idx; /* Next read CRPB */ 566 u_int transfersize; /* PIO transfer size */ 567 u_int donecount; /* PIO bytes sent/received */ 568 u_int basic_dma; /* Basic DMA used for ATAPI */ 569 u_int fake_busy; /* Fake busy bit after command submission */ 570 union ccb *frozen; /* Frozen command */ 571 struct callout pm_timer; /* Power management events */ 572 573 struct mvs_device user[16]; /* User-specified settings */ 574 struct mvs_device curr[16]; /* Current settings */ 575}; 576 577/* structure describing a MVS controller */ 578struct mvs_controller { 579 device_t dev; 580 int r_rid; 581 struct resource *r_mem; 582 struct rman sc_iomem; 583 struct mvs_controller_irq { 584 struct resource *r_irq; 585 void *handle; 586 int r_irq_rid; 587 } irq; 588 int quirks; 589 int channels; 590 int ccc; /* CCC timeout */ 591 int cccc; /* CCC commands */ 592 struct mtx mtx; /* MIM access lock */ 593 int gmim; /* Globally wanted MIM bits */ 594 int pmim; /* Port wanted MIM bits */ 595 int mim; /* Current MIM bits */ 596 int msi; /* MSI enabled */ 597 int msia; /* MSI active */ 598 struct { 599 void (*function)(void *); 600 void *argument; 601 } interrupt[MVS_MAX_PORTS]; 602}; 603 604enum mvs_err_type { 605 MVS_ERR_NONE, /* No error */ 606 MVS_ERR_INVALID, /* Error detected by us before submitting. */ 607 MVS_ERR_INNOCENT, /* Innocent victim. */ 608 MVS_ERR_TFE, /* Task File Error. */ 609 MVS_ERR_SATA, /* SATA error. */ 610 MVS_ERR_TIMEOUT, /* Command execution timeout. */ 611 MVS_ERR_NCQ, /* NCQ command error. CCB should be put on hold 612 * until READ LOG executed to reveal error. */ 613}; 614 615struct mvs_intr_arg { 616 void *arg; 617 u_int cause; 618}; 619 620extern devclass_t mvs_devclass; 621 622/* macros to hide busspace uglyness */ 623#define ATA_INB(res, offset) \ 624 bus_read_1((res), (offset)) 625#define ATA_INW(res, offset) \ 626 bus_read_2((res), (offset)) 627#define ATA_INL(res, offset) \ 628 bus_read_4((res), (offset)) 629#define ATA_INSW(res, offset, addr, count) \ 630 bus_read_multi_2((res), (offset), (addr), (count)) 631#define ATA_INSW_STRM(res, offset, addr, count) \ 632 bus_read_multi_stream_2((res), (offset), (addr), (count)) 633#define ATA_INSL(res, offset, addr, count) \ 634 bus_read_multi_4((res), (offset), (addr), (count)) 635#define ATA_INSL_STRM(res, offset, addr, count) \ 636 bus_read_multi_stream_4((res), (offset), (addr), (count)) 637#define ATA_OUTB(res, offset, value) \ 638 bus_write_1((res), (offset), (value)) 639#define ATA_OUTW(res, offset, value) \ 640 bus_write_2((res), (offset), (value)) 641#define ATA_OUTL(res, offset, value) \ 642 bus_write_4((res), (offset), (value)); 643#define ATA_OUTSW(res, offset, addr, count) \ 644 bus_write_multi_2((res), (offset), (addr), (count)) 645#define ATA_OUTSW_STRM(res, offset, addr, count) \ 646 bus_write_multi_stream_2((res), (offset), (addr), (count)) 647#define ATA_OUTSL(res, offset, addr, count) \ 648 bus_write_multi_4((res), (offset), (addr), (count)) 649#define ATA_OUTSL_STRM(res, offset, addr, count) \ 650 bus_write_multi_stream_4((res), (offset), (addr), (count)) 651