mpi2_ioc.h revision 265388
1/*- 2 * Copyright (c) 2013 LSI Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * LSI MPT-Fusion Host Adapter FreeBSD 30 * 31 * $FreeBSD: stable/10/sys/dev/mpr/mpi/mpi2_ioc.h 265236 2014-05-02 20:25:09Z ken $ 32 */ 33 34/* 35 * Copyright (c) 2000-2013 LSI Corporation. 36 * 37 * 38 * Name: mpi2_ioc.h 39 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 40 * Creation Date: October 11, 2006 41 * 42 * mpi2_ioc.h Version: 02.00.24 43 * 44 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 45 * prefix are for use only on MPI v2.5 products, and must not be used 46 * with MPI v2.0 products. Unless otherwise noted, names beginning with 47 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 48 * 49 * Version History 50 * --------------- 51 * 52 * Date Version Description 53 * -------- -------- ------------------------------------------------------ 54 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 55 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 56 * MaxTargets. 57 * Added TotalImageSize field to FWDownload Request. 58 * Added reserved words to FWUpload Request. 59 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 60 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 61 * request and replaced it with 62 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 63 * Replaced the MinReplyQueueDepth field of the IOCFacts 64 * reply with MaxReplyDescriptorPostQueueDepth. 65 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 66 * depth for the Reply Descriptor Post Queue. 67 * Added SASAddress field to Initiator Device Table 68 * Overflow Event data. 69 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 70 * for SAS Initiator Device Status Change Event data. 71 * Modified Reason Code defines for SAS Topology Change 72 * List Event data, including adding a bit for PHY Vacant 73 * status, and adding a mask for the Reason Code. 74 * Added define for 75 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 76 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 77 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 78 * the IOCFacts Reply. 79 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 80 * Moved MPI2_VERSION_UNION to mpi2.h. 81 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 82 * instead of enables, and added SASBroadcastPrimitiveMasks 83 * field. 84 * Added Log Entry Added Event and related structure. 85 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 86 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 87 * Added MaxVolumes and MaxPersistentEntries fields to 88 * IOCFacts reply. 89 * Added ProtocalFlags and IOCCapabilities fields to 90 * MPI2_FW_IMAGE_HEADER. 91 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 92 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 93 * a U16 (from a U32). 94 * Removed extra 's' from EventMasks name. 95 * 06-27-08 02.00.08 Fixed an offset in a comment. 96 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 97 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 98 * renamed MinReplyFrameSize to ReplyFrameSize. 99 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 100 * Added two new RAIDOperation values for Integrated RAID 101 * Operations Status Event data. 102 * Added four new IR Configuration Change List Event data 103 * ReasonCode values. 104 * Added two new ReasonCode defines for SAS Device Status 105 * Change Event data. 106 * Added three new DiscoveryStatus bits for the SAS 107 * Discovery event data. 108 * Added Multiplexing Status Change bit to the PhyStatus 109 * field of the SAS Topology Change List event data. 110 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 111 * BootFlags are now product-specific. 112 * Added defines for the indivdual signature bytes 113 * for MPI2_INIT_IMAGE_FOOTER. 114 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 115 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 116 * define. 117 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 118 * define. 119 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 120 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 121 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 122 * Added two new reason codes for SAS Device Status Change 123 * Event. 124 * Added new event: SAS PHY Counter. 125 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 126 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 127 * Added new product id family for 2208. 128 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 129 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 130 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 131 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 132 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 133 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 134 * Added Host Based Discovery Phy Event data. 135 * Added defines for ProductID Product field 136 * (MPI2_FW_HEADER_PID_). 137 * Modified values for SAS ProductID Family 138 * (MPI2_FW_HEADER_PID_FAMILY_). 139 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 140 * Added PowerManagementControl Request structures and 141 * defines. 142 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 143 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 144 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 145 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 146 * SASNotifyPrimitiveMasks field to 147 * MPI2_EVENT_NOTIFICATION_REQUEST. 148 * Added Temperature Threshold Event. 149 * Added Host Message Event. 150 * Added Send Host Message request and reply. 151 * 05-25-11 02.00.18 For Extended Image Header, added 152 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 153 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 154 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 155 * 08-24-11 02.00.19 Added PhysicalPort field to 156 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 157 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 158 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 159 * 03-29-12 02.00.21 Added a product specific range to event values. 160 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 161 * Added ElapsedSeconds field to 162 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 163 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 164 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 165 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 166 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 167 * Added Encrypted Hash Extended Image. 168 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. 169 * -------------------------------------------------------------------------- 170 */ 171 172#ifndef MPI2_IOC_H 173#define MPI2_IOC_H 174 175/***************************************************************************** 176* 177* IOC Messages 178* 179*****************************************************************************/ 180 181/**************************************************************************** 182* IOCInit message 183****************************************************************************/ 184 185/* IOCInit Request message */ 186typedef struct _MPI2_IOC_INIT_REQUEST 187{ 188 U8 WhoInit; /* 0x00 */ 189 U8 Reserved1; /* 0x01 */ 190 U8 ChainOffset; /* 0x02 */ 191 U8 Function; /* 0x03 */ 192 U16 Reserved2; /* 0x04 */ 193 U8 Reserved3; /* 0x06 */ 194 U8 MsgFlags; /* 0x07 */ 195 U8 VP_ID; /* 0x08 */ 196 U8 VF_ID; /* 0x09 */ 197 U16 Reserved4; /* 0x0A */ 198 U16 MsgVersion; /* 0x0C */ 199 U16 HeaderVersion; /* 0x0E */ 200 U32 Reserved5; /* 0x10 */ 201 U16 Reserved6; /* 0x14 */ 202 U8 Reserved7; /* 0x16 */ 203 U8 HostMSIxVectors; /* 0x17 */ 204 U16 Reserved8; /* 0x18 */ 205 U16 SystemRequestFrameSize; /* 0x1A */ 206 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 207 U16 ReplyFreeQueueDepth; /* 0x1E */ 208 U32 SenseBufferAddressHigh; /* 0x20 */ 209 U32 SystemReplyAddressHigh; /* 0x24 */ 210 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 211 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 212 U64 ReplyFreeQueueAddress; /* 0x38 */ 213 U64 TimeStamp; /* 0x40 */ 214} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 215 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 216 217/* WhoInit values */ 218#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 219#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 220#define MPI2_WHOINIT_ROM_BIOS (0x02) 221#define MPI2_WHOINIT_PCI_PEER (0x03) 222#define MPI2_WHOINIT_HOST_DRIVER (0x04) 223#define MPI2_WHOINIT_MANUFACTURER (0x05) 224 225/* MsgFlags */ 226#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 227 228/* MsgVersion */ 229#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 230#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 231#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 232#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 233 234/* HeaderVersion */ 235#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 236#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 237#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 238#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 239 240/* minimum depth for a Reply Descriptor Post Queue */ 241#define MPI2_RDPQ_DEPTH_MIN (16) 242 243/* Reply Descriptor Post Queue Array Entry */ 244typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY 245{ 246 U64 RDPQBaseAddress; /* 0x00 */ 247 U32 Reserved1; /* 0x08 */ 248 U32 Reserved2; /* 0x0C */ 249} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 250 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 251 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry; 252 253/* IOCInit Reply message */ 254typedef struct _MPI2_IOC_INIT_REPLY 255{ 256 U8 WhoInit; /* 0x00 */ 257 U8 Reserved1; /* 0x01 */ 258 U8 MsgLength; /* 0x02 */ 259 U8 Function; /* 0x03 */ 260 U16 Reserved2; /* 0x04 */ 261 U8 Reserved3; /* 0x06 */ 262 U8 MsgFlags; /* 0x07 */ 263 U8 VP_ID; /* 0x08 */ 264 U8 VF_ID; /* 0x09 */ 265 U16 Reserved4; /* 0x0A */ 266 U16 Reserved5; /* 0x0C */ 267 U16 IOCStatus; /* 0x0E */ 268 U32 IOCLogInfo; /* 0x10 */ 269} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 270 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 271 272 273/**************************************************************************** 274* IOCFacts message 275****************************************************************************/ 276 277/* IOCFacts Request message */ 278typedef struct _MPI2_IOC_FACTS_REQUEST 279{ 280 U16 Reserved1; /* 0x00 */ 281 U8 ChainOffset; /* 0x02 */ 282 U8 Function; /* 0x03 */ 283 U16 Reserved2; /* 0x04 */ 284 U8 Reserved3; /* 0x06 */ 285 U8 MsgFlags; /* 0x07 */ 286 U8 VP_ID; /* 0x08 */ 287 U8 VF_ID; /* 0x09 */ 288 U16 Reserved4; /* 0x0A */ 289} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 290 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 291 292 293/* IOCFacts Reply message */ 294typedef struct _MPI2_IOC_FACTS_REPLY 295{ 296 U16 MsgVersion; /* 0x00 */ 297 U8 MsgLength; /* 0x02 */ 298 U8 Function; /* 0x03 */ 299 U16 HeaderVersion; /* 0x04 */ 300 U8 IOCNumber; /* 0x06 */ 301 U8 MsgFlags; /* 0x07 */ 302 U8 VP_ID; /* 0x08 */ 303 U8 VF_ID; /* 0x09 */ 304 U16 Reserved1; /* 0x0A */ 305 U16 IOCExceptions; /* 0x0C */ 306 U16 IOCStatus; /* 0x0E */ 307 U32 IOCLogInfo; /* 0x10 */ 308 U8 MaxChainDepth; /* 0x14 */ 309 U8 WhoInit; /* 0x15 */ 310 U8 NumberOfPorts; /* 0x16 */ 311 U8 MaxMSIxVectors; /* 0x17 */ 312 U16 RequestCredit; /* 0x18 */ 313 U16 ProductID; /* 0x1A */ 314 U32 IOCCapabilities; /* 0x1C */ 315 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 316 U16 IOCRequestFrameSize; /* 0x24 */ 317 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */ 318 U16 MaxInitiators; /* 0x28 */ 319 U16 MaxTargets; /* 0x2A */ 320 U16 MaxSasExpanders; /* 0x2C */ 321 U16 MaxEnclosures; /* 0x2E */ 322 U16 ProtocolFlags; /* 0x30 */ 323 U16 HighPriorityCredit; /* 0x32 */ 324 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 325 U8 ReplyFrameSize; /* 0x36 */ 326 U8 MaxVolumes; /* 0x37 */ 327 U16 MaxDevHandle; /* 0x38 */ 328 U16 MaxPersistentEntries; /* 0x3A */ 329 U16 MinDevHandle; /* 0x3C */ 330 U16 Reserved4; /* 0x3E */ 331} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 332 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 333 334/* MsgVersion */ 335#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 336#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 337#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 338#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 339 340/* HeaderVersion */ 341#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 342#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 343#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 344#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 345 346/* IOCExceptions */ 347#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 348#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 349 350#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 351#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 352#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 353#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 354#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 355 356#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 357#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 358#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 359#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 360#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 361 362/* defines for WhoInit field are after the IOCInit Request */ 363 364/* ProductID field uses MPI2_FW_HEADER_PID_ */ 365 366/* IOCCapabilities */ 367#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 368#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 369#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 370#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 371#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 372#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 373#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 374#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 375#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 376#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 377#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 378#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 379#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 380#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 381#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 382 383/* ProtocolFlags */ 384#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 385#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 386 387 388/**************************************************************************** 389* PortFacts message 390****************************************************************************/ 391 392/* PortFacts Request message */ 393typedef struct _MPI2_PORT_FACTS_REQUEST 394{ 395 U16 Reserved1; /* 0x00 */ 396 U8 ChainOffset; /* 0x02 */ 397 U8 Function; /* 0x03 */ 398 U16 Reserved2; /* 0x04 */ 399 U8 PortNumber; /* 0x06 */ 400 U8 MsgFlags; /* 0x07 */ 401 U8 VP_ID; /* 0x08 */ 402 U8 VF_ID; /* 0x09 */ 403 U16 Reserved3; /* 0x0A */ 404} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 405 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 406 407/* PortFacts Reply message */ 408typedef struct _MPI2_PORT_FACTS_REPLY 409{ 410 U16 Reserved1; /* 0x00 */ 411 U8 MsgLength; /* 0x02 */ 412 U8 Function; /* 0x03 */ 413 U16 Reserved2; /* 0x04 */ 414 U8 PortNumber; /* 0x06 */ 415 U8 MsgFlags; /* 0x07 */ 416 U8 VP_ID; /* 0x08 */ 417 U8 VF_ID; /* 0x09 */ 418 U16 Reserved3; /* 0x0A */ 419 U16 Reserved4; /* 0x0C */ 420 U16 IOCStatus; /* 0x0E */ 421 U32 IOCLogInfo; /* 0x10 */ 422 U8 Reserved5; /* 0x14 */ 423 U8 PortType; /* 0x15 */ 424 U16 Reserved6; /* 0x16 */ 425 U16 MaxPostedCmdBuffers; /* 0x18 */ 426 U16 Reserved7; /* 0x1A */ 427} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 428 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 429 430/* PortType values */ 431#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 432#define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 433#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 434#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 435#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 436 437 438/**************************************************************************** 439* PortEnable message 440****************************************************************************/ 441 442/* PortEnable Request message */ 443typedef struct _MPI2_PORT_ENABLE_REQUEST 444{ 445 U16 Reserved1; /* 0x00 */ 446 U8 ChainOffset; /* 0x02 */ 447 U8 Function; /* 0x03 */ 448 U8 Reserved2; /* 0x04 */ 449 U8 PortFlags; /* 0x05 */ 450 U8 Reserved3; /* 0x06 */ 451 U8 MsgFlags; /* 0x07 */ 452 U8 VP_ID; /* 0x08 */ 453 U8 VF_ID; /* 0x09 */ 454 U16 Reserved4; /* 0x0A */ 455} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 456 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 457 458 459/* PortEnable Reply message */ 460typedef struct _MPI2_PORT_ENABLE_REPLY 461{ 462 U16 Reserved1; /* 0x00 */ 463 U8 MsgLength; /* 0x02 */ 464 U8 Function; /* 0x03 */ 465 U8 Reserved2; /* 0x04 */ 466 U8 PortFlags; /* 0x05 */ 467 U8 Reserved3; /* 0x06 */ 468 U8 MsgFlags; /* 0x07 */ 469 U8 VP_ID; /* 0x08 */ 470 U8 VF_ID; /* 0x09 */ 471 U16 Reserved4; /* 0x0A */ 472 U16 Reserved5; /* 0x0C */ 473 U16 IOCStatus; /* 0x0E */ 474 U32 IOCLogInfo; /* 0x10 */ 475} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 476 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 477 478 479/**************************************************************************** 480* EventNotification message 481****************************************************************************/ 482 483/* EventNotification Request message */ 484#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 485 486typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 487{ 488 U16 Reserved1; /* 0x00 */ 489 U8 ChainOffset; /* 0x02 */ 490 U8 Function; /* 0x03 */ 491 U16 Reserved2; /* 0x04 */ 492 U8 Reserved3; /* 0x06 */ 493 U8 MsgFlags; /* 0x07 */ 494 U8 VP_ID; /* 0x08 */ 495 U8 VF_ID; /* 0x09 */ 496 U16 Reserved4; /* 0x0A */ 497 U32 Reserved5; /* 0x0C */ 498 U32 Reserved6; /* 0x10 */ 499 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 500 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 501 U16 SASNotifyPrimitiveMasks; /* 0x26 */ 502 U32 Reserved8; /* 0x28 */ 503} MPI2_EVENT_NOTIFICATION_REQUEST, 504 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 505 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 506 507 508/* EventNotification Reply message */ 509typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 510{ 511 U16 EventDataLength; /* 0x00 */ 512 U8 MsgLength; /* 0x02 */ 513 U8 Function; /* 0x03 */ 514 U16 Reserved1; /* 0x04 */ 515 U8 AckRequired; /* 0x06 */ 516 U8 MsgFlags; /* 0x07 */ 517 U8 VP_ID; /* 0x08 */ 518 U8 VF_ID; /* 0x09 */ 519 U16 Reserved2; /* 0x0A */ 520 U16 Reserved3; /* 0x0C */ 521 U16 IOCStatus; /* 0x0E */ 522 U32 IOCLogInfo; /* 0x10 */ 523 U16 Event; /* 0x14 */ 524 U16 Reserved4; /* 0x16 */ 525 U32 EventContext; /* 0x18 */ 526 U32 EventData[1]; /* 0x1C */ 527} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 528 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 529 530/* AckRequired */ 531#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 532#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 533 534/* Event */ 535#define MPI2_EVENT_LOG_DATA (0x0001) 536#define MPI2_EVENT_STATE_CHANGE (0x0002) 537#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 538#define MPI2_EVENT_EVENT_CHANGE (0x000A) 539#define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 540#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 541#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 542#define MPI2_EVENT_SAS_DISCOVERY (0x0016) 543#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 544#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 545#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 546#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 547#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 548#define MPI2_EVENT_IR_VOLUME (0x001E) 549#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 550#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 551#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 552#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 553#define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 554#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 555#define MPI2_EVENT_SAS_QUIESCE (0x0025) 556#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 557#define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 558#define MPI2_EVENT_HOST_MESSAGE (0x0028) 559#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 560#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 561#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 562 563 564/* Log Entry Added Event data */ 565 566/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 567#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 568 569typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 570{ 571 U64 TimeStamp; /* 0x00 */ 572 U32 Reserved1; /* 0x08 */ 573 U16 LogSequence; /* 0x0C */ 574 U16 LogEntryQualifier; /* 0x0E */ 575 U8 VP_ID; /* 0x10 */ 576 U8 VF_ID; /* 0x11 */ 577 U16 Reserved2; /* 0x12 */ 578 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 579} MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 580 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 581 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 582 583 584/* GPIO Interrupt Event data */ 585 586typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 587{ 588 U8 GPIONum; /* 0x00 */ 589 U8 Reserved1; /* 0x01 */ 590 U16 Reserved2; /* 0x02 */ 591} MPI2_EVENT_DATA_GPIO_INTERRUPT, 592 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 593 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 594 595 596/* Temperature Threshold Event data */ 597 598typedef struct _MPI2_EVENT_DATA_TEMPERATURE 599{ 600 U16 Status; /* 0x00 */ 601 U8 SensorNum; /* 0x02 */ 602 U8 Reserved1; /* 0x03 */ 603 U16 CurrentTemperature; /* 0x04 */ 604 U16 Reserved2; /* 0x06 */ 605 U32 Reserved3; /* 0x08 */ 606 U32 Reserved4; /* 0x0C */ 607} MPI2_EVENT_DATA_TEMPERATURE, 608 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE, 609 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t; 610 611/* Temperature Threshold Event data Status bits */ 612#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 613#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 614#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 615#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 616 617 618/* Host Message Event data */ 619 620typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE 621{ 622 U8 SourceVF_ID; /* 0x00 */ 623 U8 Reserved1; /* 0x01 */ 624 U16 Reserved2; /* 0x02 */ 625 U32 Reserved3; /* 0x04 */ 626 U32 HostData[1]; /* 0x08 */ 627} MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 628 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t; 629 630 631/* Power Performance Change Event */ 632 633typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE 634{ 635 U8 CurrentPowerMode; /* 0x00 */ 636 U8 PreviousPowerMode; /* 0x01 */ 637 U16 Reserved1; /* 0x02 */ 638} MPI2_EVENT_DATA_POWER_PERF_CHANGE, 639 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 640 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t; 641 642/* defines for CurrentPowerMode and PreviousPowerMode fields */ 643#define MPI2_EVENT_PM_INIT_MASK (0xC0) 644#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 645#define MPI2_EVENT_PM_INIT_HOST (0x40) 646#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 647#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 648 649#define MPI2_EVENT_PM_MODE_MASK (0x07) 650#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 651#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 652#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 653#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 654#define MPI2_EVENT_PM_MODE_STANDBY (0x06) 655 656 657/* Hard Reset Received Event data */ 658 659typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 660{ 661 U8 Reserved1; /* 0x00 */ 662 U8 Port; /* 0x01 */ 663 U16 Reserved2; /* 0x02 */ 664} MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 665 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 666 Mpi2EventDataHardResetReceived_t, 667 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 668 669 670/* Task Set Full Event data */ 671/* this event is obsolete */ 672 673typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 674{ 675 U16 DevHandle; /* 0x00 */ 676 U16 CurrentDepth; /* 0x02 */ 677} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 678 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 679 680 681/* SAS Device Status Change Event data */ 682 683typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 684{ 685 U16 TaskTag; /* 0x00 */ 686 U8 ReasonCode; /* 0x02 */ 687 U8 PhysicalPort; /* 0x03 */ 688 U8 ASC; /* 0x04 */ 689 U8 ASCQ; /* 0x05 */ 690 U16 DevHandle; /* 0x06 */ 691 U32 Reserved2; /* 0x08 */ 692 U64 SASAddress; /* 0x0C */ 693 U8 LUN[8]; /* 0x14 */ 694} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 695 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 696 Mpi2EventDataSasDeviceStatusChange_t, 697 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 698 699/* SAS Device Status Change Event data ReasonCode values */ 700#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 701#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 702#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 703#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 704#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 705#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 706#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 707#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 708#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 709#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 710#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 711#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 712#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 713 714 715/* Integrated RAID Operation Status Event data */ 716 717typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 718{ 719 U16 VolDevHandle; /* 0x00 */ 720 U16 Reserved1; /* 0x02 */ 721 U8 RAIDOperation; /* 0x04 */ 722 U8 PercentComplete; /* 0x05 */ 723 U16 Reserved2; /* 0x06 */ 724 U32 ElapsedSeconds; /* 0x08 */ 725} MPI2_EVENT_DATA_IR_OPERATION_STATUS, 726 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 727 Mpi2EventDataIrOperationStatus_t, 728 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 729 730/* Integrated RAID Operation Status Event data RAIDOperation values */ 731#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 732#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 733#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 734#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 735#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 736 737 738/* Integrated RAID Volume Event data */ 739 740typedef struct _MPI2_EVENT_DATA_IR_VOLUME 741{ 742 U16 VolDevHandle; /* 0x00 */ 743 U8 ReasonCode; /* 0x02 */ 744 U8 Reserved1; /* 0x03 */ 745 U32 NewValue; /* 0x04 */ 746 U32 PreviousValue; /* 0x08 */ 747} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 748 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 749 750/* Integrated RAID Volume Event data ReasonCode values */ 751#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 752#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 753#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 754 755 756/* Integrated RAID Physical Disk Event data */ 757 758typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 759{ 760 U16 Reserved1; /* 0x00 */ 761 U8 ReasonCode; /* 0x02 */ 762 U8 PhysDiskNum; /* 0x03 */ 763 U16 PhysDiskDevHandle; /* 0x04 */ 764 U16 Reserved2; /* 0x06 */ 765 U16 Slot; /* 0x08 */ 766 U16 EnclosureHandle; /* 0x0A */ 767 U32 NewValue; /* 0x0C */ 768 U32 PreviousValue; /* 0x10 */ 769} MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 770 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 771 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 772 773/* Integrated RAID Physical Disk Event data ReasonCode values */ 774#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 775#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 776#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 777 778 779/* Integrated RAID Configuration Change List Event data */ 780 781/* 782 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 783 * one and check NumElements at runtime. 784 */ 785#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 786#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 787#endif 788 789typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 790{ 791 U16 ElementFlags; /* 0x00 */ 792 U16 VolDevHandle; /* 0x02 */ 793 U8 ReasonCode; /* 0x04 */ 794 U8 PhysDiskNum; /* 0x05 */ 795 U16 PhysDiskDevHandle; /* 0x06 */ 796} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 797 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 798 799/* IR Configuration Change List Event data ElementFlags values */ 800#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 801#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 802#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 803#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 804 805/* IR Configuration Change List Event data ReasonCode values */ 806#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 807#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 808#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 809#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 810#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 811#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 812#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 813#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 814#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 815 816typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 817{ 818 U8 NumElements; /* 0x00 */ 819 U8 Reserved1; /* 0x01 */ 820 U8 Reserved2; /* 0x02 */ 821 U8 ConfigNum; /* 0x03 */ 822 U32 Flags; /* 0x04 */ 823 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 824} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 825 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 826 Mpi2EventDataIrConfigChangeList_t, 827 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 828 829/* IR Configuration Change List Event data Flags values */ 830#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 831 832 833/* SAS Discovery Event data */ 834 835typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 836{ 837 U8 Flags; /* 0x00 */ 838 U8 ReasonCode; /* 0x01 */ 839 U8 PhysicalPort; /* 0x02 */ 840 U8 Reserved1; /* 0x03 */ 841 U32 DiscoveryStatus; /* 0x04 */ 842} MPI2_EVENT_DATA_SAS_DISCOVERY, 843 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 844 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 845 846/* SAS Discovery Event data Flags values */ 847#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 848#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 849 850/* SAS Discovery Event data ReasonCode values */ 851#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 852#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 853 854/* SAS Discovery Event data DiscoveryStatus values */ 855#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 856#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 857#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 858#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 859#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 860#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 861#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 862#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 863#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 864#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 865#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 866#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 867#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 868#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 869#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 870#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 871#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 872#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 873#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 874#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 875 876 877/* SAS Broadcast Primitive Event data */ 878 879typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 880{ 881 U8 PhyNum; /* 0x00 */ 882 U8 Port; /* 0x01 */ 883 U8 PortWidth; /* 0x02 */ 884 U8 Primitive; /* 0x03 */ 885} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 886 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 887 Mpi2EventDataSasBroadcastPrimitive_t, 888 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 889 890/* defines for the Primitive field */ 891#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 892#define MPI2_EVENT_PRIMITIVE_SES (0x02) 893#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 894#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 895#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 896#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 897#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 898#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 899 900 901/* SAS Notify Primitive Event data */ 902 903typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE 904{ 905 U8 PhyNum; /* 0x00 */ 906 U8 Port; /* 0x01 */ 907 U8 Reserved1; /* 0x02 */ 908 U8 Primitive; /* 0x03 */ 909} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 910 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 911 Mpi2EventDataSasNotifyPrimitive_t, 912 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t; 913 914/* defines for the Primitive field */ 915#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 916#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 917#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 918#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 919 920 921/* SAS Initiator Device Status Change Event data */ 922 923typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 924{ 925 U8 ReasonCode; /* 0x00 */ 926 U8 PhysicalPort; /* 0x01 */ 927 U16 DevHandle; /* 0x02 */ 928 U64 SASAddress; /* 0x04 */ 929} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 930 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 931 Mpi2EventDataSasInitDevStatusChange_t, 932 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 933 934/* SAS Initiator Device Status Change event ReasonCode values */ 935#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 936#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 937 938 939/* SAS Initiator Device Table Overflow Event data */ 940 941typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 942{ 943 U16 MaxInit; /* 0x00 */ 944 U16 CurrentInit; /* 0x02 */ 945 U64 SASAddress; /* 0x04 */ 946} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 947 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 948 Mpi2EventDataSasInitTableOverflow_t, 949 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 950 951 952/* SAS Topology Change List Event data */ 953 954/* 955 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 956 * one and check NumEntries at runtime. 957 */ 958#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 959#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 960#endif 961 962typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 963{ 964 U16 AttachedDevHandle; /* 0x00 */ 965 U8 LinkRate; /* 0x02 */ 966 U8 PhyStatus; /* 0x03 */ 967} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 968 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 969 970typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 971{ 972 U16 EnclosureHandle; /* 0x00 */ 973 U16 ExpanderDevHandle; /* 0x02 */ 974 U8 NumPhys; /* 0x04 */ 975 U8 Reserved1; /* 0x05 */ 976 U16 Reserved2; /* 0x06 */ 977 U8 NumEntries; /* 0x08 */ 978 U8 StartPhyNum; /* 0x09 */ 979 U8 ExpStatus; /* 0x0A */ 980 U8 PhysicalPort; /* 0x0B */ 981 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 982} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 983 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 984 Mpi2EventDataSasTopologyChangeList_t, 985 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 986 987/* values for the ExpStatus field */ 988#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 989#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 990#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 991#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 992#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 993 994/* defines for the LinkRate field */ 995#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 996#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 997#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 998#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 999 1000#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 1001#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 1002#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 1003#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 1004#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 1005#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 1006#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 1007#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 1008#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 1009#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 1010#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 1011 1012/* values for the PhyStatus field */ 1013#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 1014#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 1015/* values for the PhyStatus ReasonCode sub-field */ 1016#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 1017#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 1018#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 1019#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 1020#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 1021#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 1022 1023 1024/* SAS Enclosure Device Status Change Event data */ 1025 1026typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 1027{ 1028 U16 EnclosureHandle; /* 0x00 */ 1029 U8 ReasonCode; /* 0x02 */ 1030 U8 PhysicalPort; /* 0x03 */ 1031 U64 EnclosureLogicalID; /* 0x04 */ 1032 U16 NumSlots; /* 0x0C */ 1033 U16 StartSlot; /* 0x0E */ 1034 U32 PhyBits; /* 0x10 */ 1035} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1036 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1037 Mpi2EventDataSasEnclDevStatusChange_t, 1038 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 1039 1040/* SAS Enclosure Device Status Change event ReasonCode values */ 1041#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 1042#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 1043 1044 1045/* SAS PHY Counter Event data */ 1046 1047typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 1048{ 1049 U64 TimeStamp; /* 0x00 */ 1050 U32 Reserved1; /* 0x08 */ 1051 U8 PhyEventCode; /* 0x0C */ 1052 U8 PhyNum; /* 0x0D */ 1053 U16 Reserved2; /* 0x0E */ 1054 U32 PhyEventInfo; /* 0x10 */ 1055 U8 CounterType; /* 0x14 */ 1056 U8 ThresholdWindow; /* 0x15 */ 1057 U8 TimeUnits; /* 0x16 */ 1058 U8 Reserved3; /* 0x17 */ 1059 U32 EventThreshold; /* 0x18 */ 1060 U16 ThresholdFlags; /* 0x1C */ 1061 U16 Reserved4; /* 0x1E */ 1062} MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1063 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1064 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 1065 1066/* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 1067 1068/* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1069 1070/* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1071 1072/* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1073 1074 1075/* SAS Quiesce Event data */ 1076 1077typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 1078{ 1079 U8 ReasonCode; /* 0x00 */ 1080 U8 Reserved1; /* 0x01 */ 1081 U16 Reserved2; /* 0x02 */ 1082 U32 Reserved3; /* 0x04 */ 1083} MPI2_EVENT_DATA_SAS_QUIESCE, 1084 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1085 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 1086 1087/* SAS Quiesce Event data ReasonCode values */ 1088#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1089#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1090 1091 1092/* Host Based Discovery Phy Event data */ 1093 1094typedef struct _MPI2_EVENT_HBD_PHY_SAS 1095{ 1096 U8 Flags; /* 0x00 */ 1097 U8 NegotiatedLinkRate; /* 0x01 */ 1098 U8 PhyNum; /* 0x02 */ 1099 U8 PhysicalPort; /* 0x03 */ 1100 U32 Reserved1; /* 0x04 */ 1101 U8 InitialFrame[28]; /* 0x08 */ 1102} MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 1103 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 1104 1105/* values for the Flags field */ 1106#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1107#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1108 1109/* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 1110 1111typedef union _MPI2_EVENT_HBD_DESCRIPTOR 1112{ 1113 MPI2_EVENT_HBD_PHY_SAS Sas; 1114} MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1115 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 1116 1117typedef struct _MPI2_EVENT_DATA_HBD_PHY 1118{ 1119 U8 DescriptorType; /* 0x00 */ 1120 U8 Reserved1; /* 0x01 */ 1121 U16 Reserved2; /* 0x02 */ 1122 U32 Reserved3; /* 0x04 */ 1123 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 1124} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 1125 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 1126 1127/* values for the DescriptorType field */ 1128#define MPI2_EVENT_HBD_DT_SAS (0x01) 1129 1130 1131 1132/**************************************************************************** 1133* EventAck message 1134****************************************************************************/ 1135 1136/* EventAck Request message */ 1137typedef struct _MPI2_EVENT_ACK_REQUEST 1138{ 1139 U16 Reserved1; /* 0x00 */ 1140 U8 ChainOffset; /* 0x02 */ 1141 U8 Function; /* 0x03 */ 1142 U16 Reserved2; /* 0x04 */ 1143 U8 Reserved3; /* 0x06 */ 1144 U8 MsgFlags; /* 0x07 */ 1145 U8 VP_ID; /* 0x08 */ 1146 U8 VF_ID; /* 0x09 */ 1147 U16 Reserved4; /* 0x0A */ 1148 U16 Event; /* 0x0C */ 1149 U16 Reserved5; /* 0x0E */ 1150 U32 EventContext; /* 0x10 */ 1151} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1152 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1153 1154 1155/* EventAck Reply message */ 1156typedef struct _MPI2_EVENT_ACK_REPLY 1157{ 1158 U16 Reserved1; /* 0x00 */ 1159 U8 MsgLength; /* 0x02 */ 1160 U8 Function; /* 0x03 */ 1161 U16 Reserved2; /* 0x04 */ 1162 U8 Reserved3; /* 0x06 */ 1163 U8 MsgFlags; /* 0x07 */ 1164 U8 VP_ID; /* 0x08 */ 1165 U8 VF_ID; /* 0x09 */ 1166 U16 Reserved4; /* 0x0A */ 1167 U16 Reserved5; /* 0x0C */ 1168 U16 IOCStatus; /* 0x0E */ 1169 U32 IOCLogInfo; /* 0x10 */ 1170} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1171 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1172 1173 1174/**************************************************************************** 1175* SendHostMessage message 1176****************************************************************************/ 1177 1178/* SendHostMessage Request message */ 1179typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST 1180{ 1181 U16 HostDataLength; /* 0x00 */ 1182 U8 ChainOffset; /* 0x02 */ 1183 U8 Function; /* 0x03 */ 1184 U16 Reserved1; /* 0x04 */ 1185 U8 Reserved2; /* 0x06 */ 1186 U8 MsgFlags; /* 0x07 */ 1187 U8 VP_ID; /* 0x08 */ 1188 U8 VF_ID; /* 0x09 */ 1189 U16 Reserved3; /* 0x0A */ 1190 U8 Reserved4; /* 0x0C */ 1191 U8 DestVF_ID; /* 0x0D */ 1192 U16 Reserved5; /* 0x0E */ 1193 U32 Reserved6; /* 0x10 */ 1194 U32 Reserved7; /* 0x14 */ 1195 U32 Reserved8; /* 0x18 */ 1196 U32 Reserved9; /* 0x1C */ 1197 U32 Reserved10; /* 0x20 */ 1198 U32 HostData[1]; /* 0x24 */ 1199} MPI2_SEND_HOST_MESSAGE_REQUEST, 1200 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1201 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t; 1202 1203 1204/* SendHostMessage Reply message */ 1205typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY 1206{ 1207 U16 HostDataLength; /* 0x00 */ 1208 U8 MsgLength; /* 0x02 */ 1209 U8 Function; /* 0x03 */ 1210 U16 Reserved1; /* 0x04 */ 1211 U8 Reserved2; /* 0x06 */ 1212 U8 MsgFlags; /* 0x07 */ 1213 U8 VP_ID; /* 0x08 */ 1214 U8 VF_ID; /* 0x09 */ 1215 U16 Reserved3; /* 0x0A */ 1216 U16 Reserved4; /* 0x0C */ 1217 U16 IOCStatus; /* 0x0E */ 1218 U32 IOCLogInfo; /* 0x10 */ 1219} MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1220 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t; 1221 1222 1223/**************************************************************************** 1224* FWDownload message 1225****************************************************************************/ 1226 1227/* MPI v2.0 FWDownload Request message */ 1228typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1229{ 1230 U8 ImageType; /* 0x00 */ 1231 U8 Reserved1; /* 0x01 */ 1232 U8 ChainOffset; /* 0x02 */ 1233 U8 Function; /* 0x03 */ 1234 U16 Reserved2; /* 0x04 */ 1235 U8 Reserved3; /* 0x06 */ 1236 U8 MsgFlags; /* 0x07 */ 1237 U8 VP_ID; /* 0x08 */ 1238 U8 VF_ID; /* 0x09 */ 1239 U16 Reserved4; /* 0x0A */ 1240 U32 TotalImageSize; /* 0x0C */ 1241 U32 Reserved5; /* 0x10 */ 1242 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1243} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1244 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1245 1246#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1247 1248#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1249#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1250#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1251#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1252#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1253#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1254#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1255#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1256#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */ 1257#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1258 1259/* MPI v2.0 FWDownload TransactionContext Element */ 1260typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1261{ 1262 U8 Reserved1; /* 0x00 */ 1263 U8 ContextSize; /* 0x01 */ 1264 U8 DetailsLength; /* 0x02 */ 1265 U8 Flags; /* 0x03 */ 1266 U32 Reserved2; /* 0x04 */ 1267 U32 ImageOffset; /* 0x08 */ 1268 U32 ImageSize; /* 0x0C */ 1269} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1270 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1271 1272 1273/* MPI v2.5 FWDownload Request message */ 1274typedef struct _MPI25_FW_DOWNLOAD_REQUEST 1275{ 1276 U8 ImageType; /* 0x00 */ 1277 U8 Reserved1; /* 0x01 */ 1278 U8 ChainOffset; /* 0x02 */ 1279 U8 Function; /* 0x03 */ 1280 U16 Reserved2; /* 0x04 */ 1281 U8 Reserved3; /* 0x06 */ 1282 U8 MsgFlags; /* 0x07 */ 1283 U8 VP_ID; /* 0x08 */ 1284 U8 VF_ID; /* 0x09 */ 1285 U16 Reserved4; /* 0x0A */ 1286 U32 TotalImageSize; /* 0x0C */ 1287 U32 Reserved5; /* 0x10 */ 1288 U32 Reserved6; /* 0x14 */ 1289 U32 ImageOffset; /* 0x18 */ 1290 U32 ImageSize; /* 0x1C */ 1291 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1292} MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST, 1293 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest; 1294 1295 1296/* FWDownload Reply message */ 1297typedef struct _MPI2_FW_DOWNLOAD_REPLY 1298{ 1299 U8 ImageType; /* 0x00 */ 1300 U8 Reserved1; /* 0x01 */ 1301 U8 MsgLength; /* 0x02 */ 1302 U8 Function; /* 0x03 */ 1303 U16 Reserved2; /* 0x04 */ 1304 U8 Reserved3; /* 0x06 */ 1305 U8 MsgFlags; /* 0x07 */ 1306 U8 VP_ID; /* 0x08 */ 1307 U8 VF_ID; /* 0x09 */ 1308 U16 Reserved4; /* 0x0A */ 1309 U16 Reserved5; /* 0x0C */ 1310 U16 IOCStatus; /* 0x0E */ 1311 U32 IOCLogInfo; /* 0x10 */ 1312} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1313 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1314 1315 1316/**************************************************************************** 1317* FWUpload message 1318****************************************************************************/ 1319 1320/* MPI v2.0 FWUpload Request message */ 1321typedef struct _MPI2_FW_UPLOAD_REQUEST 1322{ 1323 U8 ImageType; /* 0x00 */ 1324 U8 Reserved1; /* 0x01 */ 1325 U8 ChainOffset; /* 0x02 */ 1326 U8 Function; /* 0x03 */ 1327 U16 Reserved2; /* 0x04 */ 1328 U8 Reserved3; /* 0x06 */ 1329 U8 MsgFlags; /* 0x07 */ 1330 U8 VP_ID; /* 0x08 */ 1331 U8 VF_ID; /* 0x09 */ 1332 U16 Reserved4; /* 0x0A */ 1333 U32 Reserved5; /* 0x0C */ 1334 U32 Reserved6; /* 0x10 */ 1335 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1336} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1337 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1338 1339#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1340#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1341#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1342#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1343#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1344#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1345#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1346#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1347#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1348#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1349 1350/* MPI v2.0 FWUpload TransactionContext Element */ 1351typedef struct _MPI2_FW_UPLOAD_TCSGE 1352{ 1353 U8 Reserved1; /* 0x00 */ 1354 U8 ContextSize; /* 0x01 */ 1355 U8 DetailsLength; /* 0x02 */ 1356 U8 Flags; /* 0x03 */ 1357 U32 Reserved2; /* 0x04 */ 1358 U32 ImageOffset; /* 0x08 */ 1359 U32 ImageSize; /* 0x0C */ 1360} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1361 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1362 1363 1364/* MPI v2.5 FWUpload Request message */ 1365typedef struct _MPI25_FW_UPLOAD_REQUEST 1366{ 1367 U8 ImageType; /* 0x00 */ 1368 U8 Reserved1; /* 0x01 */ 1369 U8 ChainOffset; /* 0x02 */ 1370 U8 Function; /* 0x03 */ 1371 U16 Reserved2; /* 0x04 */ 1372 U8 Reserved3; /* 0x06 */ 1373 U8 MsgFlags; /* 0x07 */ 1374 U8 VP_ID; /* 0x08 */ 1375 U8 VF_ID; /* 0x09 */ 1376 U16 Reserved4; /* 0x0A */ 1377 U32 Reserved5; /* 0x0C */ 1378 U32 Reserved6; /* 0x10 */ 1379 U32 Reserved7; /* 0x14 */ 1380 U32 ImageOffset; /* 0x18 */ 1381 U32 ImageSize; /* 0x1C */ 1382 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1383} MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST, 1384 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t; 1385 1386 1387/* FWUpload Reply message */ 1388typedef struct _MPI2_FW_UPLOAD_REPLY 1389{ 1390 U8 ImageType; /* 0x00 */ 1391 U8 Reserved1; /* 0x01 */ 1392 U8 MsgLength; /* 0x02 */ 1393 U8 Function; /* 0x03 */ 1394 U16 Reserved2; /* 0x04 */ 1395 U8 Reserved3; /* 0x06 */ 1396 U8 MsgFlags; /* 0x07 */ 1397 U8 VP_ID; /* 0x08 */ 1398 U8 VF_ID; /* 0x09 */ 1399 U16 Reserved4; /* 0x0A */ 1400 U16 Reserved5; /* 0x0C */ 1401 U16 IOCStatus; /* 0x0E */ 1402 U32 IOCLogInfo; /* 0x10 */ 1403 U32 ActualImageSize; /* 0x14 */ 1404} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1405 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1406 1407 1408/* FW Image Header */ 1409typedef struct _MPI2_FW_IMAGE_HEADER 1410{ 1411 U32 Signature; /* 0x00 */ 1412 U32 Signature0; /* 0x04 */ 1413 U32 Signature1; /* 0x08 */ 1414 U32 Signature2; /* 0x0C */ 1415 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1416 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1417 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1418 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1419 U16 VendorID; /* 0x20 */ 1420 U16 ProductID; /* 0x22 */ 1421 U16 ProtocolFlags; /* 0x24 */ 1422 U16 Reserved26; /* 0x26 */ 1423 U32 IOCCapabilities; /* 0x28 */ 1424 U32 ImageSize; /* 0x2C */ 1425 U32 NextImageHeaderOffset; /* 0x30 */ 1426 U32 Checksum; /* 0x34 */ 1427 U32 Reserved38; /* 0x38 */ 1428 U32 Reserved3C; /* 0x3C */ 1429 U32 Reserved40; /* 0x40 */ 1430 U32 Reserved44; /* 0x44 */ 1431 U32 Reserved48; /* 0x48 */ 1432 U32 Reserved4C; /* 0x4C */ 1433 U32 Reserved50; /* 0x50 */ 1434 U32 Reserved54; /* 0x54 */ 1435 U32 Reserved58; /* 0x58 */ 1436 U32 Reserved5C; /* 0x5C */ 1437 U32 Reserved60; /* 0x60 */ 1438 U32 FirmwareVersionNameWhat; /* 0x64 */ 1439 U8 FirmwareVersionName[32]; /* 0x68 */ 1440 U32 VendorNameWhat; /* 0x88 */ 1441 U8 VendorName[32]; /* 0x8C */ 1442 U32 PackageNameWhat; /* 0x88 */ 1443 U8 PackageName[32]; /* 0x8C */ 1444 U32 ReservedD0; /* 0xD0 */ 1445 U32 ReservedD4; /* 0xD4 */ 1446 U32 ReservedD8; /* 0xD8 */ 1447 U32 ReservedDC; /* 0xDC */ 1448 U32 ReservedE0; /* 0xE0 */ 1449 U32 ReservedE4; /* 0xE4 */ 1450 U32 ReservedE8; /* 0xE8 */ 1451 U32 ReservedEC; /* 0xEC */ 1452 U32 ReservedF0; /* 0xF0 */ 1453 U32 ReservedF4; /* 0xF4 */ 1454 U32 ReservedF8; /* 0xF8 */ 1455 U32 ReservedFC; /* 0xFC */ 1456} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1457 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1458 1459/* Signature field */ 1460#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1461#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1462#define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1463 1464/* Signature0 field */ 1465#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1466#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1467 1468/* Signature1 field */ 1469#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1470#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1471 1472/* Signature2 field */ 1473#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1474#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1475 1476 1477/* defines for using the ProductID field */ 1478#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1479#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1480 1481#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1482#define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1483#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1484#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1485 1486 1487#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1488/* SAS ProductID Family bits */ 1489#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1490#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1491#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) 1492 1493/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1494 1495/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1496 1497 1498#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1499#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1500#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1501 1502#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1503 1504#define MPI2_FW_HEADER_SIZE (0x100) 1505 1506 1507/* Extended Image Header */ 1508typedef struct _MPI2_EXT_IMAGE_HEADER 1509 1510{ 1511 U8 ImageType; /* 0x00 */ 1512 U8 Reserved1; /* 0x01 */ 1513 U16 Reserved2; /* 0x02 */ 1514 U32 Checksum; /* 0x04 */ 1515 U32 ImageSize; /* 0x08 */ 1516 U32 NextImageHeaderOffset; /* 0x0C */ 1517 U32 PackageVersion; /* 0x10 */ 1518 U32 Reserved3; /* 0x14 */ 1519 U32 Reserved4; /* 0x18 */ 1520 U32 Reserved5; /* 0x1C */ 1521 U8 IdentifyString[32]; /* 0x20 */ 1522} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1523 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1524 1525/* useful offsets */ 1526#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1527#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1528#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1529 1530#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1531 1532/* defines for the ImageType field */ 1533#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1534#define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1535#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1536#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1537#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1538#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1539#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1540#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1541#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) /* MPI v2.5 and newer */ 1542#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) 1543#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) 1544 1545#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */ 1546 1547 1548 1549/* FLASH Layout Extended Image Data */ 1550 1551/* 1552 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1553 * one and check RegionsPerLayout at runtime. 1554 */ 1555#ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1556#define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1557#endif 1558 1559/* 1560 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1561 * one and check NumberOfLayouts at runtime. 1562 */ 1563#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1564#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1565#endif 1566 1567typedef struct _MPI2_FLASH_REGION 1568{ 1569 U8 RegionType; /* 0x00 */ 1570 U8 Reserved1; /* 0x01 */ 1571 U16 Reserved2; /* 0x02 */ 1572 U32 RegionOffset; /* 0x04 */ 1573 U32 RegionSize; /* 0x08 */ 1574 U32 Reserved3; /* 0x0C */ 1575} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1576 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1577 1578typedef struct _MPI2_FLASH_LAYOUT 1579{ 1580 U32 FlashSize; /* 0x00 */ 1581 U32 Reserved1; /* 0x04 */ 1582 U32 Reserved2; /* 0x08 */ 1583 U32 Reserved3; /* 0x0C */ 1584 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1585} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1586 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1587 1588typedef struct _MPI2_FLASH_LAYOUT_DATA 1589{ 1590 U8 ImageRevision; /* 0x00 */ 1591 U8 Reserved1; /* 0x01 */ 1592 U8 SizeOfRegion; /* 0x02 */ 1593 U8 Reserved2; /* 0x03 */ 1594 U16 NumberOfLayouts; /* 0x04 */ 1595 U16 RegionsPerLayout; /* 0x06 */ 1596 U16 MinimumSectorAlignment; /* 0x08 */ 1597 U16 Reserved3; /* 0x0A */ 1598 U32 Reserved4; /* 0x0C */ 1599 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1600} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1601 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1602 1603/* defines for the RegionType field */ 1604#define MPI2_FLASH_REGION_UNUSED (0x00) 1605#define MPI2_FLASH_REGION_FIRMWARE (0x01) 1606#define MPI2_FLASH_REGION_BIOS (0x02) 1607#define MPI2_FLASH_REGION_NVDATA (0x03) 1608#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1609#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1610#define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1611#define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1612#define MPI2_FLASH_REGION_MEGARAID (0x09) 1613#define MPI2_FLASH_REGION_INIT (0x0A) 1614 1615/* ImageRevision */ 1616#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1617 1618 1619 1620/* Supported Devices Extended Image Data */ 1621 1622/* 1623 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1624 * one and check NumberOfDevices at runtime. 1625 */ 1626#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1627#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1628#endif 1629 1630typedef struct _MPI2_SUPPORTED_DEVICE 1631{ 1632 U16 DeviceID; /* 0x00 */ 1633 U16 VendorID; /* 0x02 */ 1634 U16 DeviceIDMask; /* 0x04 */ 1635 U16 Reserved1; /* 0x06 */ 1636 U8 LowPCIRev; /* 0x08 */ 1637 U8 HighPCIRev; /* 0x09 */ 1638 U16 Reserved2; /* 0x0A */ 1639 U32 Reserved3; /* 0x0C */ 1640} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1641 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1642 1643typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1644{ 1645 U8 ImageRevision; /* 0x00 */ 1646 U8 Reserved1; /* 0x01 */ 1647 U8 NumberOfDevices; /* 0x02 */ 1648 U8 Reserved2; /* 0x03 */ 1649 U32 Reserved3; /* 0x04 */ 1650 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1651} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1652 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1653 1654/* ImageRevision */ 1655#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1656 1657 1658/* Init Extended Image Data */ 1659 1660typedef struct _MPI2_INIT_IMAGE_FOOTER 1661 1662{ 1663 U32 BootFlags; /* 0x00 */ 1664 U32 ImageSize; /* 0x04 */ 1665 U32 Signature0; /* 0x08 */ 1666 U32 Signature1; /* 0x0C */ 1667 U32 Signature2; /* 0x10 */ 1668 U32 ResetVector; /* 0x14 */ 1669} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1670 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1671 1672/* defines for the BootFlags field */ 1673#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1674 1675/* defines for the ImageSize field */ 1676#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1677 1678/* defines for the Signature0 field */ 1679#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1680#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1681 1682/* defines for the Signature1 field */ 1683#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1684#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1685 1686/* defines for the Signature2 field */ 1687#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1688#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1689 1690/* Signature fields as individual bytes */ 1691#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1692#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1693#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1694#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1695 1696#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1697#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1698#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1699#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1700 1701#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1702#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1703#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1704#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1705 1706/* defines for the ResetVector field */ 1707#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1708 1709 1710/* Encrypted Hash Extended Image Data */ 1711 1712typedef struct _MPI25_ENCRYPTED_HASH_ENTRY 1713{ 1714 U8 HashImageType; /* 0x00 */ 1715 U8 HashAlgorithm; /* 0x01 */ 1716 U8 EncryptionAlgorithm; /* 0x02 */ 1717 U8 Reserved1; /* 0x03 */ 1718 U32 Reserved2; /* 0x04 */ 1719 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ 1720} MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY, 1721 Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t; 1722 1723/* values for HashImageType */ 1724#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) 1725#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) 1726#define MPI25_HASH_IMAGE_TYPE_BIOS (0x02) 1727 1728/* values for HashAlgorithm */ 1729#define MPI25_HASH_ALGORITHM_UNUSED (0x00) 1730#define MPI25_HASH_ALGORITHM_SHA256 (0x01) 1731 1732/* values for EncryptionAlgorithm */ 1733#define MPI25_ENCRYPTION_ALG_UNUSED (0x00) 1734#define MPI25_ENCRYPTION_ALG_RSA256 (0x01) 1735 1736typedef struct _MPI25_ENCRYPTED_HASH_DATA 1737{ 1738 U8 ImageVersion; /* 0x00 */ 1739 U8 NumHash; /* 0x01 */ 1740 U16 Reserved1; /* 0x02 */ 1741 U32 Reserved2; /* 0x04 */ 1742 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ /* variable number of entries */ 1743} MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA, 1744 Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t; 1745 1746/**************************************************************************** 1747* PowerManagementControl message 1748****************************************************************************/ 1749 1750/* PowerManagementControl Request message */ 1751typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1752{ 1753 U8 Feature; /* 0x00 */ 1754 U8 Reserved1; /* 0x01 */ 1755 U8 ChainOffset; /* 0x02 */ 1756 U8 Function; /* 0x03 */ 1757 U16 Reserved2; /* 0x04 */ 1758 U8 Reserved3; /* 0x06 */ 1759 U8 MsgFlags; /* 0x07 */ 1760 U8 VP_ID; /* 0x08 */ 1761 U8 VF_ID; /* 0x09 */ 1762 U16 Reserved4; /* 0x0A */ 1763 U8 Parameter1; /* 0x0C */ 1764 U8 Parameter2; /* 0x0D */ 1765 U8 Parameter3; /* 0x0E */ 1766 U8 Parameter4; /* 0x0F */ 1767 U32 Reserved5; /* 0x10 */ 1768 U32 Reserved6; /* 0x14 */ 1769} MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1770 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1771 1772/* defines for the Feature field */ 1773#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1774#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1775#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */ 1776#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1777#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */ 1778#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1779#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1780 1781/* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1782/* Parameter1 contains a PHY number */ 1783/* Parameter2 indicates power condition action using these defines */ 1784#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1785#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1786#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1787/* Parameter3 and Parameter4 are reserved */ 1788 1789/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1790/* Parameter1 contains SAS port width modulation group number */ 1791/* Parameter2 indicates IOC action using these defines */ 1792#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1793#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1794#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1795/* Parameter3 indicates desired modulation level using these defines */ 1796#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1797#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1798#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1799#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1800/* Parameter4 is reserved */ 1801 1802/* this next set (_PCIE_LINK) is obsolete */ 1803/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1804/* Parameter1 indicates desired PCIe link speed using these defines */ 1805#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */ 1806#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */ 1807#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */ 1808/* Parameter2 indicates desired PCIe link width using these defines */ 1809#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */ 1810#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */ 1811#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */ 1812#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */ 1813/* Parameter3 and Parameter4 are reserved */ 1814 1815/* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1816/* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1817#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1818#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1819#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1820#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1821/* Parameter2, Parameter3, and Parameter4 are reserved */ 1822 1823/* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */ 1824/* Parameter1 indicates host action regarding global power management mode */ 1825#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 1826#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 1827#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 1828/* Parameter2 indicates the requested global power management mode */ 1829#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 1830#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 1831#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 1832/* Parameter3 and Parameter4 are reserved */ 1833 1834 1835/* PowerManagementControl Reply message */ 1836typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1837{ 1838 U8 Feature; /* 0x00 */ 1839 U8 Reserved1; /* 0x01 */ 1840 U8 MsgLength; /* 0x02 */ 1841 U8 Function; /* 0x03 */ 1842 U16 Reserved2; /* 0x04 */ 1843 U8 Reserved3; /* 0x06 */ 1844 U8 MsgFlags; /* 0x07 */ 1845 U8 VP_ID; /* 0x08 */ 1846 U8 VF_ID; /* 0x09 */ 1847 U16 Reserved4; /* 0x0A */ 1848 U16 Reserved5; /* 0x0C */ 1849 U16 IOCStatus; /* 0x0E */ 1850 U32 IOCLogInfo; /* 0x10 */ 1851} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1852 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1853 1854 1855#endif 1856 1857