mlxvar.h revision 51973
1/*- 2 * Copyright (c) 1999 Michael Smith 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/mlx/mlxvar.h 51973 1999-10-07 02:20:32Z msmith $ 27 */ 28 29/* 30 * We could actually use all 33 segments, but using only 32 means that 31 * each scatter/gather map is 256 bytes in size, and thus we don't have to worry about 32 * maps crossing page boundaries. 33 */ 34#define MLX_NSEG 32 /* max scatter/gather segments we use */ 35#define MLX_NSLOTS 256 /* max number of command slots */ 36 37#define MLX_CFG_BASE0 0x10 /* first region */ 38#define MLX_CFG_BASE1 0x14 /* second region (type 3 only) */ 39 40#define MLX_MAXDRIVES 32 41 42#define MLX_BLKSIZE 512 /* fixed feature */ 43 44/* 45 * Structure describing a System Drive as attached to the controller. 46 */ 47struct mlx_sysdrive 48{ 49 /* from MLX_CMD_ENQSYSDRIVE */ 50 u_int32_t ms_size; 51 int ms_state; 52 int ms_raidlevel; 53 54 /* synthetic geometry */ 55 int ms_cylinders; 56 int ms_heads; 57 int ms_sectors; 58 59 /* handle for attached driver */ 60 device_t ms_disk; 61}; 62 63/* 64 * Per-command control structure. 65 */ 66struct mlx_command 67{ 68 TAILQ_ENTRY(mlx_command) mc_link; /* list linkage */ 69 70 struct mlx_softc *mc_sc; /* controller that owns us */ 71 u_int8_t mc_slot; /* command slot we occupy */ 72 u_int16_t mc_status; /* command completion status */ 73 u_int8_t mc_mailbox[16]; /* command mailbox */ 74 u_int32_t mc_sgphys; /* physical address of s/g array in controller space */ 75 int mc_nsgent; /* number of entries in s/g map */ 76 int mc_flags; 77#define MLX_CMD_DATAIN (1<<0) 78#define MLX_CMD_DATAOUT (1<<1) 79#define MLX_CMD_PRIORITY (1<<2) /* high-priority command */ 80 81 void *mc_data; /* data buffer */ 82 size_t mc_length; 83 bus_dmamap_t mc_dmamap; /* DMA map for data */ 84 u_int32_t mc_dataphys; /* data buffer base address controller space */ 85 86 void (* mc_complete)(struct mlx_command *mc); /* completion handler */ 87 void *mc_private; /* submitter-private data or wait channel */ 88}; 89 90/* 91 * Per-controller structure. 92 */ 93struct mlx_softc 94{ 95 /* bus connections */ 96 device_t mlx_dev; 97 struct resource *mlx_mem; /* mailbox interface window */ 98 bus_space_handle_t mlx_bhandle; /* bus space handle */ 99 bus_space_tag_t mlx_btag; /* bus space tag */ 100 bus_dma_tag_t mlx_parent_dmat;/* parent DMA tag */ 101 bus_dma_tag_t mlx_buffer_dmat;/* data buffer DMA tag */ 102 struct resource *mlx_irq; /* interrupt */ 103 void *mlx_intr; /* interrupt handle */ 104 105 /* scatter/gather lists and their controller-visible mappings */ 106 struct mlx_sgentry *mlx_sgtable; /* s/g lists */ 107 u_int32_t mlx_sgbusaddr; /* s/g table base address in bus space */ 108 bus_dma_tag_t mlx_sg_dmat; /* s/g buffer DMA tag */ 109 bus_dmamap_t mlx_sg_dmamap; /* map for s/g buffers */ 110 111 /* controller limits and features */ 112 int mlx_hwid; /* hardware identifier */ 113 int mlx_maxiop; /* maximum number of I/O operations */ 114 int mlx_nchan; /* number of active channels */ 115 int mlx_maxiosize; /* largest I/O for this controller */ 116 int mlx_maxtarg; /* maximum number of targets per channel */ 117 int mlx_maxtags; /* maximum number of tags per device */ 118 int mlx_scsicap; /* SCSI capabilities */ 119 int mlx_feature; /* controller features/quirks */ 120#define MLX_FEAT_PAUSEWORKS (1<<0) /* channel pause works as expected */ 121 122 /* controller queues and arrays */ 123 TAILQ_HEAD(, mlx_command) mlx_freecmds; /* command structures available for reuse */ 124 TAILQ_HEAD(, mlx_command) mlx_donecmd; /* commands waiting for completion processing */ 125 struct mlx_command *mlx_busycmd[MLX_NSLOTS]; /* busy commands */ 126 int mlx_busycmds; /* count of busy commands */ 127 struct mlx_sysdrive mlx_sysdrive[MLX_MAXDRIVES]; /* system drives */ 128 struct buf_queue_head mlx_bufq; /* outstanding I/O operations */ 129 int mlx_waitbufs; /* number of bufs awaiting commands */ 130 131 /* controller status */ 132 u_int8_t mlx_fwminor; /* firmware revision */ 133 u_int8_t mlx_fwmajor; 134 int mlx_geom; 135#define MLX_GEOM_128_32 0 /* geoemetry translation modes */ 136#define MLX_GEOM_256_63 1 137 int mlx_state; 138#define MLX_STATE_INTEN (1<<0) /* interrupts have been enabled */ 139#define MLX_STATE_SHUTDOWN (1<<1) /* controller is shut down */ 140#define MLX_STATE_OPEN (1<<2) /* control device is open */ 141#define MLX_STATE_SUSPEND (1<<3) /* controller is suspended */ 142 struct callout_handle mlx_timeout; /* periodic status monitor */ 143 time_t mlx_lastpoll; /* last time_second we polled for status */ 144 u_int16_t mlx_lastevent; /* sequence number of the last event we recorded */ 145 u_int16_t mlx_currevent; /* sequence number last time we looked */ 146 int mlx_polling; /* if > 0, polling operations still running */ 147 int mlx_rebuild; /* if >= 0, drive is being rebuilt */ 148 u_int32_t mlx_rebuildstat;/* blocks left to rebuild if active */ 149 int mlx_check; /* if >= 0, drive is being checked */ 150 struct mlx_pause mlx_pause; /* pending pause operation details */ 151 152 /* interface-specific accessor functions */ 153 int mlx_iftype; /* interface protocol */ 154#define MLX_IFTYPE_3 3 155#define MLX_IFTYPE_4 4 156#define MLX_IFTYPE_5 5 157 int (* mlx_tryqueue)(struct mlx_softc *sc, struct mlx_command *mc); 158 int (* mlx_findcomplete)(struct mlx_softc *sc, u_int8_t *slot, u_int16_t *status); 159 void (* mlx_intaction)(struct mlx_softc *sc, int action); 160#define MLX_INTACTION_DISABLE 0 161#define MLX_INTACTION_ENABLE 1 162#define MLX_INTACTION_ACKNOWLEDGE 2 163 164}; 165 166/* 167 * Interface between bus connections and driver core. 168 */ 169extern void mlx_free(struct mlx_softc *sc); 170extern int mlx_attach(struct mlx_softc *sc); 171extern void mlx_startup(struct mlx_softc *sc); 172extern void mlx_intr(void *data); 173extern int mlx_detach(device_t dev); 174extern int mlx_shutdown(device_t dev); 175extern int mlx_suspend(device_t dev); 176extern int mlx_resume(device_t dev); 177extern d_open_t mlx_open; 178extern d_close_t mlx_close; 179extern d_ioctl_t mlx_ioctl; 180 181extern devclass_t mlx_devclass; 182 183/* 184 * Mylex System Disk driver 185 */ 186struct mlxd_softc 187{ 188 device_t mlxd_dev; 189 struct mlx_softc *mlxd_controller; 190 struct mlx_sysdrive *mlxd_drive; 191 struct disk mlxd_disk; 192 struct devstat mlxd_stats; 193 struct disklabel mlxd_label; 194 int mlxd_unit; 195 int mlxd_flags; 196#define MLXD_OPEN (1<<0) /* drive is open (can't shut down) */ 197}; 198 199/* 200 * Interface between driver core and disk driver (should be using a bus?) 201 */ 202extern int mlx_submit_buf(struct mlx_softc *sc, struct buf *bp); 203extern int mlx_submit_ioctl(struct mlx_softc *sc, struct mlx_sysdrive *drive, u_long cmd, 204 caddr_t addr, int32_t flag, struct proc *p); 205extern void mlxd_intr(void *data); 206 207/* 208 * Accessor defines for the V3 interface. 209 */ 210#define MLX_V3_MAILBOX 0x00 211#define MLX_V3_STATUS_IDENT 0x0d 212#define MLX_V3_STATUS 0x0e 213#define MLX_V3_IDBR 0x40 214#define MLX_V3_ODBR 0x41 215#define MLX_V3_IER 0x43 216 217#define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_MAILBOX + idx, val) 218#define MLX_V3_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS_IDENT) 219#define MLX_V3_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS) 220#define MLX_V3_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR) 221#define MLX_V3_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR, val) 222#define MLX_V3_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR) 223#define MLX_V3_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR, val) 224#define MLX_V3_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IER, val) 225 226#define MLX_V3_IDB_FULL (1<<0) /* mailbox is full */ 227#define MLX_V3_IDB_SACK (1<<1) /* acknowledge status read */ 228#define MLX_V3_IDB_RESET (1<<3) /* request soft reset */ 229 230#define MLX_V3_ODB_SAVAIL (1<<0) /* status is available */ 231 232/* 233 * Inlines to build various command structures 234 */ 235static __inline void 236mlx_make_type1(struct mlx_command *mc, 237 u_int8_t code, 238 u_int16_t f1, 239 u_int32_t f2, 240 u_int8_t f3, 241 u_int32_t f4, 242 u_int8_t f5) 243{ 244 mc->mc_mailbox[0x0] = code; 245 mc->mc_mailbox[0x2] = f1 & 0xff; 246 mc->mc_mailbox[0x3] = (((f2 >> 24) & 0x3) << 6) | ((f1 >> 8) & 0x3f); 247 mc->mc_mailbox[0x4] = f2 & 0xff; 248 mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff; 249 mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff; 250 mc->mc_mailbox[0x7] = f3; 251 mc->mc_mailbox[0x8] = f4 & 0xff; 252 mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff; 253 mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff; 254 mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff; 255 mc->mc_mailbox[0xc] = f5; 256} 257 258static __inline void 259mlx_make_type2(struct mlx_command *mc, 260 u_int8_t code, 261 u_int8_t f1, 262 u_int8_t f2, 263 u_int8_t f3, 264 u_int8_t f4, 265 u_int8_t f5, 266 u_int8_t f6, 267 u_int32_t f7, 268 u_int8_t f8) 269{ 270 mc->mc_mailbox[0x0] = code; 271 mc->mc_mailbox[0x2] = f1; 272 mc->mc_mailbox[0x3] = f2; 273 mc->mc_mailbox[0x4] = f3; 274 mc->mc_mailbox[0x5] = f4; 275 mc->mc_mailbox[0x6] = f5; 276 mc->mc_mailbox[0x7] = f6; 277 mc->mc_mailbox[0x8] = f7 & 0xff; 278 mc->mc_mailbox[0x9] = (f7 >> 8) & 0xff; 279 mc->mc_mailbox[0xa] = (f7 >> 16) & 0xff; 280 mc->mc_mailbox[0xb] = (f7 >> 24) & 0xff; 281 mc->mc_mailbox[0xc] = f8; 282} 283 284static __inline void 285mlx_make_type3(struct mlx_command *mc, 286 u_int8_t code, 287 u_int8_t f1, 288 u_int8_t f2, 289 u_int16_t f3, 290 u_int8_t f4, 291 u_int8_t f5, 292 u_int32_t f6, 293 u_int8_t f7) 294{ 295 mc->mc_mailbox[0x0] = code; 296 mc->mc_mailbox[0x2] = f1; 297 mc->mc_mailbox[0x3] = f2; 298 mc->mc_mailbox[0x4] = f3 & 0xff; 299 mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff; 300 mc->mc_mailbox[0x6] = f4; 301 mc->mc_mailbox[0x7] = f5; 302 mc->mc_mailbox[0x8] = f6 & 0xff; 303 mc->mc_mailbox[0x9] = (f6 >> 8) & 0xff; 304 mc->mc_mailbox[0xa] = (f6 >> 16) & 0xff; 305 mc->mc_mailbox[0xb] = (f6 >> 24) & 0xff; 306 mc->mc_mailbox[0xc] = f7; 307} 308 309static __inline void 310mlx_make_type4(struct mlx_command *mc, 311 u_int8_t code, 312 u_int16_t f1, 313 u_int32_t f2, 314 u_int32_t f3, 315 u_int8_t f4) 316{ 317 mc->mc_mailbox[0x0] = code; 318 mc->mc_mailbox[0x2] = f1 & 0xff; 319 mc->mc_mailbox[0x3] = (f1 >> 8) & 0xff; 320 mc->mc_mailbox[0x4] = f2 & 0xff; 321 mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff; 322 mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff; 323 mc->mc_mailbox[0x7] = (f2 >> 24) & 0xff; 324 mc->mc_mailbox[0x8] = f3 & 0xff; 325 mc->mc_mailbox[0x9] = (f3 >> 8) & 0xff; 326 mc->mc_mailbox[0xa] = (f3 >> 16) & 0xff; 327 mc->mc_mailbox[0xb] = (f3 >> 24) & 0xff; 328 mc->mc_mailbox[0xc] = f4; 329} 330 331static __inline void 332mlx_make_type5(struct mlx_command *mc, 333 u_int8_t code, 334 u_int8_t f1, 335 u_int8_t f2, 336 u_int32_t f3, 337 u_int32_t f4, 338 u_int8_t f5) 339{ 340 mc->mc_mailbox[0x0] = code; 341 mc->mc_mailbox[0x2] = f1; 342 mc->mc_mailbox[0x3] = f2; 343 mc->mc_mailbox[0x4] = f3 & 0xff; 344 mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff; 345 mc->mc_mailbox[0x6] = (f3 >> 16) & 0xff; 346 mc->mc_mailbox[0x7] = (f3 >> 24) & 0xff; 347 mc->mc_mailbox[0x8] = f4 & 0xff; 348 mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff; 349 mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff; 350 mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff; 351 mc->mc_mailbox[0xc] = f5; 352} 353 354