rdcphyreg.h revision 216828
1216828Syongari/*- 2216828Syongari * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 3216828Syongari * All rights reserved. 4216828Syongari * 5216828Syongari * Redistribution and use in source and binary forms, with or without 6216828Syongari * modification, are permitted provided that the following conditions 7216828Syongari * are met: 8216828Syongari * 1. Redistributions of source code must retain the above copyright 9216828Syongari * notice unmodified, this list of conditions, and the following 10216828Syongari * disclaimer. 11216828Syongari * 2. Redistributions in binary form must reproduce the above copyright 12216828Syongari * notice, this list of conditions and the following disclaimer in the 13216828Syongari * documentation and/or other materials provided with the distribution. 14216828Syongari * 15216828Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16216828Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17216828Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18216828Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19216828Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20216828Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21216828Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22216828Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23216828Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24216828Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25216828Syongari * SUCH DAMAGE. 26216828Syongari * 27216828Syongari * $FreeBSD: head/sys/dev/mii/rdcphyreg.h 216828 2010-12-30 23:50:25Z yongari $ 28216828Syongari */ 29216828Syongari 30216828Syongari#ifndef _DEV_MII_RDCPHYREG_H_ 31216828Syongari#define _DEV_MII_RDCPHYREG_H_ 32216828Syongari 33216828Syongari#define MII_RDCPHY_DEBUG 0x11 34216828Syongari#define DEBUG_JABBER_DIS 0x0040 35216828Syongari#define DEBUG_LOOP_BACK_10MBPS 0x0400 36216828Syongari 37216828Syongari#define MII_RDCPHY_CTRL 0x14 38216828Syongari#define CTRL_SQE_ENB 0x0100 39216828Syongari#define CTRL_NEG_POLARITY 0x0400 40216828Syongari#define CTRL_AUTO_POLARITY 0x0800 41216828Syongari#define CTRL_MDIXSEL_RX 0x2000 42216828Syongari#define CTRL_MDIXSEL_TX 0x4000 43216828Syongari#define CTRL_AUTO_MDIX_DIS 0x8000 44216828Syongari 45216828Syongari#define MII_RDCPHY_CTRL2 0x15 46216828Syongari#define CTRL2_LED_DUPLEX 0x0000 47216828Syongari#define CTRL2_LED_DUPLEX_COL 0x0008 48216828Syongari#define CTRL2_LED_ACT 0x0010 49216828Syongari#define CTRL2_LED_SPEED_ACT 0x0018 50216828Syongari#define CTRL2_LED_BLK_100MBPS_DIS 0x0020 51216828Syongari#define CTRL2_LED_BLK_10MBPS_DIS 0x0040 52216828Syongari#define CTRL2_LED_BLK_LINK_ACT_DIS 0x0080 53216828Syongari#define CTRL2_SDT_THRESH_MASK 0x3E00 54216828Syongari#define CTRL2_TIMING_ERR_SEL 0x4000 55216828Syongari#define CTRL2_LED_BLK_80MS 0x8000 56216828Syongari#define CTRL2_LED_BLK_160MS 0x0000 57216828Syongari#define CTRL2_LED_MASK 0x0018 58216828Syongari 59216828Syongari#define MII_RDCPHY_STATUS 0x16 60216828Syongari#define STATUS_AUTO_MDIX_RX 0x0200 61216828Syongari#define STATUS_AUTO_MDIX_TX 0x0400 62216828Syongari#define STATUS_NEG_POLARITY 0x0800 63216828Syongari#define STATUS_FULL_DUPLEX 0x1000 64216828Syongari#define STATUS_SPEED_10 0x0000 65216828Syongari#define STATUS_SPEED_100 0x2000 66216828Syongari#define STATUS_SPEED_MASK 0x6000 67216828Syongari#define STATUS_LINK_UP 0x8000 68216828Syongari 69216828Syongari/* Analog test register 2 */ 70216828Syongari#define MII_RDCPHY_TEST2 0x1A 71216828Syongari#define TEST2_PWR_DOWN 0x0200 72216828Syongari 73216828Syongari#endif /* _DEV_MII_RDCPHYREG_H_ */ 74