1175702Smarius/* $NetBSD: nsphyterreg.h,v 1.4 2005/12/11 12:22:42 christos Exp $ */ 2175702Smarius 3175702Smarius/*- 4175702Smarius * Copyright (c) 1999, 2001 The NetBSD Foundation, Inc. 5175702Smarius * All rights reserved. 6175702Smarius * 7175702Smarius * This code is derived from software contributed to The NetBSD Foundation 8175702Smarius * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9175702Smarius * NASA Ames Research Center. 10175702Smarius * 11175702Smarius * Redistribution and use in source and binary forms, with or without 12175702Smarius * modification, are permitted provided that the following conditions 13175702Smarius * are met: 14175702Smarius * 1. Redistributions of source code must retain the above copyright 15175702Smarius * notice, this list of conditions and the following disclaimer. 16175702Smarius * 2. Redistributions in binary form must reproduce the above copyright 17175702Smarius * notice, this list of conditions and the following disclaimer in the 18175702Smarius * documentation and/or other materials provided with the distribution. 19175702Smarius * 20175702Smarius * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21175702Smarius * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22175702Smarius * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23175702Smarius * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24175702Smarius * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25175702Smarius * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26175702Smarius * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27175702Smarius * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28175702Smarius * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29175702Smarius * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30175702Smarius * POSSIBILITY OF SUCH DAMAGE. 31175702Smarius * 32175702Smarius * $FreeBSD: releng/10.2/sys/dev/mii/nsphyterreg.h 204646 2010-03-03 17:55:51Z joel $ 33175702Smarius */ 34175702Smarius 35175702Smarius#ifndef _DEV_MII_NSPHYTERREG_H_ 36175702Smarius#define _DEV_MII_NSPHYTERREG_H_ 37175702Smarius 38175702Smarius/* 39175702Smarius * DP83843 registers; We also have the MacPHYTER (DP83815) internal 40175702Smarius * PHY register definitions here, since the two are, for our purposes, 41175702Smarius * compatible. 42175702Smarius */ 43175702Smarius 44175702Smarius#define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */ 45175702Smarius#define PHYSTS_REL 0x8000 /* receive error latch */ 46175702Smarius#define PHYSTS_CIML 0x4000 /* CIM latch */ 47175702Smarius#define PHYSTS_FCSL 0x2000 /* false carrier sense latch */ 48175702Smarius#define PHYSTS_DEVRDY 0x0800 /* device ready */ 49175702Smarius#define PHYSTS_PGRX 0x0400 /* page received */ 50175702Smarius#define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */ 51175702Smarius#define PHYSTS_MIIINTR 0x0100 /* MII interrupt */ 52175702Smarius#define PHYSTS_REMFAULT 0x0080 /* remote fault */ 53175702Smarius#define PHYSTS_JABBER 0x0040 /* jabber detect */ 54175702Smarius#define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */ 55175702Smarius#define PHYSTS_RESETSTAT 0x0010 /* reset status */ 56175702Smarius#define PHYSTS_LOOPBACK 0x0008 /* loopback status */ 57175702Smarius#define PHYSTS_DUPLEX 0x0004 /* full duplex */ 58175702Smarius#define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */ 59175702Smarius#define PHYSTS_LINK 0x0001 /* link up */ 60175702Smarius /* Below are the MacPHYTER bits that are different. */ 61175702Smarius#define PHYSTS_MP_REL 0x2000 /* receive error latch */ 62175702Smarius#define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */ 63175702Smarius#define PHYSTS_MP_FCSL 0x0800 /* false carrier sense latch */ 64175702Smarius#define PHYSTS_MP_SIGNAL 0x0400 /* signal detect */ 65175702Smarius#define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */ 66175702Smarius#define PHYSTS_MP_PGRX 0x0100 /* page received */ 67175702Smarius#define PHYSTS_MP_MIIINTR 0x0080 /* MII interrupt */ 68175702Smarius#define PHYSTS_MP_REMFAULT 0x0040 /* remote fault */ 69175702Smarius#define PHYSTS_MP_JABBER 0x0020 /* jabber detect */ 70175702Smarius#define PHYSTS_MP_NWAYCOMP 0x0010 /* NWAY complete */ 71175702Smarius 72175702Smarius 73175702Smarius#define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific 74175702Smarius control */ 75175702Smarius 76175702Smarius#define MIPSCR_INTEN 0x0002 /* interrupt enable */ 77175702Smarius#define MIPSCR_TINT 0x0001 /* test interrupt */ 78175702Smarius 79175702Smarius 80175702Smarius#define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic 81175702Smarius status */ 82175702Smarius#define MIPGSR_MINT 0x8000 /* MII interrupt pending */ 83175702Smarius /* The bits below are MacPHYTER only. */ 84175702Smarius#define MIPGSR_MSK_LINK 0x4000 /* mask link status event */ 85175702Smarius#define MIPGSR_MSK_JAB 0x2000 /* mask jabber event */ 86175702Smarius#define MIPGSR_MSK_RF 0x1000 /* mask remote fault event */ 87175702Smarius#define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */ 88175702Smarius#define MIPGSR_MSK_FHF 0x0400 /* mask false carrier half full event */ 89175702Smarius#define MIPGSR_MSK_RHF 0x0200 /* mask RX error half full event */ 90175702Smarius 91175702Smarius#define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */ 92175702Smarius 93175702Smarius#define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */ 94175702Smarius 95175702Smarius#define MII_NSPHYTER_RECR 0x15 /* Receive error counter */ 96175702Smarius 97175702Smarius 98175702Smarius#define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */ 99175702Smarius#define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */ 100175702Smarius#define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */ 101175702Smarius#define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */ 102175702Smarius#define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */ 103175702Smarius#define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */ 104175702Smarius#define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */ 105175702Smarius#define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */ 106175702Smarius#define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */ 107175702Smarius#define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */ 108175702Smarius#define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */ 109175702Smarius#define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */ 110175702Smarius#define PCSR_CODE_ERR 0x0008 /* code errors */ 111175702Smarius#define PCSR_PME_ERR 0x0004 /* premature end errors */ 112175702Smarius#define PCSR_LINK_ERR 0x0002 /* link errors */ 113175702Smarius#define PCSR_PKT_ERR 0x0001 /* packet errors */ 114175702Smarius /* Below are the MacPHYTER bits that are different. */ 115175702Smarius#define PCSR_MP_BYP_4B5B 0x1000 /* bypass encoder */ 116175702Smarius#define PCSR_MP_FREE_CLK 0x0800 /* free funning RX clock */ 117175702Smarius#define PCSR_MP_TQ_EN 0x0400 /* enable True Quiet mode */ 118175702Smarius#define PCSR_MP_SD_FORCE_B 0x0200 /* force signal detection */ 119175702Smarius#define PCSR_MP_SD_OPTION 0x0100 /* enhanced signal detection alg. */ 120175702Smarius#define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */ 121175702Smarius 122175702Smarius 123175702Smarius /* The bits below are not on MacPHYTER. */ 124175702Smarius#define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */ 125175702Smarius#define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */ 126175702Smarius#define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */ 127175702Smarius#define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */ 128175702Smarius#define LBR_BP_RX 0x0800 /* bypass receive function */ 129175702Smarius#define LBR_BP_TX 0x0400 /* bypass transmit function */ 130175702Smarius#define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */ 131175702Smarius#define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */ 132175702Smarius#define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */ 133175702Smarius 134175702Smarius 135175702Smarius /* The bits below are not on MacPHYTER. */ 136175702Smarius#define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */ 137175702Smarius#define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */ 138175702Smarius#define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */ 139175702Smarius#define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */ 140175702Smarius#define BTSCR_POL_DS 0x0400 /* polarity detection and correction 141175702Smarius disable */ 142175702Smarius#define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */ 143175702Smarius#define BTSCR_LP_DS 0x0100 /* link pulse disable */ 144175702Smarius#define BTSCR_HB_DS 0x0080 /* heartbeat disabled */ 145175702Smarius#define BTSCR_LS_SEL 0x0040 /* low squelch select */ 146175702Smarius#define BTSCR_AUI_SEL 0x0020 /* AUI select */ 147175702Smarius#define BTSCR_JAB_DS 0x0010 /* jabber disable */ 148175702Smarius#define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */ 149175702Smarius#define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */ 150175702Smarius 151175702Smarius 152175702Smarius#define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */ 153175702Smarius#define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */ 154175702Smarius#define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */ 155175702Smarius#define PHYCTRL_REPEATER 0x0200 /* repeater mode */ 156175702Smarius#define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */ 157175702Smarius#define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */ 158175702Smarius#define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */ 159175702Smarius#define PHYCTRL_PHYADDR 0x001f /* PHY address */ 160175702Smarius /* Below are the MacPHYTER bits that are different. */ 161175702Smarius#define PHYCRTL_MP_PSR_15 0x0800 /* BIST sequence select */ 162175702Smarius#define PHYCTRL_MP_BIST_STAT 0x0400 /* BIST passed */ 163175702Smarius#define PHYCTRL_MP_BIST_START 0x0200 /* start BIST */ 164175702Smarius#define PHYCTRL_MP_BP_STRETCH 0x0100 /* bypass LED stretching */ 165175702Smarius#define PHYCTRL_MP_PAUSE_STS 0x0080 /* pause status */ 166175702Smarius 167175702Smarius 168175702Smarius /* The bits below are MacPHYTER only. */ 169175702Smarius#define MII_MACPHYTER_TBTCTL 0x1a /* 10baseT Control */ 170175702Smarius#define TBTCTL_LOOPBACK_10_DIS 0x0100 /* loopback 10Mb/s disable */ 171175702Smarius#define TBTCTL_LP_DIS 0x0080 /* link pulse disable */ 172175702Smarius#define TBTCTL_FORCE_LINK_10 0x0040 /* force 10Mb/s link good */ 173175702Smarius#define TBTCTL_FORCE_POL_COR 0x0020 /* force polarity correction */ 174175702Smarius#define TBTCTL_INV_POLARITY 0x0010 /* inverted polarity */ 175175702Smarius#define TBTCTL_AUTOPOL_DIS 0x0008 /* auto-polarity disable */ 176175702Smarius#define TBTCTL_HEARTBEAT_DIS 0x0002 /* heartbeat disable */ 177175702Smarius#define TBTCTL_JABBER_DIS 0x0001 /* jabber disable */ 178175702Smarius 179175702Smarius#endif /* _DEV_MII_NSPHYTERREG_H_ */ 180