ciphy.c revision 183489
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/mii/ciphy.c 183489 2008-09-30 07:20:26Z yongari $"); 35 36/* 37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/bus.h> 46 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_media.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include "miidevs.h" 54 55#include <dev/mii/ciphyreg.h> 56 57#include "miibus_if.h" 58 59#include <machine/bus.h> 60/* 61#include <dev/vge/if_vgereg.h> 62*/ 63static int ciphy_probe(device_t); 64static int ciphy_attach(device_t); 65 66static device_method_t ciphy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, ciphy_probe), 69 DEVMETHOD(device_attach, ciphy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73}; 74 75static devclass_t ciphy_devclass; 76 77static driver_t ciphy_driver = { 78 "ciphy", 79 ciphy_methods, 80 sizeof(struct mii_softc) 81}; 82 83DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 84 85static int ciphy_service(struct mii_softc *, struct mii_data *, int); 86static void ciphy_status(struct mii_softc *); 87static void ciphy_reset(struct mii_softc *); 88static void ciphy_fixup(struct mii_softc *); 89 90static const struct mii_phydesc ciphys[] = { 91 MII_PHY_DESC(CICADA, CS8201), 92 MII_PHY_DESC(CICADA, CS8201A), 93 MII_PHY_DESC(CICADA, CS8201B), 94 MII_PHY_DESC(CICADA, CS8204), 95 MII_PHY_DESC(CICADA, CS8244), 96 MII_PHY_DESC(VITESSE, VSC8601), 97 MII_PHY_END 98}; 99 100static int 101ciphy_probe(device_t dev) 102{ 103 104 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT)); 105} 106 107static int 108ciphy_attach(device_t dev) 109{ 110 struct mii_softc *sc; 111 struct mii_attach_args *ma; 112 struct mii_data *mii; 113 114 sc = device_get_softc(dev); 115 ma = device_get_ivars(dev); 116 sc->mii_dev = device_get_parent(dev); 117 mii = device_get_softc(sc->mii_dev); 118 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 119 120 sc->mii_inst = mii->mii_instance; 121 sc->mii_phy = ma->mii_phyno; 122 sc->mii_service = ciphy_service; 123 sc->mii_pdata = mii; 124 125 sc->mii_flags |= MIIF_NOISOLATE; 126 mii->mii_instance++; 127 128 ciphy_reset(sc); 129 130 sc->mii_capabilities = 131 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 132 if (sc->mii_capabilities & BMSR_EXTSTAT) 133 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 134 device_printf(dev, " "); 135 mii_phy_add_media(sc); 136 printf("\n"); 137 138 MIIBUS_MEDIAINIT(sc->mii_dev); 139 return (0); 140} 141 142static int 143ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 144{ 145 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 146 int reg, speed, gig; 147 148 switch (cmd) { 149 case MII_POLLSTAT: 150 /* 151 * If we're not polling our PHY instance, just return. 152 */ 153 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 154 return (0); 155 break; 156 157 case MII_MEDIACHG: 158 /* 159 * If the media indicates a different PHY instance, 160 * isolate ourselves. 161 */ 162 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 163 reg = PHY_READ(sc, MII_BMCR); 164 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 165 return (0); 166 } 167 168 /* 169 * If the interface is not up, don't do anything. 170 */ 171 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 172 break; 173 174 ciphy_fixup(sc); /* XXX hardware bug work-around */ 175 176 switch (IFM_SUBTYPE(ife->ifm_media)) { 177 case IFM_AUTO: 178#ifdef foo 179 /* 180 * If we're already in auto mode, just return. 181 */ 182 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 183 return (0); 184#endif 185 (void) mii_phy_auto(sc); 186 break; 187 case IFM_1000_T: 188 speed = CIPHY_S1000; 189 goto setit; 190 case IFM_100_TX: 191 speed = CIPHY_S100; 192 goto setit; 193 case IFM_10_T: 194 speed = CIPHY_S10; 195setit: 196 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 197 speed |= CIPHY_BMCR_FDX; 198 gig = CIPHY_1000CTL_AFD; 199 } else { 200 gig = CIPHY_1000CTL_AHD; 201 } 202 203 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); 204 PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 205 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 206 207 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 208 break; 209 210 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 211 PHY_WRITE(sc, CIPHY_MII_BMCR, 212 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); 213 214 /* 215 * When setting the link manually, one side must 216 * be the master and the other the slave. However 217 * ifmedia doesn't give us a good way to specify 218 * this, so we fake it by using one of the LINK 219 * flags. If LINK0 is set, we program the PHY to 220 * be a master, otherwise it's a slave. 221 */ 222 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 223 PHY_WRITE(sc, CIPHY_MII_1000CTL, 224 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); 225 } else { 226 PHY_WRITE(sc, CIPHY_MII_1000CTL, 227 gig|CIPHY_1000CTL_MSE); 228 } 229 break; 230 case IFM_NONE: 231 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 232 break; 233 case IFM_100_T4: 234 default: 235 return (EINVAL); 236 } 237 break; 238 239 case MII_TICK: 240 /* 241 * If we're not currently selected, just return. 242 */ 243 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 244 return (0); 245 246 /* 247 * Is the interface even up? 248 */ 249 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 250 return (0); 251 252 /* 253 * Only used for autonegotiation. 254 */ 255 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 256 break; 257 258 /* 259 * Check to see if we have link. If we do, we don't 260 * need to restart the autonegotiation process. Read 261 * the BMSR twice in case it's latched. 262 */ 263 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 264 if (reg & BMSR_LINK) 265 break; 266 267 /* Announce link loss right after it happens. */ 268 if (++sc->mii_ticks == 0) 269 break; 270 /* 271 * Only retry autonegotiation every mii_anegticks seconds. 272 */ 273 if (sc->mii_ticks <= sc->mii_anegticks) 274 break; 275 276 sc->mii_ticks = 0; 277 mii_phy_auto(sc); 278 return (0); 279 } 280 281 /* Update the media status. */ 282 ciphy_status(sc); 283 284 /* 285 * Callback if something changed. Note that we need to poke 286 * apply fixups for certain PHY revs. 287 */ 288 if (sc->mii_media_active != mii->mii_media_active || 289 sc->mii_media_status != mii->mii_media_status || 290 cmd == MII_MEDIACHG) { 291 ciphy_fixup(sc); 292 } 293 mii_phy_update(sc, cmd); 294 return (0); 295} 296 297static void 298ciphy_status(struct mii_softc *sc) 299{ 300 struct mii_data *mii = sc->mii_pdata; 301 int bmsr, bmcr; 302 303 mii->mii_media_status = IFM_AVALID; 304 mii->mii_media_active = IFM_ETHER; 305 306 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 307 308 if (bmsr & BMSR_LINK) 309 mii->mii_media_status |= IFM_ACTIVE; 310 311 bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 312 313 if (bmcr & CIPHY_BMCR_LOOP) 314 mii->mii_media_active |= IFM_LOOP; 315 316 if (bmcr & CIPHY_BMCR_AUTOEN) { 317 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 318 /* Erg, still trying, I guess... */ 319 mii->mii_media_active |= IFM_NONE; 320 return; 321 } 322 } 323 324 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 325 switch (bmsr & CIPHY_AUXCSR_SPEED) { 326 case CIPHY_SPEED10: 327 mii->mii_media_active |= IFM_10_T; 328 break; 329 case CIPHY_SPEED100: 330 mii->mii_media_active |= IFM_100_TX; 331 break; 332 case CIPHY_SPEED1000: 333 mii->mii_media_active |= IFM_1000_T; 334 break; 335 default: 336 device_printf(sc->mii_dev, "unknown PHY speed %x\n", 337 bmsr & CIPHY_AUXCSR_SPEED); 338 break; 339 } 340 341 if (bmsr & CIPHY_AUXCSR_FDX) 342 mii->mii_media_active |= IFM_FDX; 343} 344 345static void 346ciphy_reset(struct mii_softc *sc) 347{ 348 349 mii_phy_reset(sc); 350 DELAY(1000); 351} 352 353#define PHY_SETBIT(x, y, z) \ 354 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 355#define PHY_CLRBIT(x, y, z) \ 356 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 357 358static void 359ciphy_fixup(struct mii_softc *sc) 360{ 361 uint16_t model; 362 uint16_t status, speed; 363 uint16_t val; 364 365 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 366 status = PHY_READ(sc, CIPHY_MII_AUXCSR); 367 speed = status & CIPHY_AUXCSR_SPEED; 368 369 if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), 370 "nfe") == 0) { 371 /* need to set for 2.5V RGMII for NVIDIA adapters */ 372 val = PHY_READ(sc, CIPHY_MII_ECTL1); 373 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); 374 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); 375 PHY_WRITE(sc, CIPHY_MII_ECTL1, val); 376 /* From Linux. */ 377 val = PHY_READ(sc, CIPHY_MII_AUXCSR); 378 val |= CIPHY_AUXCSR_MDPPS; 379 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); 380 val = PHY_READ(sc, CIPHY_MII_10BTCSR); 381 val |= CIPHY_10BTCSR_ECHO; 382 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); 383 } 384 385 switch (model) { 386 case MII_MODEL_CICADA_CS8204: 387 case MII_MODEL_CICADA_CS8201: 388 389 /* Turn off "aux mode" (whatever that means) */ 390 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 391 392 /* 393 * Work around speed polling bug in VT3119/VT3216 394 * when using MII in full duplex mode. 395 */ 396 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 397 (status & CIPHY_AUXCSR_FDX)) { 398 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 399 } else { 400 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 401 } 402 403 /* Enable link/activity LED blink. */ 404 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 405 406 break; 407 408 case MII_MODEL_CICADA_CS8201A: 409 case MII_MODEL_CICADA_CS8201B: 410 411 /* 412 * Work around speed polling bug in VT3119/VT3216 413 * when using MII in full duplex mode. 414 */ 415 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 416 (status & CIPHY_AUXCSR_FDX)) { 417 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 418 } else { 419 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 420 } 421 422 break; 423 case MII_MODEL_CICADA_CS8244: 424 case MII_MODEL_VITESSE_VSC8601: 425 break; 426 default: 427 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", 428 model); 429 break; 430 } 431} 432