ciphy.c revision 176773
1139749Simp/*- 2135048Swpaul * Copyright (c) 2004 3135048Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4135048Swpaul * 5135048Swpaul * Redistribution and use in source and binary forms, with or without 6135048Swpaul * modification, are permitted provided that the following conditions 7135048Swpaul * are met: 8135048Swpaul * 1. Redistributions of source code must retain the above copyright 9135048Swpaul * notice, this list of conditions and the following disclaimer. 10135048Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11135048Swpaul * notice, this list of conditions and the following disclaimer in the 12135048Swpaul * documentation and/or other materials provided with the distribution. 13135048Swpaul * 3. All advertising materials mentioning features or use of this software 14135048Swpaul * must display the following acknowledgement: 15135048Swpaul * This product includes software developed by Bill Paul. 16135048Swpaul * 4. Neither the name of the author nor the names of any co-contributors 17135048Swpaul * may be used to endorse or promote products derived from this software 18135048Swpaul * without specific prior written permission. 19135048Swpaul * 20135048Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21135048Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22135048Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23135048Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24135048Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25135048Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26135048Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27135048Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28135048Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29135048Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30135048Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 31135048Swpaul */ 32135048Swpaul 33135048Swpaul#include <sys/cdefs.h> 34135048Swpaul__FBSDID("$FreeBSD: head/sys/dev/mii/ciphy.c 176773 2008-03-03 18:44:33Z raj $"); 35135048Swpaul 36135048Swpaul/* 37176773Sraj * Driver for the Cicada CS8201/CS8204 10/100/1000 copper PHY. 38135048Swpaul */ 39135048Swpaul 40135048Swpaul#include <sys/param.h> 41135048Swpaul#include <sys/systm.h> 42135048Swpaul#include <sys/kernel.h> 43135048Swpaul#include <sys/module.h> 44135048Swpaul#include <sys/socket.h> 45135048Swpaul#include <sys/bus.h> 46135048Swpaul 47135048Swpaul#include <net/if.h> 48135048Swpaul#include <net/if_arp.h> 49135048Swpaul#include <net/if_media.h> 50135048Swpaul 51135048Swpaul#include <dev/mii/mii.h> 52135048Swpaul#include <dev/mii/miivar.h> 53135048Swpaul#include "miidevs.h" 54135048Swpaul 55135048Swpaul#include <dev/mii/ciphyreg.h> 56135048Swpaul 57135048Swpaul#include "miibus_if.h" 58135048Swpaul 59135048Swpaul#include <machine/bus.h> 60135048Swpaul/* 61135048Swpaul#include <dev/vge/if_vgereg.h> 62135048Swpaul*/ 63135048Swpaulstatic int ciphy_probe(device_t); 64135048Swpaulstatic int ciphy_attach(device_t); 65135048Swpaul 66135048Swpaulstatic device_method_t ciphy_methods[] = { 67135048Swpaul /* device interface */ 68135048Swpaul DEVMETHOD(device_probe, ciphy_probe), 69135048Swpaul DEVMETHOD(device_attach, ciphy_attach), 70135048Swpaul DEVMETHOD(device_detach, mii_phy_detach), 71135048Swpaul DEVMETHOD(device_shutdown, bus_generic_shutdown), 72135048Swpaul { 0, 0 } 73135048Swpaul}; 74135048Swpaul 75135048Swpaulstatic devclass_t ciphy_devclass; 76135048Swpaul 77135048Swpaulstatic driver_t ciphy_driver = { 78135048Swpaul "ciphy", 79135048Swpaul ciphy_methods, 80135048Swpaul sizeof(struct mii_softc) 81135048Swpaul}; 82135048Swpaul 83135048SwpaulDRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 84135048Swpaul 85135048Swpaulstatic int ciphy_service(struct mii_softc *, struct mii_data *, int); 86135048Swpaulstatic void ciphy_status(struct mii_softc *); 87135048Swpaulstatic void ciphy_reset(struct mii_softc *); 88135048Swpaulstatic void ciphy_fixup(struct mii_softc *); 89135048Swpaul 90164827Smariusstatic const struct mii_phydesc ciphys[] = { 91164827Smarius MII_PHY_DESC(CICADA, CS8201), 92164827Smarius MII_PHY_DESC(CICADA, CS8201A), 93164827Smarius MII_PHY_DESC(CICADA, CS8201B), 94176773Sraj MII_PHY_DESC(CICADA, CS8204), 95170365Syongari MII_PHY_DESC(VITESSE, VSC8601), 96164827Smarius MII_PHY_END 97164827Smarius}; 98164827Smarius 99135048Swpaulstatic int 100150763Simpciphy_probe(device_t dev) 101135048Swpaul{ 102135048Swpaul 103164827Smarius return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT)); 104135048Swpaul} 105135048Swpaul 106135048Swpaulstatic int 107150763Simpciphy_attach(device_t dev) 108135048Swpaul{ 109135048Swpaul struct mii_softc *sc; 110135048Swpaul struct mii_attach_args *ma; 111135048Swpaul struct mii_data *mii; 112135048Swpaul 113135048Swpaul sc = device_get_softc(dev); 114135048Swpaul ma = device_get_ivars(dev); 115135048Swpaul sc->mii_dev = device_get_parent(dev); 116135048Swpaul mii = device_get_softc(sc->mii_dev); 117135048Swpaul LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 118135048Swpaul 119135048Swpaul sc->mii_inst = mii->mii_instance; 120135048Swpaul sc->mii_phy = ma->mii_phyno; 121135048Swpaul sc->mii_service = ciphy_service; 122135048Swpaul sc->mii_pdata = mii; 123135048Swpaul 124135048Swpaul sc->mii_flags |= MIIF_NOISOLATE; 125135048Swpaul mii->mii_instance++; 126135048Swpaul 127135048Swpaul ciphy_reset(sc); 128135048Swpaul 129135048Swpaul sc->mii_capabilities = 130135048Swpaul PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 131135048Swpaul if (sc->mii_capabilities & BMSR_EXTSTAT) 132135048Swpaul sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 133135048Swpaul device_printf(dev, " "); 134135048Swpaul mii_phy_add_media(sc); 135135048Swpaul printf("\n"); 136135048Swpaul 137135048Swpaul MIIBUS_MEDIAINIT(sc->mii_dev); 138164705Smarius return (0); 139135048Swpaul} 140135048Swpaul 141135048Swpaulstatic int 142150763Simpciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 143135048Swpaul{ 144135048Swpaul struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 145135048Swpaul int reg, speed, gig; 146135048Swpaul 147135048Swpaul switch (cmd) { 148135048Swpaul case MII_POLLSTAT: 149135048Swpaul /* 150135048Swpaul * If we're not polling our PHY instance, just return. 151135048Swpaul */ 152135048Swpaul if (IFM_INST(ife->ifm_media) != sc->mii_inst) 153135048Swpaul return (0); 154135048Swpaul break; 155135048Swpaul 156135048Swpaul case MII_MEDIACHG: 157135048Swpaul /* 158135048Swpaul * If the media indicates a different PHY instance, 159135048Swpaul * isolate ourselves. 160135048Swpaul */ 161135048Swpaul if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 162135048Swpaul reg = PHY_READ(sc, MII_BMCR); 163135048Swpaul PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 164135048Swpaul return (0); 165135048Swpaul } 166135048Swpaul 167135048Swpaul /* 168135048Swpaul * If the interface is not up, don't do anything. 169135048Swpaul */ 170135048Swpaul if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 171135048Swpaul break; 172135048Swpaul 173135048Swpaul ciphy_fixup(sc); /* XXX hardware bug work-around */ 174135048Swpaul 175135048Swpaul switch (IFM_SUBTYPE(ife->ifm_media)) { 176135048Swpaul case IFM_AUTO: 177135048Swpaul#ifdef foo 178135048Swpaul /* 179135048Swpaul * If we're already in auto mode, just return. 180135048Swpaul */ 181135048Swpaul if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 182135048Swpaul return (0); 183135048Swpaul#endif 184135048Swpaul (void) mii_phy_auto(sc); 185135048Swpaul break; 186135048Swpaul case IFM_1000_T: 187135048Swpaul speed = CIPHY_S1000; 188135048Swpaul goto setit; 189135048Swpaul case IFM_100_TX: 190135048Swpaul speed = CIPHY_S100; 191135048Swpaul goto setit; 192135048Swpaul case IFM_10_T: 193135048Swpaul speed = CIPHY_S10; 194135048Swpaulsetit: 195135048Swpaul if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 196135048Swpaul speed |= CIPHY_BMCR_FDX; 197135048Swpaul gig = CIPHY_1000CTL_AFD; 198135048Swpaul } else { 199135048Swpaul gig = CIPHY_1000CTL_AHD; 200135048Swpaul } 201135048Swpaul 202135048Swpaul PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); 203135048Swpaul PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 204135048Swpaul PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 205135048Swpaul 206164705Smarius if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 207135048Swpaul break; 208135048Swpaul 209135048Swpaul PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 210135048Swpaul PHY_WRITE(sc, CIPHY_MII_BMCR, 211135048Swpaul speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); 212135048Swpaul 213135048Swpaul /* 214135048Swpaul * When setting the link manually, one side must 215135048Swpaul * be the master and the other the slave. However 216135048Swpaul * ifmedia doesn't give us a good way to specify 217135048Swpaul * this, so we fake it by using one of the LINK 218135048Swpaul * flags. If LINK0 is set, we program the PHY to 219135048Swpaul * be a master, otherwise it's a slave. 220135048Swpaul */ 221135048Swpaul if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 222135048Swpaul PHY_WRITE(sc, CIPHY_MII_1000CTL, 223135048Swpaul gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); 224135048Swpaul } else { 225135048Swpaul PHY_WRITE(sc, CIPHY_MII_1000CTL, 226135048Swpaul gig|CIPHY_1000CTL_MSE); 227135048Swpaul } 228135048Swpaul break; 229135048Swpaul case IFM_NONE: 230135048Swpaul PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 231135048Swpaul break; 232135048Swpaul case IFM_100_T4: 233135048Swpaul default: 234135048Swpaul return (EINVAL); 235135048Swpaul } 236135048Swpaul break; 237135048Swpaul 238135048Swpaul case MII_TICK: 239135048Swpaul /* 240135048Swpaul * If we're not currently selected, just return. 241135048Swpaul */ 242135048Swpaul if (IFM_INST(ife->ifm_media) != sc->mii_inst) 243135048Swpaul return (0); 244135048Swpaul 245135048Swpaul /* 246135048Swpaul * Is the interface even up? 247135048Swpaul */ 248135048Swpaul if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 249135048Swpaul return (0); 250135048Swpaul 251135048Swpaul /* 252135048Swpaul * Only used for autonegotiation. 253135048Swpaul */ 254135048Swpaul if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 255135048Swpaul break; 256135048Swpaul 257135048Swpaul /* 258135048Swpaul * Check to see if we have link. If we do, we don't 259135048Swpaul * need to restart the autonegotiation process. Read 260135048Swpaul * the BMSR twice in case it's latched. 261135048Swpaul */ 262135048Swpaul reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 263135048Swpaul if (reg & BMSR_LINK) 264135048Swpaul break; 265135048Swpaul 266135048Swpaul /* 267135048Swpaul * Only retry autonegotiation every 5 seconds. 268135048Swpaul */ 269164830Smarius if (++sc->mii_ticks <= MII_ANEGTICKS) 270135048Swpaul break; 271164705Smarius 272135048Swpaul sc->mii_ticks = 0; 273135048Swpaul mii_phy_auto(sc); 274135048Swpaul return (0); 275135048Swpaul } 276135048Swpaul 277135048Swpaul /* Update the media status. */ 278135048Swpaul ciphy_status(sc); 279135048Swpaul 280135048Swpaul /* 281135048Swpaul * Callback if something changed. Note that we need to poke 282135048Swpaul * apply fixups for certain PHY revs. 283135048Swpaul */ 284164705Smarius if (sc->mii_media_active != mii->mii_media_active || 285135048Swpaul sc->mii_media_status != mii->mii_media_status || 286135048Swpaul cmd == MII_MEDIACHG) { 287135048Swpaul ciphy_fixup(sc); 288135048Swpaul } 289135048Swpaul mii_phy_update(sc, cmd); 290135048Swpaul return (0); 291135048Swpaul} 292135048Swpaul 293135048Swpaulstatic void 294150763Simpciphy_status(struct mii_softc *sc) 295135048Swpaul{ 296135048Swpaul struct mii_data *mii = sc->mii_pdata; 297135048Swpaul int bmsr, bmcr; 298135048Swpaul 299135048Swpaul mii->mii_media_status = IFM_AVALID; 300135048Swpaul mii->mii_media_active = IFM_ETHER; 301135048Swpaul 302135048Swpaul bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 303135048Swpaul 304135048Swpaul if (bmsr & BMSR_LINK) 305135048Swpaul mii->mii_media_status |= IFM_ACTIVE; 306135048Swpaul 307135048Swpaul bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 308135048Swpaul 309135048Swpaul if (bmcr & CIPHY_BMCR_LOOP) 310135048Swpaul mii->mii_media_active |= IFM_LOOP; 311135048Swpaul 312135048Swpaul if (bmcr & CIPHY_BMCR_AUTOEN) { 313135048Swpaul if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 314135048Swpaul /* Erg, still trying, I guess... */ 315135048Swpaul mii->mii_media_active |= IFM_NONE; 316135048Swpaul return; 317135048Swpaul } 318135048Swpaul } 319135048Swpaul 320135048Swpaul bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 321135048Swpaul switch (bmsr & CIPHY_AUXCSR_SPEED) { 322135048Swpaul case CIPHY_SPEED10: 323135048Swpaul mii->mii_media_active |= IFM_10_T; 324135048Swpaul break; 325135048Swpaul case CIPHY_SPEED100: 326135048Swpaul mii->mii_media_active |= IFM_100_TX; 327135048Swpaul break; 328135048Swpaul case CIPHY_SPEED1000: 329135048Swpaul mii->mii_media_active |= IFM_1000_T; 330135048Swpaul break; 331135048Swpaul default: 332135048Swpaul device_printf(sc->mii_dev, "unknown PHY speed %x\n", 333135048Swpaul bmsr & CIPHY_AUXCSR_SPEED); 334135048Swpaul break; 335135048Swpaul } 336135048Swpaul 337135048Swpaul if (bmsr & CIPHY_AUXCSR_FDX) 338135048Swpaul mii->mii_media_active |= IFM_FDX; 339135048Swpaul} 340135048Swpaul 341135048Swpaulstatic void 342135048Swpaulciphy_reset(struct mii_softc *sc) 343135048Swpaul{ 344164830Smarius 345135048Swpaul mii_phy_reset(sc); 346135048Swpaul DELAY(1000); 347135048Swpaul} 348135048Swpaul 349135048Swpaul#define PHY_SETBIT(x, y, z) \ 350135048Swpaul PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 351135048Swpaul#define PHY_CLRBIT(x, y, z) \ 352135048Swpaul PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 353135048Swpaul 354135048Swpaulstatic void 355135048Swpaulciphy_fixup(struct mii_softc *sc) 356135048Swpaul{ 357135048Swpaul uint16_t model; 358135048Swpaul uint16_t status, speed; 359170365Syongari uint16_t val; 360135048Swpaul 361135048Swpaul model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 362135048Swpaul status = PHY_READ(sc, CIPHY_MII_AUXCSR); 363135048Swpaul speed = status & CIPHY_AUXCSR_SPEED; 364135048Swpaul 365170365Syongari if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), 366170365Syongari "nfe") == 0) { 367170365Syongari /* need to set for 2.5V RGMII for NVIDIA adapters */ 368170365Syongari val = PHY_READ(sc, CIPHY_MII_ECTL1); 369170365Syongari val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); 370170365Syongari val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); 371170365Syongari PHY_WRITE(sc, CIPHY_MII_ECTL1, val); 372170365Syongari /* From Linux. */ 373170365Syongari val = PHY_READ(sc, CIPHY_MII_AUXCSR); 374170365Syongari val |= CIPHY_AUXCSR_MDPPS; 375170365Syongari PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); 376170365Syongari val = PHY_READ(sc, CIPHY_MII_10BTCSR); 377170365Syongari val |= CIPHY_10BTCSR_ECHO; 378170365Syongari PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); 379170365Syongari } 380170365Syongari 381135048Swpaul switch (model) { 382176773Sraj case MII_MODEL_CICADA_CS8204: 383135048Swpaul case MII_MODEL_CICADA_CS8201: 384135048Swpaul 385135048Swpaul /* Turn off "aux mode" (whatever that means) */ 386135048Swpaul PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 387135048Swpaul 388135048Swpaul /* 389135048Swpaul * Work around speed polling bug in VT3119/VT3216 390135048Swpaul * when using MII in full duplex mode. 391135048Swpaul */ 392135048Swpaul if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 393135048Swpaul (status & CIPHY_AUXCSR_FDX)) { 394135048Swpaul PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 395135048Swpaul } else { 396135048Swpaul PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 397135048Swpaul } 398135048Swpaul 399135048Swpaul /* Enable link/activity LED blink. */ 400135048Swpaul PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 401135048Swpaul 402135048Swpaul break; 403135048Swpaul 404135048Swpaul case MII_MODEL_CICADA_CS8201A: 405135048Swpaul case MII_MODEL_CICADA_CS8201B: 406135048Swpaul 407135048Swpaul /* 408135048Swpaul * Work around speed polling bug in VT3119/VT3216 409135048Swpaul * when using MII in full duplex mode. 410135048Swpaul */ 411135048Swpaul if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 412135048Swpaul (status & CIPHY_AUXCSR_FDX)) { 413135048Swpaul PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 414135048Swpaul } else { 415135048Swpaul PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 416135048Swpaul } 417135048Swpaul 418135048Swpaul break; 419170365Syongari case MII_MODEL_VITESSE_VSC8601: 420170365Syongari break; 421135048Swpaul default: 422135048Swpaul device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", 423135048Swpaul model); 424135048Swpaul break; 425135048Swpaul } 426135048Swpaul} 427