ciphy.c revision 150763
1139749Simp/*-
2135048Swpaul * Copyright (c) 2004
3135048Swpaul *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4135048Swpaul *
5135048Swpaul * Redistribution and use in source and binary forms, with or without
6135048Swpaul * modification, are permitted provided that the following conditions
7135048Swpaul * are met:
8135048Swpaul * 1. Redistributions of source code must retain the above copyright
9135048Swpaul *    notice, this list of conditions and the following disclaimer.
10135048Swpaul * 2. Redistributions in binary form must reproduce the above copyright
11135048Swpaul *    notice, this list of conditions and the following disclaimer in the
12135048Swpaul *    documentation and/or other materials provided with the distribution.
13135048Swpaul * 3. All advertising materials mentioning features or use of this software
14135048Swpaul *    must display the following acknowledgement:
15135048Swpaul *	This product includes software developed by Bill Paul.
16135048Swpaul * 4. Neither the name of the author nor the names of any co-contributors
17135048Swpaul *    may be used to endorse or promote products derived from this software
18135048Swpaul *    without specific prior written permission.
19135048Swpaul *
20135048Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21135048Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22135048Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23135048Swpaul * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24135048Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25135048Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26135048Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27135048Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28135048Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29135048Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30135048Swpaul * THE POSSIBILITY OF SUCH DAMAGE.
31135048Swpaul *
32135048Swpaul * $FreeBSD: head/sys/dev/mii/ciphy.c 150763 2005-09-30 19:39:27Z imp $
33135048Swpaul */
34135048Swpaul
35135048Swpaul#include <sys/cdefs.h>
36135048Swpaul__FBSDID("$FreeBSD: head/sys/dev/mii/ciphy.c 150763 2005-09-30 19:39:27Z imp $");
37135048Swpaul
38135048Swpaul/*
39135048Swpaul * Driver for the Cicada CS8201 10/100/1000 copper PHY.
40135048Swpaul */
41135048Swpaul
42135048Swpaul#include <sys/param.h>
43135048Swpaul#include <sys/systm.h>
44135048Swpaul#include <sys/kernel.h>
45135048Swpaul#include <sys/module.h>
46135048Swpaul#include <sys/socket.h>
47135048Swpaul#include <sys/bus.h>
48135048Swpaul
49135048Swpaul#include <machine/clock.h>
50135048Swpaul
51135048Swpaul#include <net/if.h>
52135048Swpaul#include <net/if_arp.h>
53135048Swpaul#include <net/if_media.h>
54135048Swpaul
55135048Swpaul#include <dev/mii/mii.h>
56135048Swpaul#include <dev/mii/miivar.h>
57135048Swpaul#include "miidevs.h"
58135048Swpaul
59135048Swpaul#include <dev/mii/ciphyreg.h>
60135048Swpaul
61135048Swpaul#include "miibus_if.h"
62135048Swpaul
63135048Swpaul#include <machine/bus.h>
64135048Swpaul/*
65135048Swpaul#include <dev/vge/if_vgereg.h>
66135048Swpaul*/
67135048Swpaulstatic int ciphy_probe(device_t);
68135048Swpaulstatic int ciphy_attach(device_t);
69135048Swpaul
70135048Swpaulstatic device_method_t ciphy_methods[] = {
71135048Swpaul	/* device interface */
72135048Swpaul	DEVMETHOD(device_probe,		ciphy_probe),
73135048Swpaul	DEVMETHOD(device_attach,	ciphy_attach),
74135048Swpaul	DEVMETHOD(device_detach,	mii_phy_detach),
75135048Swpaul	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
76135048Swpaul	{ 0, 0 }
77135048Swpaul};
78135048Swpaul
79135048Swpaulstatic devclass_t ciphy_devclass;
80135048Swpaul
81135048Swpaulstatic driver_t ciphy_driver = {
82135048Swpaul	"ciphy",
83135048Swpaul	ciphy_methods,
84135048Swpaul	sizeof(struct mii_softc)
85135048Swpaul};
86135048Swpaul
87135048SwpaulDRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
88135048Swpaul
89135048Swpaulstatic int	ciphy_service(struct mii_softc *, struct mii_data *, int);
90135048Swpaulstatic void	ciphy_status(struct mii_softc *);
91135048Swpaulstatic void	ciphy_reset(struct mii_softc *);
92135048Swpaulstatic void	ciphy_fixup(struct mii_softc *);
93135048Swpaul
94135048Swpaulstatic int
95150763Simpciphy_probe(device_t dev)
96135048Swpaul{
97135048Swpaul	struct mii_attach_args *ma;
98135048Swpaul
99135048Swpaul	ma = device_get_ivars(dev);
100135048Swpaul
101135048Swpaul	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
102135048Swpaul	    MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201) {
103135048Swpaul		device_set_desc(dev, MII_STR_CICADA_CS8201);
104135048Swpaul		return(0);
105135048Swpaul	}
106135048Swpaul
107135048Swpaul	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
108135048Swpaul	    MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201A) {
109135048Swpaul		device_set_desc(dev, MII_STR_CICADA_CS8201A);
110135048Swpaul		return(0);
111135048Swpaul	}
112135048Swpaul
113135048Swpaul	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
114135048Swpaul	    MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201B) {
115135048Swpaul		device_set_desc(dev, MII_STR_CICADA_CS8201B);
116135048Swpaul		return(0);
117135048Swpaul	}
118135048Swpaul
119135048Swpaul	return(ENXIO);
120135048Swpaul}
121135048Swpaul
122135048Swpaulstatic int
123150763Simpciphy_attach(device_t dev)
124135048Swpaul{
125135048Swpaul	struct mii_softc *sc;
126135048Swpaul	struct mii_attach_args *ma;
127135048Swpaul	struct mii_data *mii;
128135048Swpaul
129135048Swpaul	sc = device_get_softc(dev);
130135048Swpaul	ma = device_get_ivars(dev);
131135048Swpaul	sc->mii_dev = device_get_parent(dev);
132135048Swpaul	mii = device_get_softc(sc->mii_dev);
133135048Swpaul	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
134135048Swpaul
135135048Swpaul	sc->mii_inst = mii->mii_instance;
136135048Swpaul	sc->mii_phy = ma->mii_phyno;
137135048Swpaul	sc->mii_service = ciphy_service;
138135048Swpaul	sc->mii_pdata = mii;
139135048Swpaul
140135048Swpaul	sc->mii_flags |= MIIF_NOISOLATE;
141135048Swpaul	mii->mii_instance++;
142135048Swpaul
143135048Swpaul	ciphy_reset(sc);
144135048Swpaul
145135048Swpaul	sc->mii_capabilities =
146135048Swpaul	    PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
147135048Swpaul	if (sc->mii_capabilities & BMSR_EXTSTAT)
148135048Swpaul		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
149135048Swpaul	device_printf(dev, " ");
150135048Swpaul	mii_phy_add_media(sc);
151135048Swpaul	printf("\n");
152135048Swpaul
153135048Swpaul	MIIBUS_MEDIAINIT(sc->mii_dev);
154135048Swpaul	return(0);
155135048Swpaul}
156135048Swpaul
157135048Swpaulstatic int
158150763Simpciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
159135048Swpaul{
160135048Swpaul	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
161135048Swpaul	int reg, speed, gig;
162135048Swpaul
163135048Swpaul	switch (cmd) {
164135048Swpaul	case MII_POLLSTAT:
165135048Swpaul		/*
166135048Swpaul		 * If we're not polling our PHY instance, just return.
167135048Swpaul		 */
168135048Swpaul		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
169135048Swpaul			return (0);
170135048Swpaul		break;
171135048Swpaul
172135048Swpaul	case MII_MEDIACHG:
173135048Swpaul		/*
174135048Swpaul		 * If the media indicates a different PHY instance,
175135048Swpaul		 * isolate ourselves.
176135048Swpaul		 */
177135048Swpaul		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
178135048Swpaul			reg = PHY_READ(sc, MII_BMCR);
179135048Swpaul			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
180135048Swpaul			return (0);
181135048Swpaul		}
182135048Swpaul
183135048Swpaul		/*
184135048Swpaul		 * If the interface is not up, don't do anything.
185135048Swpaul		 */
186135048Swpaul		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
187135048Swpaul			break;
188135048Swpaul
189135048Swpaul		ciphy_fixup(sc);	/* XXX hardware bug work-around */
190135048Swpaul
191135048Swpaul		switch (IFM_SUBTYPE(ife->ifm_media)) {
192135048Swpaul		case IFM_AUTO:
193135048Swpaul#ifdef foo
194135048Swpaul			/*
195135048Swpaul			 * If we're already in auto mode, just return.
196135048Swpaul			 */
197135048Swpaul			if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
198135048Swpaul				return (0);
199135048Swpaul#endif
200135048Swpaul			(void) mii_phy_auto(sc);
201135048Swpaul			break;
202135048Swpaul		case IFM_1000_T:
203135048Swpaul			speed = CIPHY_S1000;
204135048Swpaul			goto setit;
205135048Swpaul		case IFM_100_TX:
206135048Swpaul			speed = CIPHY_S100;
207135048Swpaul			goto setit;
208135048Swpaul		case IFM_10_T:
209135048Swpaul			speed = CIPHY_S10;
210135048Swpaulsetit:
211135048Swpaul			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
212135048Swpaul				speed |= CIPHY_BMCR_FDX;
213135048Swpaul				gig = CIPHY_1000CTL_AFD;
214135048Swpaul			} else {
215135048Swpaul				gig = CIPHY_1000CTL_AHD;
216135048Swpaul			}
217135048Swpaul
218135048Swpaul			PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
219135048Swpaul			PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
220135048Swpaul			PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
221135048Swpaul
222135048Swpaul			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
223135048Swpaul				break;
224135048Swpaul
225135048Swpaul			PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
226135048Swpaul			PHY_WRITE(sc, CIPHY_MII_BMCR,
227135048Swpaul			    speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
228135048Swpaul
229135048Swpaul			/*
230135048Swpaul			 * When setting the link manually, one side must
231135048Swpaul			 * be the master and the other the slave. However
232135048Swpaul			 * ifmedia doesn't give us a good way to specify
233135048Swpaul			 * this, so we fake it by using one of the LINK
234135048Swpaul			 * flags. If LINK0 is set, we program the PHY to
235135048Swpaul			 * be a master, otherwise it's a slave.
236135048Swpaul			 */
237135048Swpaul			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
238135048Swpaul				PHY_WRITE(sc, CIPHY_MII_1000CTL,
239135048Swpaul				    gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
240135048Swpaul			} else {
241135048Swpaul				PHY_WRITE(sc, CIPHY_MII_1000CTL,
242135048Swpaul				    gig|CIPHY_1000CTL_MSE);
243135048Swpaul			}
244135048Swpaul			break;
245135048Swpaul		case IFM_NONE:
246135048Swpaul			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
247135048Swpaul			break;
248135048Swpaul		case IFM_100_T4:
249135048Swpaul		default:
250135048Swpaul			return (EINVAL);
251135048Swpaul		}
252135048Swpaul		break;
253135048Swpaul
254135048Swpaul	case MII_TICK:
255135048Swpaul		/*
256135048Swpaul		 * If we're not currently selected, just return.
257135048Swpaul		 */
258135048Swpaul		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
259135048Swpaul			return (0);
260135048Swpaul
261135048Swpaul		/*
262135048Swpaul		 * Is the interface even up?
263135048Swpaul		 */
264135048Swpaul		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
265135048Swpaul			return (0);
266135048Swpaul
267135048Swpaul		/*
268135048Swpaul		 * Only used for autonegotiation.
269135048Swpaul		 */
270135048Swpaul		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
271135048Swpaul			break;
272135048Swpaul
273135048Swpaul		/*
274135048Swpaul		 * Check to see if we have link.  If we do, we don't
275135048Swpaul		 * need to restart the autonegotiation process.  Read
276135048Swpaul		 * the BMSR twice in case it's latched.
277135048Swpaul		 */
278135048Swpaul		reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
279135048Swpaul		if (reg & BMSR_LINK)
280135048Swpaul			break;
281135048Swpaul
282135048Swpaul		/*
283135048Swpaul		 * Only retry autonegotiation every 5 seconds.
284135048Swpaul		 */
285135048Swpaul		if (++sc->mii_ticks <= 5/*10*/)
286135048Swpaul			break;
287135048Swpaul
288135048Swpaul		sc->mii_ticks = 0;
289135048Swpaul		mii_phy_auto(sc);
290135048Swpaul		return (0);
291135048Swpaul	}
292135048Swpaul
293135048Swpaul	/* Update the media status. */
294135048Swpaul	ciphy_status(sc);
295135048Swpaul
296135048Swpaul	/*
297135048Swpaul	 * Callback if something changed. Note that we need to poke
298135048Swpaul	 * apply fixups for certain PHY revs.
299135048Swpaul	 */
300135048Swpaul	if (sc->mii_media_active != mii->mii_media_active ||
301135048Swpaul	    sc->mii_media_status != mii->mii_media_status ||
302135048Swpaul	    cmd == MII_MEDIACHG) {
303135048Swpaul		ciphy_fixup(sc);
304135048Swpaul	}
305135048Swpaul	mii_phy_update(sc, cmd);
306135048Swpaul	return (0);
307135048Swpaul}
308135048Swpaul
309135048Swpaulstatic void
310150763Simpciphy_status(struct mii_softc *sc)
311135048Swpaul{
312135048Swpaul	struct mii_data *mii = sc->mii_pdata;
313135048Swpaul	int bmsr, bmcr;
314135048Swpaul
315135048Swpaul	mii->mii_media_status = IFM_AVALID;
316135048Swpaul	mii->mii_media_active = IFM_ETHER;
317135048Swpaul
318135048Swpaul	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
319135048Swpaul
320135048Swpaul	if (bmsr & BMSR_LINK)
321135048Swpaul		mii->mii_media_status |= IFM_ACTIVE;
322135048Swpaul
323135048Swpaul	bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
324135048Swpaul
325135048Swpaul	if (bmcr & CIPHY_BMCR_LOOP)
326135048Swpaul		mii->mii_media_active |= IFM_LOOP;
327135048Swpaul
328135048Swpaul	if (bmcr & CIPHY_BMCR_AUTOEN) {
329135048Swpaul		if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
330135048Swpaul			/* Erg, still trying, I guess... */
331135048Swpaul			mii->mii_media_active |= IFM_NONE;
332135048Swpaul			return;
333135048Swpaul		}
334135048Swpaul	}
335135048Swpaul
336135048Swpaul	bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
337135048Swpaul	switch (bmsr & CIPHY_AUXCSR_SPEED) {
338135048Swpaul	case CIPHY_SPEED10:
339135048Swpaul		mii->mii_media_active |= IFM_10_T;
340135048Swpaul		break;
341135048Swpaul	case CIPHY_SPEED100:
342135048Swpaul		mii->mii_media_active |= IFM_100_TX;
343135048Swpaul		break;
344135048Swpaul	case CIPHY_SPEED1000:
345135048Swpaul		mii->mii_media_active |= IFM_1000_T;
346135048Swpaul		break;
347135048Swpaul	default:
348135048Swpaul		device_printf(sc->mii_dev, "unknown PHY speed %x\n",
349135048Swpaul		    bmsr & CIPHY_AUXCSR_SPEED);
350135048Swpaul		break;
351135048Swpaul	}
352135048Swpaul
353135048Swpaul	if (bmsr & CIPHY_AUXCSR_FDX)
354135048Swpaul		mii->mii_media_active |= IFM_FDX;
355135048Swpaul
356135048Swpaul	return;
357135048Swpaul}
358135048Swpaul
359135048Swpaulstatic void
360135048Swpaulciphy_reset(struct mii_softc *sc)
361135048Swpaul{
362135048Swpaul	mii_phy_reset(sc);
363135048Swpaul	DELAY(1000);
364135048Swpaul
365135048Swpaul	return;
366135048Swpaul}
367135048Swpaul
368135048Swpaul#define PHY_SETBIT(x, y, z) \
369135048Swpaul	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
370135048Swpaul#define PHY_CLRBIT(x, y, z) \
371135048Swpaul	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
372135048Swpaul
373135048Swpaulstatic void
374135048Swpaulciphy_fixup(struct mii_softc *sc)
375135048Swpaul{
376135048Swpaul	uint16_t		model;
377135048Swpaul	uint16_t		status, speed;
378135048Swpaul
379135048Swpaul	model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
380135048Swpaul	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
381135048Swpaul	speed = status & CIPHY_AUXCSR_SPEED;
382135048Swpaul
383135048Swpaul	switch (model) {
384135048Swpaul	case MII_MODEL_CICADA_CS8201:
385135048Swpaul
386135048Swpaul		/* Turn off "aux mode" (whatever that means) */
387135048Swpaul		PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
388135048Swpaul
389135048Swpaul		/*
390135048Swpaul		 * Work around speed polling bug in VT3119/VT3216
391135048Swpaul		 * when using MII in full duplex mode.
392135048Swpaul		 */
393135048Swpaul		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
394135048Swpaul		    (status & CIPHY_AUXCSR_FDX)) {
395135048Swpaul			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
396135048Swpaul		} else {
397135048Swpaul			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
398135048Swpaul		}
399135048Swpaul
400135048Swpaul		/* Enable link/activity LED blink. */
401135048Swpaul		PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
402135048Swpaul
403135048Swpaul		break;
404135048Swpaul
405135048Swpaul	case MII_MODEL_CICADA_CS8201A:
406135048Swpaul	case MII_MODEL_CICADA_CS8201B:
407135048Swpaul
408135048Swpaul		/*
409135048Swpaul		 * Work around speed polling bug in VT3119/VT3216
410135048Swpaul		 * when using MII in full duplex mode.
411135048Swpaul		 */
412135048Swpaul		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
413135048Swpaul		    (status & CIPHY_AUXCSR_FDX)) {
414135048Swpaul			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
415135048Swpaul		} else {
416135048Swpaul			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
417135048Swpaul		}
418135048Swpaul
419135048Swpaul		break;
420135048Swpaul	default:
421135048Swpaul		device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
422135048Swpaul		    model);
423135048Swpaul		break;
424135048Swpaul	}
425135048Swpaul
426135048Swpaul	return;
427135048Swpaul}
428