1139749Simp/*- 2135048Swpaul * Copyright (c) 2004 3135048Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4135048Swpaul * 5135048Swpaul * Redistribution and use in source and binary forms, with or without 6135048Swpaul * modification, are permitted provided that the following conditions 7135048Swpaul * are met: 8135048Swpaul * 1. Redistributions of source code must retain the above copyright 9135048Swpaul * notice, this list of conditions and the following disclaimer. 10135048Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11135048Swpaul * notice, this list of conditions and the following disclaimer in the 12135048Swpaul * documentation and/or other materials provided with the distribution. 13135048Swpaul * 3. All advertising materials mentioning features or use of this software 14135048Swpaul * must display the following acknowledgement: 15135048Swpaul * This product includes software developed by Bill Paul. 16135048Swpaul * 4. Neither the name of the author nor the names of any co-contributors 17135048Swpaul * may be used to endorse or promote products derived from this software 18135048Swpaul * without specific prior written permission. 19135048Swpaul * 20135048Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21135048Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22135048Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23135048Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24135048Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25135048Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26135048Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27135048Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28135048Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29135048Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30135048Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 31135048Swpaul */ 32135048Swpaul 33135048Swpaul#include <sys/cdefs.h> 34135048Swpaul__FBSDID("$FreeBSD: releng/10.2/sys/dev/mii/ciphy.c 235999 2012-05-25 15:05:17Z raj $"); 35135048Swpaul 36135048Swpaul/* 37178598Sraj * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY. 38135048Swpaul */ 39135048Swpaul 40135048Swpaul#include <sys/param.h> 41135048Swpaul#include <sys/systm.h> 42135048Swpaul#include <sys/kernel.h> 43135048Swpaul#include <sys/module.h> 44135048Swpaul#include <sys/socket.h> 45135048Swpaul#include <sys/bus.h> 46135048Swpaul 47135048Swpaul#include <net/if.h> 48135048Swpaul#include <net/if_arp.h> 49135048Swpaul#include <net/if_media.h> 50135048Swpaul 51135048Swpaul#include <dev/mii/mii.h> 52135048Swpaul#include <dev/mii/miivar.h> 53135048Swpaul#include "miidevs.h" 54135048Swpaul 55135048Swpaul#include <dev/mii/ciphyreg.h> 56135048Swpaul 57135048Swpaul#include "miibus_if.h" 58135048Swpaul 59135048Swpaul#include <machine/bus.h> 60213893Smarius 61135048Swpaulstatic int ciphy_probe(device_t); 62135048Swpaulstatic int ciphy_attach(device_t); 63135048Swpaul 64135048Swpaulstatic device_method_t ciphy_methods[] = { 65135048Swpaul /* device interface */ 66135048Swpaul DEVMETHOD(device_probe, ciphy_probe), 67135048Swpaul DEVMETHOD(device_attach, ciphy_attach), 68135048Swpaul DEVMETHOD(device_detach, mii_phy_detach), 69135048Swpaul DEVMETHOD(device_shutdown, bus_generic_shutdown), 70227908Smarius DEVMETHOD_END 71135048Swpaul}; 72135048Swpaul 73135048Swpaulstatic devclass_t ciphy_devclass; 74135048Swpaul 75135048Swpaulstatic driver_t ciphy_driver = { 76135048Swpaul "ciphy", 77135048Swpaul ciphy_methods, 78135048Swpaul sizeof(struct mii_softc) 79135048Swpaul}; 80135048Swpaul 81135048SwpaulDRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 82135048Swpaul 83135048Swpaulstatic int ciphy_service(struct mii_softc *, struct mii_data *, int); 84135048Swpaulstatic void ciphy_status(struct mii_softc *); 85135048Swpaulstatic void ciphy_reset(struct mii_softc *); 86135048Swpaulstatic void ciphy_fixup(struct mii_softc *); 87135048Swpaul 88164827Smariusstatic const struct mii_phydesc ciphys[] = { 89221407Smarius MII_PHY_DESC(xxCICADA, CS8201), 90221407Smarius MII_PHY_DESC(xxCICADA, CS8201A), 91221407Smarius MII_PHY_DESC(xxCICADA, CS8201B), 92221407Smarius MII_PHY_DESC(xxCICADA, CS8204), 93221407Smarius MII_PHY_DESC(xxCICADA, VSC8211), 94235999Sraj MII_PHY_DESC(xxCICADA, VSC8221), 95221407Smarius MII_PHY_DESC(xxCICADA, CS8244), 96221407Smarius MII_PHY_DESC(xxVITESSE, VSC8601), 97235999Sraj MII_PHY_DESC(xxVITESSE, VSC8641), 98164827Smarius MII_PHY_END 99164827Smarius}; 100164827Smarius 101221407Smariusstatic const struct mii_phy_funcs ciphy_funcs = { 102221407Smarius ciphy_service, 103221407Smarius ciphy_status, 104221407Smarius ciphy_reset 105221407Smarius}; 106221407Smarius 107135048Swpaulstatic int 108150763Simpciphy_probe(device_t dev) 109135048Swpaul{ 110135048Swpaul 111164827Smarius return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT)); 112135048Swpaul} 113135048Swpaul 114135048Swpaulstatic int 115150763Simpciphy_attach(device_t dev) 116135048Swpaul{ 117135048Swpaul 118221407Smarius mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 119221407Smarius &ciphy_funcs, 1); 120164705Smarius return (0); 121135048Swpaul} 122135048Swpaul 123135048Swpaulstatic int 124150763Simpciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 125135048Swpaul{ 126135048Swpaul struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 127135048Swpaul int reg, speed, gig; 128135048Swpaul 129135048Swpaul switch (cmd) { 130135048Swpaul case MII_POLLSTAT: 131135048Swpaul break; 132135048Swpaul 133135048Swpaul case MII_MEDIACHG: 134135048Swpaul /* 135135048Swpaul * If the interface is not up, don't do anything. 136135048Swpaul */ 137135048Swpaul if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 138135048Swpaul break; 139135048Swpaul 140135048Swpaul ciphy_fixup(sc); /* XXX hardware bug work-around */ 141135048Swpaul 142135048Swpaul switch (IFM_SUBTYPE(ife->ifm_media)) { 143135048Swpaul case IFM_AUTO: 144135048Swpaul#ifdef foo 145135048Swpaul /* 146135048Swpaul * If we're already in auto mode, just return. 147135048Swpaul */ 148135048Swpaul if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 149135048Swpaul return (0); 150135048Swpaul#endif 151215297Smarius (void)mii_phy_auto(sc); 152135048Swpaul break; 153135048Swpaul case IFM_1000_T: 154135048Swpaul speed = CIPHY_S1000; 155135048Swpaul goto setit; 156135048Swpaul case IFM_100_TX: 157135048Swpaul speed = CIPHY_S100; 158135048Swpaul goto setit; 159135048Swpaul case IFM_10_T: 160135048Swpaul speed = CIPHY_S10; 161135048Swpaulsetit: 162217413Smarius if ((ife->ifm_media & IFM_FDX) != 0) { 163135048Swpaul speed |= CIPHY_BMCR_FDX; 164135048Swpaul gig = CIPHY_1000CTL_AFD; 165217413Smarius } else 166135048Swpaul gig = CIPHY_1000CTL_AHD; 167135048Swpaul 168217413Smarius if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 169217413Smarius gig |= CIPHY_1000CTL_MSE; 170217413Smarius if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 171217413Smarius gig |= CIPHY_1000CTL_MSC; 172217413Smarius speed |= 173217413Smarius CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG; 174217413Smarius } else 175217413Smarius gig = 0; 176217413Smarius PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 177135048Swpaul PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 178135048Swpaul PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 179135048Swpaul break; 180135048Swpaul case IFM_NONE: 181215297Smarius PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 182135048Swpaul break; 183135048Swpaul default: 184135048Swpaul return (EINVAL); 185135048Swpaul } 186135048Swpaul break; 187135048Swpaul 188135048Swpaul case MII_TICK: 189135048Swpaul /* 190135048Swpaul * Is the interface even up? 191135048Swpaul */ 192135048Swpaul if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 193135048Swpaul return (0); 194135048Swpaul 195135048Swpaul /* 196135048Swpaul * Only used for autonegotiation. 197135048Swpaul */ 198135048Swpaul if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 199135048Swpaul break; 200135048Swpaul 201135048Swpaul /* 202135048Swpaul * Check to see if we have link. If we do, we don't 203135048Swpaul * need to restart the autonegotiation process. Read 204135048Swpaul * the BMSR twice in case it's latched. 205135048Swpaul */ 206135048Swpaul reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 207135048Swpaul if (reg & BMSR_LINK) 208135048Swpaul break; 209135048Swpaul 210183488Syongari /* Announce link loss right after it happens. */ 211183488Syongari if (++sc->mii_ticks == 0) 212183488Syongari break; 213135048Swpaul /* 214183489Syongari * Only retry autonegotiation every mii_anegticks seconds. 215135048Swpaul */ 216183489Syongari if (sc->mii_ticks <= sc->mii_anegticks) 217135048Swpaul break; 218164705Smarius 219135048Swpaul sc->mii_ticks = 0; 220135048Swpaul mii_phy_auto(sc); 221183490Syongari break; 222135048Swpaul } 223135048Swpaul 224135048Swpaul /* Update the media status. */ 225221407Smarius PHY_STATUS(sc); 226135048Swpaul 227135048Swpaul /* 228135048Swpaul * Callback if something changed. Note that we need to poke 229135048Swpaul * apply fixups for certain PHY revs. 230135048Swpaul */ 231164705Smarius if (sc->mii_media_active != mii->mii_media_active || 232135048Swpaul sc->mii_media_status != mii->mii_media_status || 233135048Swpaul cmd == MII_MEDIACHG) { 234135048Swpaul ciphy_fixup(sc); 235135048Swpaul } 236135048Swpaul mii_phy_update(sc, cmd); 237135048Swpaul return (0); 238135048Swpaul} 239135048Swpaul 240135048Swpaulstatic void 241150763Simpciphy_status(struct mii_softc *sc) 242135048Swpaul{ 243135048Swpaul struct mii_data *mii = sc->mii_pdata; 244135048Swpaul int bmsr, bmcr; 245135048Swpaul 246135048Swpaul mii->mii_media_status = IFM_AVALID; 247135048Swpaul mii->mii_media_active = IFM_ETHER; 248135048Swpaul 249135048Swpaul bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 250135048Swpaul 251135048Swpaul if (bmsr & BMSR_LINK) 252135048Swpaul mii->mii_media_status |= IFM_ACTIVE; 253135048Swpaul 254135048Swpaul bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 255135048Swpaul 256135048Swpaul if (bmcr & CIPHY_BMCR_LOOP) 257135048Swpaul mii->mii_media_active |= IFM_LOOP; 258135048Swpaul 259135048Swpaul if (bmcr & CIPHY_BMCR_AUTOEN) { 260135048Swpaul if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 261135048Swpaul /* Erg, still trying, I guess... */ 262135048Swpaul mii->mii_media_active |= IFM_NONE; 263135048Swpaul return; 264135048Swpaul } 265135048Swpaul } 266135048Swpaul 267135048Swpaul bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 268135048Swpaul switch (bmsr & CIPHY_AUXCSR_SPEED) { 269135048Swpaul case CIPHY_SPEED10: 270135048Swpaul mii->mii_media_active |= IFM_10_T; 271135048Swpaul break; 272135048Swpaul case CIPHY_SPEED100: 273135048Swpaul mii->mii_media_active |= IFM_100_TX; 274135048Swpaul break; 275135048Swpaul case CIPHY_SPEED1000: 276135048Swpaul mii->mii_media_active |= IFM_1000_T; 277135048Swpaul break; 278135048Swpaul default: 279135048Swpaul device_printf(sc->mii_dev, "unknown PHY speed %x\n", 280135048Swpaul bmsr & CIPHY_AUXCSR_SPEED); 281135048Swpaul break; 282135048Swpaul } 283135048Swpaul 284135048Swpaul if (bmsr & CIPHY_AUXCSR_FDX) 285221407Smarius mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 286183491Syongari else 287183491Syongari mii->mii_media_active |= IFM_HDX; 288215297Smarius 289215297Smarius if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 290215297Smarius (PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0) 291215297Smarius mii->mii_media_active |= IFM_ETH_MASTER; 292135048Swpaul} 293135048Swpaul 294135048Swpaulstatic void 295135048Swpaulciphy_reset(struct mii_softc *sc) 296135048Swpaul{ 297164830Smarius 298135048Swpaul mii_phy_reset(sc); 299135048Swpaul DELAY(1000); 300135048Swpaul} 301135048Swpaul 302135048Swpaul#define PHY_SETBIT(x, y, z) \ 303135048Swpaul PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 304135048Swpaul#define PHY_CLRBIT(x, y, z) \ 305135048Swpaul PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 306135048Swpaul 307135048Swpaulstatic void 308135048Swpaulciphy_fixup(struct mii_softc *sc) 309135048Swpaul{ 310135048Swpaul uint16_t model; 311135048Swpaul uint16_t status, speed; 312170365Syongari uint16_t val; 313135048Swpaul 314135048Swpaul model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 315135048Swpaul status = PHY_READ(sc, CIPHY_MII_AUXCSR); 316135048Swpaul speed = status & CIPHY_AUXCSR_SPEED; 317135048Swpaul 318170365Syongari if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), 319170365Syongari "nfe") == 0) { 320170365Syongari /* need to set for 2.5V RGMII for NVIDIA adapters */ 321170365Syongari val = PHY_READ(sc, CIPHY_MII_ECTL1); 322170365Syongari val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); 323170365Syongari val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); 324170365Syongari PHY_WRITE(sc, CIPHY_MII_ECTL1, val); 325170365Syongari /* From Linux. */ 326170365Syongari val = PHY_READ(sc, CIPHY_MII_AUXCSR); 327170365Syongari val |= CIPHY_AUXCSR_MDPPS; 328170365Syongari PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); 329170365Syongari val = PHY_READ(sc, CIPHY_MII_10BTCSR); 330170365Syongari val |= CIPHY_10BTCSR_ECHO; 331170365Syongari PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); 332170365Syongari } 333170365Syongari 334135048Swpaul switch (model) { 335221407Smarius case MII_MODEL_xxCICADA_CS8204: 336221407Smarius case MII_MODEL_xxCICADA_CS8201: 337135048Swpaul 338135048Swpaul /* Turn off "aux mode" (whatever that means) */ 339135048Swpaul PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 340135048Swpaul 341135048Swpaul /* 342135048Swpaul * Work around speed polling bug in VT3119/VT3216 343135048Swpaul * when using MII in full duplex mode. 344135048Swpaul */ 345135048Swpaul if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 346135048Swpaul (status & CIPHY_AUXCSR_FDX)) { 347135048Swpaul PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 348135048Swpaul } else { 349135048Swpaul PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 350135048Swpaul } 351135048Swpaul 352135048Swpaul /* Enable link/activity LED blink. */ 353135048Swpaul PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 354135048Swpaul 355135048Swpaul break; 356135048Swpaul 357221407Smarius case MII_MODEL_xxCICADA_CS8201A: 358221407Smarius case MII_MODEL_xxCICADA_CS8201B: 359135048Swpaul 360135048Swpaul /* 361135048Swpaul * Work around speed polling bug in VT3119/VT3216 362135048Swpaul * when using MII in full duplex mode. 363135048Swpaul */ 364135048Swpaul if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 365135048Swpaul (status & CIPHY_AUXCSR_FDX)) { 366135048Swpaul PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 367135048Swpaul } else { 368135048Swpaul PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 369135048Swpaul } 370135048Swpaul 371135048Swpaul break; 372221407Smarius case MII_MODEL_xxCICADA_VSC8211: 373235999Sraj case MII_MODEL_xxCICADA_VSC8221: 374221407Smarius case MII_MODEL_xxCICADA_CS8244: 375221407Smarius case MII_MODEL_xxVITESSE_VSC8601: 376235999Sraj case MII_MODEL_xxVITESSE_VSC8641: 377170365Syongari break; 378135048Swpaul default: 379135048Swpaul device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", 380135048Swpaul model); 381135048Swpaul break; 382135048Swpaul } 383135048Swpaul} 384