brgphy.c revision 215353
1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 215353 2010-11-15 23:13:25Z jkim $"); 35 36/* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/bus.h> 46 47#include <net/if.h> 48#include <net/ethernet.h> 49#include <net/if_media.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include "miidevs.h" 54 55#include <dev/mii/brgphyreg.h> 56#include <net/if_arp.h> 57#include <machine/bus.h> 58#include <dev/bge/if_bgereg.h> 59#include <dev/bce/if_bcereg.h> 60 61#include <dev/pci/pcireg.h> 62#include <dev/pci/pcivar.h> 63 64#include "miibus_if.h" 65 66static int brgphy_probe(device_t); 67static int brgphy_attach(device_t); 68 69struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_oui; 72 int mii_model; 73 int mii_rev; 74 int serdes_flags; /* Keeps track of the serdes type used */ 75#define BRGPHY_5706S 0x0001 76#define BRGPHY_5708S 0x0002 77#define BRGPHY_NOANWAIT 0x0004 78#define BRGPHY_5709S 0x0008 79 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 80}; 81 82static device_method_t brgphy_methods[] = { 83 /* device interface */ 84 DEVMETHOD(device_probe, brgphy_probe), 85 DEVMETHOD(device_attach, brgphy_attach), 86 DEVMETHOD(device_detach, mii_phy_detach), 87 DEVMETHOD(device_shutdown, bus_generic_shutdown), 88 { 0, 0 } 89}; 90 91static devclass_t brgphy_devclass; 92 93static driver_t brgphy_driver = { 94 "brgphy", 95 brgphy_methods, 96 sizeof(struct brgphy_softc) 97}; 98 99DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 100 101static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102static void brgphy_setmedia(struct mii_softc *, int); 103static void brgphy_status(struct mii_softc *); 104static void brgphy_mii_phy_auto(struct mii_softc *, int); 105static void brgphy_reset(struct mii_softc *); 106static void brgphy_enable_loopback(struct mii_softc *); 107static void bcm5401_load_dspcode(struct mii_softc *); 108static void bcm5411_load_dspcode(struct mii_softc *); 109static void bcm54k2_load_dspcode(struct mii_softc *); 110static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 111static void brgphy_fixup_adc_bug(struct mii_softc *); 112static void brgphy_fixup_adjust_trim(struct mii_softc *); 113static void brgphy_fixup_ber_bug(struct mii_softc *); 114static void brgphy_fixup_crc_bug(struct mii_softc *); 115static void brgphy_fixup_jitter_bug(struct mii_softc *); 116static void brgphy_ethernet_wirespeed(struct mii_softc *); 117static void brgphy_jumbo_settings(struct mii_softc *, u_long); 118 119static const struct mii_phydesc brgphys[] = { 120 MII_PHY_DESC(xxBROADCOM, BCM5400), 121 MII_PHY_DESC(xxBROADCOM, BCM5401), 122 MII_PHY_DESC(xxBROADCOM, BCM5411), 123 MII_PHY_DESC(xxBROADCOM, BCM54K2), 124 MII_PHY_DESC(xxBROADCOM, BCM5701), 125 MII_PHY_DESC(xxBROADCOM, BCM5703), 126 MII_PHY_DESC(xxBROADCOM, BCM5704), 127 MII_PHY_DESC(xxBROADCOM, BCM5705), 128 MII_PHY_DESC(xxBROADCOM, BCM5706), 129 MII_PHY_DESC(xxBROADCOM, BCM5714), 130 MII_PHY_DESC(xxBROADCOM, BCM5750), 131 MII_PHY_DESC(xxBROADCOM, BCM5752), 132 MII_PHY_DESC(xxBROADCOM, BCM5754), 133 MII_PHY_DESC(xxBROADCOM, BCM5780), 134 MII_PHY_DESC(xxBROADCOM, BCM5708C), 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5482S), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 141 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), 142 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 143 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), 144 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), 145 MII_PHY_DESC(xxBROADCOM_ALT2, BCM5717C), 146 MII_PHY_DESC(BROADCOM2, BCM5906), 147 MII_PHY_END 148}; 149 150#define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 151#define HS21_BCM_CHIPID 0x57081021 152 153static int 154detect_hs21(struct bce_softc *bce_sc) 155{ 156 char *sysenv; 157 int found; 158 159 found = 0; 160 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { 161 sysenv = getenv("smbios.system.product"); 162 if (sysenv != NULL) { 163 if (strcmp(sysenv, HS21_PRODUCT_ID) == 0) 164 found = 1; 165 freeenv(sysenv); 166 } 167 } 168 return (found); 169} 170 171/* Search for our PHY in the list of known PHYs */ 172static int 173brgphy_probe(device_t dev) 174{ 175 176 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 177} 178 179/* Attach the PHY to the MII bus */ 180static int 181brgphy_attach(device_t dev) 182{ 183 struct brgphy_softc *bsc; 184 struct bge_softc *bge_sc = NULL; 185 struct bce_softc *bce_sc = NULL; 186 struct mii_softc *sc; 187 struct mii_attach_args *ma; 188 struct mii_data *mii; 189 struct ifnet *ifp; 190 191 bsc = device_get_softc(dev); 192 sc = &bsc->mii_sc; 193 ma = device_get_ivars(dev); 194 sc->mii_dev = device_get_parent(dev); 195 mii = ma->mii_data; 196 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 197 198 /* Initialize mii_softc structure */ 199 sc->mii_flags = miibus_get_flags(dev); 200 sc->mii_inst = mii->mii_instance++; 201 sc->mii_phy = ma->mii_phyno; 202 sc->mii_service = brgphy_service; 203 sc->mii_pdata = mii; 204 205 /* 206 * At least some variants wedge when isolating, at least some also 207 * don't support loopback. 208 */ 209 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE; 210 211 /* Initialize brgphy_softc structure */ 212 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 213 bsc->mii_model = MII_MODEL(ma->mii_id2); 214 bsc->mii_rev = MII_REV(ma->mii_id2); 215 bsc->serdes_flags = 0; 216 217 if (bootverbose) 218 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 219 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 220 221 /* Handle any special cases based on the PHY ID */ 222 switch (bsc->mii_oui) { 223 case MII_OUI_BROADCOM: 224 case MII_OUI_BROADCOM2: 225 break; 226 case MII_OUI_xxBROADCOM: 227 switch (bsc->mii_model) { 228 case MII_MODEL_xxBROADCOM_BCM5706: 229 case MII_MODEL_xxBROADCOM_BCM5714: 230 /* 231 * The 5464 PHY used in the 5706 supports both copper 232 * and fiber interfaces over GMII. Need to check the 233 * shadow registers to see which mode is actually 234 * in effect, and therefore whether we have 5706C or 235 * 5706S. 236 */ 237 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 238 BRGPHY_SHADOW_1C_MODE_CTRL); 239 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 240 BRGPHY_SHADOW_1C_ENA_1000X) { 241 bsc->serdes_flags |= BRGPHY_5706S; 242 sc->mii_flags |= MIIF_HAVEFIBER; 243 } 244 break; 245 } break; 246 case MII_OUI_xxBROADCOM_ALT1: 247 switch (bsc->mii_model) { 248 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 249 bsc->serdes_flags |= BRGPHY_5708S; 250 sc->mii_flags |= MIIF_HAVEFIBER; 251 break; 252 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: 253 bsc->serdes_flags |= BRGPHY_5709S; 254 sc->mii_flags |= MIIF_HAVEFIBER; 255 break; 256 } 257 break; 258 case MII_OUI_xxBROADCOM_ALT2: 259 /* No special handling yet. */ 260 break; 261 default: 262 device_printf(dev, "Unrecognized OUI for PHY!\n"); 263 } 264 265 ifp = sc->mii_pdata->mii_ifp; 266 267 /* Find the MAC driver associated with this PHY. */ 268 if (strcmp(ifp->if_dname, "bge") == 0) { 269 bge_sc = ifp->if_softc; 270 } else if (strcmp(ifp->if_dname, "bce") == 0) { 271 bce_sc = ifp->if_softc; 272 } 273 274 brgphy_reset(sc); 275 276 /* Read the PHY's capabilities. */ 277 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 278 if (sc->mii_capabilities & BMSR_EXTSTAT) 279 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 280 device_printf(dev, " "); 281 282#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 283 284 /* Add the supported media types */ 285 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 286 mii_phy_add_media(sc); 287 printf("\n"); 288 } else { 289 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 290 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 291 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 292 printf("1000baseSX-FDX, "); 293 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 294 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 295 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 296 printf("2500baseSX-FDX, "); 297 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 298 (detect_hs21(bce_sc) != 0)) { 299 /* 300 * There appears to be certain silicon revision 301 * in IBM HS21 blades that is having issues with 302 * this driver wating for the auto-negotiation to 303 * complete. This happens with a specific chip id 304 * only and when the 1000baseSX-FDX is the only 305 * mode. Workaround this issue since it's unlikely 306 * to be ever addressed. 307 */ 308 printf("auto-neg workaround, "); 309 bsc->serdes_flags |= BRGPHY_NOANWAIT; 310 } 311 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 312 printf("auto\n"); 313 } 314 315#undef ADD 316 MIIBUS_MEDIAINIT(sc->mii_dev); 317 return (0); 318} 319 320static int 321brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 322{ 323 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 324 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 325 int val; 326 327 switch (cmd) { 328 case MII_POLLSTAT: 329 break; 330 case MII_MEDIACHG: 331 /* If the interface is not up, don't do anything. */ 332 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 333 break; 334 335 /* Todo: Why is this here? Is it really needed? */ 336 brgphy_reset(sc); /* XXX hardware bug work-around */ 337 338 switch (IFM_SUBTYPE(ife->ifm_media)) { 339 case IFM_AUTO: 340 brgphy_mii_phy_auto(sc, ife->ifm_media); 341 break; 342 case IFM_2500_SX: 343 case IFM_1000_SX: 344 case IFM_1000_T: 345 case IFM_100_TX: 346 case IFM_10_T: 347 brgphy_setmedia(sc, ife->ifm_media); 348 break; 349 default: 350 return (EINVAL); 351 } 352 break; 353 case MII_TICK: 354 /* Bail if the interface isn't up. */ 355 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 356 return (0); 357 358 359 /* Bail if autoneg isn't in process. */ 360 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 361 sc->mii_ticks = 0; 362 break; 363 } 364 365 /* 366 * Check to see if we have link. If we do, we don't 367 * need to restart the autonegotiation process. 368 */ 369 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 370 if (val & BMSR_LINK) { 371 sc->mii_ticks = 0; /* Reset autoneg timer. */ 372 break; 373 } 374 375 /* Announce link loss right after it happens. */ 376 if (sc->mii_ticks++ == 0) 377 break; 378 379 /* Only retry autonegotiation every mii_anegticks seconds. */ 380 if (sc->mii_ticks <= sc->mii_anegticks) 381 break; 382 383 384 /* Retry autonegotiation */ 385 sc->mii_ticks = 0; 386 brgphy_mii_phy_auto(sc, ife->ifm_media); 387 break; 388 } 389 390 /* Update the media status. */ 391 brgphy_status(sc); 392 393 /* 394 * Callback if something changed. Note that we need to poke 395 * the DSP on the Broadcom PHYs if the media changes. 396 */ 397 if (sc->mii_media_active != mii->mii_media_active || 398 sc->mii_media_status != mii->mii_media_status || 399 cmd == MII_MEDIACHG) { 400 switch (bsc->mii_oui) { 401 case MII_OUI_BROADCOM: 402 break; 403 case MII_OUI_xxBROADCOM: 404 switch (bsc->mii_model) { 405 case MII_MODEL_xxBROADCOM_BCM5400: 406 bcm5401_load_dspcode(sc); 407 break; 408 case MII_MODEL_xxBROADCOM_BCM5401: 409 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 410 bcm5401_load_dspcode(sc); 411 break; 412 case MII_MODEL_xxBROADCOM_BCM5411: 413 bcm5411_load_dspcode(sc); 414 break; 415 case MII_MODEL_xxBROADCOM_BCM54K2: 416 bcm54k2_load_dspcode(sc); 417 break; 418 } 419 break; 420 case MII_OUI_xxBROADCOM_ALT1: 421 break; 422 } 423 } 424 mii_phy_update(sc, cmd); 425 return (0); 426} 427 428/****************************************************************************/ 429/* Sets the PHY link speed. */ 430/* */ 431/* Returns: */ 432/* None */ 433/****************************************************************************/ 434static void 435brgphy_setmedia(struct mii_softc *sc, int media) 436{ 437 int bmcr = 0, gig; 438 439 switch (IFM_SUBTYPE(media)) { 440 case IFM_2500_SX: 441 break; 442 case IFM_1000_SX: 443 case IFM_1000_T: 444 bmcr = BRGPHY_S1000; 445 break; 446 case IFM_100_TX: 447 bmcr = BRGPHY_S100; 448 break; 449 case IFM_10_T: 450 default: 451 bmcr = BRGPHY_S10; 452 break; 453 } 454 455 if ((media & IFM_GMASK) == IFM_FDX) { 456 bmcr |= BRGPHY_BMCR_FDX; 457 gig = BRGPHY_1000CTL_AFD; 458 } else { 459 gig = BRGPHY_1000CTL_AHD; 460 } 461 462 /* Force loopback to disconnect PHY from Ethernet medium. */ 463 brgphy_enable_loopback(sc); 464 465 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 466 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 467 468 if (IFM_SUBTYPE(media) != IFM_1000_T && 469 IFM_SUBTYPE(media) != IFM_1000_SX) { 470 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 471 return; 472 } 473 474 if (IFM_SUBTYPE(media) == IFM_1000_T) { 475 gig |= BRGPHY_1000CTL_MSE; 476 if ((media & IFM_ETH_MASTER) != 0) 477 gig |= BRGPHY_1000CTL_MSC; 478 } 479 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 480 PHY_WRITE(sc, BRGPHY_MII_BMCR, 481 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 482} 483 484/****************************************************************************/ 485/* Set the media status based on the PHY settings. */ 486/* */ 487/* Returns: */ 488/* None */ 489/****************************************************************************/ 490static void 491brgphy_status(struct mii_softc *sc) 492{ 493 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 494 struct mii_data *mii = sc->mii_pdata; 495 int aux, bmcr, bmsr, val, xstat; 496 u_int flowstat; 497 498 mii->mii_media_status = IFM_AVALID; 499 mii->mii_media_active = IFM_ETHER; 500 501 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 502 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 503 504 if (bmcr & BRGPHY_BMCR_LOOP) { 505 mii->mii_media_active |= IFM_LOOP; 506 } 507 508 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 509 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 510 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 511 /* Erg, still trying, I guess... */ 512 mii->mii_media_active |= IFM_NONE; 513 return; 514 } 515 516 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 517 /* 518 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 519 * wedges at least the PHY of BCM5704 (but not others). 520 */ 521 flowstat = mii_phy_flowstatus(sc); 522 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 523 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 524 525 /* If copper link is up, get the negotiated speed/duplex. */ 526 if (aux & BRGPHY_AUXSTS_LINK) { 527 mii->mii_media_status |= IFM_ACTIVE; 528 switch (aux & BRGPHY_AUXSTS_AN_RES) { 529 case BRGPHY_RES_1000FD: 530 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 531 case BRGPHY_RES_1000HD: 532 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 533 case BRGPHY_RES_100FD: 534 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 535 case BRGPHY_RES_100T4: 536 mii->mii_media_active |= IFM_100_T4; break; 537 case BRGPHY_RES_100HD: 538 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 539 case BRGPHY_RES_10FD: 540 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 541 case BRGPHY_RES_10HD: 542 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 543 default: 544 mii->mii_media_active |= IFM_NONE; break; 545 } 546 547 if ((mii->mii_media_active & IFM_FDX) != 0) 548 mii->mii_media_active |= flowstat; 549 550 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 551 (xstat & BRGPHY_1000STS_MSR) != 0) 552 mii->mii_media_active |= IFM_ETH_MASTER; 553 } 554 } else { 555 /* Todo: Add support for flow control. */ 556 /* If serdes link is up, get the negotiated speed/duplex. */ 557 if (bmsr & BRGPHY_BMSR_LINK) { 558 mii->mii_media_status |= IFM_ACTIVE; 559 } 560 561 /* Check the link speed/duplex based on the PHY type. */ 562 if (bsc->serdes_flags & BRGPHY_5706S) { 563 mii->mii_media_active |= IFM_1000_SX; 564 565 /* If autoneg enabled, read negotiated duplex settings */ 566 if (bmcr & BRGPHY_BMCR_AUTOEN) { 567 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 568 if (val & BRGPHY_SERDES_ANAR_FDX) 569 mii->mii_media_active |= IFM_FDX; 570 else 571 mii->mii_media_active |= IFM_HDX; 572 } 573 } else if (bsc->serdes_flags & BRGPHY_5708S) { 574 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 575 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 576 577 /* Check for MRBE auto-negotiated speed results. */ 578 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 579 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 580 mii->mii_media_active |= IFM_10_FL; break; 581 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 582 mii->mii_media_active |= IFM_100_FX; break; 583 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 584 mii->mii_media_active |= IFM_1000_SX; break; 585 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 586 mii->mii_media_active |= IFM_2500_SX; break; 587 } 588 589 /* Check for MRBE auto-negotiated duplex results. */ 590 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 591 mii->mii_media_active |= IFM_FDX; 592 else 593 mii->mii_media_active |= IFM_HDX; 594 } else if (bsc->serdes_flags & BRGPHY_5709S) { 595 /* Select GP Status Block of the AN MMD, get autoneg results. */ 596 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 597 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 598 599 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 600 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 601 602 /* Check for MRBE auto-negotiated speed results. */ 603 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 604 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 605 mii->mii_media_active |= IFM_10_FL; break; 606 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 607 mii->mii_media_active |= IFM_100_FX; break; 608 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 609 mii->mii_media_active |= IFM_1000_SX; break; 610 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 611 mii->mii_media_active |= IFM_2500_SX; break; 612 } 613 614 /* Check for MRBE auto-negotiated duplex results. */ 615 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 616 mii->mii_media_active |= IFM_FDX; 617 else 618 mii->mii_media_active |= IFM_HDX; 619 } 620 } 621} 622 623static void 624brgphy_mii_phy_auto(struct mii_softc *sc, int media) 625{ 626 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 627 int anar, ktcr = 0; 628 629 brgphy_reset(sc); 630 631 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 632 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 633 if ((media & IFM_FLOW) != 0 || 634 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 635 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 636 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 637 } else { 638 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 639 if ((media & IFM_FLOW) != 0 || 640 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 641 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 642 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 643 } 644 645 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 646 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 647 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 648 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 649 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 650 651 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 652 BRGPHY_BMCR_STARTNEG); 653 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 654} 655 656/* Enable loopback to force the link down. */ 657static void 658brgphy_enable_loopback(struct mii_softc *sc) 659{ 660 int i; 661 662 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 663 for (i = 0; i < 15000; i++) { 664 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 665 break; 666 DELAY(10); 667 } 668} 669 670/* Turn off tap power management on 5401. */ 671static void 672bcm5401_load_dspcode(struct mii_softc *sc) 673{ 674 static const struct { 675 int reg; 676 uint16_t val; 677 } dspcode[] = { 678 { BRGPHY_MII_AUXCTL, 0x0c20 }, 679 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 680 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 681 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 682 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 683 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 684 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 685 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 686 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 687 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 688 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 689 { 0, 0 }, 690 }; 691 int i; 692 693 for (i = 0; dspcode[i].reg != 0; i++) 694 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 695 DELAY(40); 696} 697 698static void 699bcm5411_load_dspcode(struct mii_softc *sc) 700{ 701 static const struct { 702 int reg; 703 uint16_t val; 704 } dspcode[] = { 705 { 0x1c, 0x8c23 }, 706 { 0x1c, 0x8ca3 }, 707 { 0x1c, 0x8c23 }, 708 { 0, 0 }, 709 }; 710 int i; 711 712 for (i = 0; dspcode[i].reg != 0; i++) 713 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 714} 715 716void 717bcm54k2_load_dspcode(struct mii_softc *sc) 718{ 719 static const struct { 720 int reg; 721 uint16_t val; 722 } dspcode[] = { 723 { 4, 0x01e1 }, 724 { 9, 0x0300 }, 725 { 0, 0 }, 726 }; 727 int i; 728 729 for (i = 0; dspcode[i].reg != 0; i++) 730 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 731 732} 733 734static void 735brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 736{ 737 static const struct { 738 int reg; 739 uint16_t val; 740 } dspcode[] = { 741 { 0x1c, 0x8d68 }, 742 { 0x1c, 0x8d68 }, 743 { 0, 0 }, 744 }; 745 int i; 746 747 for (i = 0; dspcode[i].reg != 0; i++) 748 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 749} 750 751static void 752brgphy_fixup_adc_bug(struct mii_softc *sc) 753{ 754 static const struct { 755 int reg; 756 uint16_t val; 757 } dspcode[] = { 758 { BRGPHY_MII_AUXCTL, 0x0c00 }, 759 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 760 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 761 { 0, 0 }, 762 }; 763 int i; 764 765 for (i = 0; dspcode[i].reg != 0; i++) 766 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 767} 768 769static void 770brgphy_fixup_adjust_trim(struct mii_softc *sc) 771{ 772 static const struct { 773 int reg; 774 uint16_t val; 775 } dspcode[] = { 776 { BRGPHY_MII_AUXCTL, 0x0c00 }, 777 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 778 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 779 { BRGPHY_MII_TEST1, 0x0014 }, 780 { BRGPHY_MII_AUXCTL, 0x0400 }, 781 { 0, 0 }, 782 }; 783 int i; 784 785 for (i = 0; dspcode[i].reg != 0; i++) 786 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 787} 788 789static void 790brgphy_fixup_ber_bug(struct mii_softc *sc) 791{ 792 static const struct { 793 int reg; 794 uint16_t val; 795 } dspcode[] = { 796 { BRGPHY_MII_AUXCTL, 0x0c00 }, 797 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 798 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 799 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 800 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 801 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 802 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 803 { BRGPHY_MII_AUXCTL, 0x0400 }, 804 { 0, 0 }, 805 }; 806 int i; 807 808 for (i = 0; dspcode[i].reg != 0; i++) 809 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 810} 811 812static void 813brgphy_fixup_crc_bug(struct mii_softc *sc) 814{ 815 static const struct { 816 int reg; 817 uint16_t val; 818 } dspcode[] = { 819 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 820 { 0x1c, 0x8c68 }, 821 { 0x1c, 0x8d68 }, 822 { 0x1c, 0x8c68 }, 823 { 0, 0 }, 824 }; 825 int i; 826 827 for (i = 0; dspcode[i].reg != 0; i++) 828 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 829} 830 831static void 832brgphy_fixup_jitter_bug(struct mii_softc *sc) 833{ 834 static const struct { 835 int reg; 836 uint16_t val; 837 } dspcode[] = { 838 { BRGPHY_MII_AUXCTL, 0x0c00 }, 839 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 840 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 841 { BRGPHY_MII_AUXCTL, 0x0400 }, 842 { 0, 0 }, 843 }; 844 int i; 845 846 for (i = 0; dspcode[i].reg != 0; i++) 847 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 848} 849 850static void 851brgphy_fixup_disable_early_dac(struct mii_softc *sc) 852{ 853 uint32_t val; 854 855 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 856 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 857 val &= ~(1 << 8); 858 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 859 860} 861 862static void 863brgphy_ethernet_wirespeed(struct mii_softc *sc) 864{ 865 uint32_t val; 866 867 /* Enable Ethernet@WireSpeed. */ 868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 869 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 870 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 871} 872 873static void 874brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 875{ 876 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 877 uint32_t val; 878 879 /* Set or clear jumbo frame settings in the PHY. */ 880 if (mtu > ETHER_MAX_LEN) { 881 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 882 /* BCM5401 PHY cannot read-modify-write. */ 883 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 884 } else { 885 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 886 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 887 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 888 val | BRGPHY_AUXCTL_LONG_PKT); 889 } 890 891 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 892 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 893 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 894 } else { 895 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 896 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 897 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 898 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 899 900 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 901 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 902 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 903 } 904} 905 906static void 907brgphy_reset(struct mii_softc *sc) 908{ 909 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 910 struct bge_softc *bge_sc = NULL; 911 struct bce_softc *bce_sc = NULL; 912 struct ifnet *ifp; 913 int val; 914 915 /* Perform a standard PHY reset. */ 916 mii_phy_reset(sc); 917 918 /* Handle any PHY specific procedures following the reset. */ 919 switch (bsc->mii_oui) { 920 case MII_OUI_BROADCOM: 921 break; 922 case MII_OUI_xxBROADCOM: 923 switch (bsc->mii_model) { 924 case MII_MODEL_xxBROADCOM_BCM5400: 925 bcm5401_load_dspcode(sc); 926 break; 927 case MII_MODEL_xxBROADCOM_BCM5401: 928 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 929 bcm5401_load_dspcode(sc); 930 break; 931 case MII_MODEL_xxBROADCOM_BCM5411: 932 bcm5411_load_dspcode(sc); 933 break; 934 case MII_MODEL_xxBROADCOM_BCM54K2: 935 bcm54k2_load_dspcode(sc); 936 break; 937 } 938 break; 939 case MII_OUI_xxBROADCOM_ALT1: 940 case MII_OUI_xxBROADCOM_ALT2: 941 break; 942 } 943 944 ifp = sc->mii_pdata->mii_ifp; 945 946 /* Find the driver associated with this PHY. */ 947 if (strcmp(ifp->if_dname, "bge") == 0) { 948 bge_sc = ifp->if_softc; 949 } else if (strcmp(ifp->if_dname, "bce") == 0) { 950 bce_sc = ifp->if_softc; 951 } 952 953 if (bge_sc) { 954 /* Fix up various bugs */ 955 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 956 brgphy_fixup_5704_a0_bug(sc); 957 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 958 brgphy_fixup_adc_bug(sc); 959 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 960 brgphy_fixup_adjust_trim(sc); 961 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 962 brgphy_fixup_ber_bug(sc); 963 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 964 brgphy_fixup_crc_bug(sc); 965 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 966 brgphy_fixup_jitter_bug(sc); 967 968 brgphy_jumbo_settings(sc, ifp->if_mtu); 969 970 if (bge_sc->bge_phy_flags & BGE_PHY_WIRESPEED) 971 brgphy_ethernet_wirespeed(sc); 972 973 /* Enable Link LED on Dell boxes */ 974 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 975 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 976 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 977 ~BRGPHY_PHY_EXTCTL_3_LED); 978 } 979 980 /* Adjust output voltage (From Linux driver) */ 981 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 982 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 983 } else if (bce_sc) { 984 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 985 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 986 987 /* Store autoneg capabilities/results in digital block (Page 0) */ 988 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 989 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 990 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 991 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 992 993 /* Enable fiber mode and autodetection */ 994 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 995 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 996 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 997 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 998 999 /* Enable parallel detection */ 1000 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1001 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1002 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1003 1004 /* Advertise 2.5G support through next page during autoneg */ 1005 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1006 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1007 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1008 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1009 1010 /* Increase TX signal amplitude */ 1011 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1012 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1013 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1014 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1015 BRGPHY_5708S_TX_MISC_PG5); 1016 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1017 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1018 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1019 BRGPHY_5708S_DIG_PG0); 1020 } 1021 1022 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1023 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1024 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1025 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1026 BRGPHY_5708S_TX_MISC_PG5); 1027 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1028 bce_sc->bce_port_hw_cfg & 1029 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1030 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1031 BRGPHY_5708S_DIG_PG0); 1032 } 1033 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1034 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1035 1036 /* Select the SerDes Digital block of the AN MMD. */ 1037 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1038 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1039 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1040 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1041 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1042 1043 /* Select the Over 1G block of the AN MMD. */ 1044 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1045 1046 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1047 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1048 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1049 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1050 else 1051 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1052 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1053 1054 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1055 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1056 1057 /* Enable MRBE speed autoneg. */ 1058 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1059 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1060 BRGPHY_MRBE_MSG_PG5_NP_T2; 1061 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1062 1063 /* Select the Clause 73 User B0 block of the AN MMD. */ 1064 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1065 1066 /* Enable MRBE speed autoneg. */ 1067 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1068 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1069 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1070 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1071 1072 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1073 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1074 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1075 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1076 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1077 brgphy_fixup_disable_early_dac(sc); 1078 1079 brgphy_jumbo_settings(sc, ifp->if_mtu); 1080 brgphy_ethernet_wirespeed(sc); 1081 } else { 1082 brgphy_fixup_ber_bug(sc); 1083 brgphy_jumbo_settings(sc, ifp->if_mtu); 1084 brgphy_ethernet_wirespeed(sc); 1085 } 1086 } 1087} 1088