1155093Smarius/* $NetBSD: lancereg.h,v 1.12 2005/12/11 12:21:27 christos Exp $ */ 2155093Smarius 3155093Smarius/*- 4155093Smarius * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5155093Smarius * All rights reserved. 6155093Smarius * 7155093Smarius * This code is derived from software contributed to The NetBSD Foundation 8155093Smarius * by Charles M. Hannum and Jason R. Thorpe. 9155093Smarius * 10155093Smarius * Redistribution and use in source and binary forms, with or without 11155093Smarius * modification, are permitted provided that the following conditions 12155093Smarius * are met: 13155093Smarius * 1. Redistributions of source code must retain the above copyright 14155093Smarius * notice, this list of conditions and the following disclaimer. 15155093Smarius * 2. Redistributions in binary form must reproduce the above copyright 16155093Smarius * notice, this list of conditions and the following disclaimer in the 17155093Smarius * documentation and/or other materials provided with the distribution. 18155093Smarius * 19155093Smarius * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20155093Smarius * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21155093Smarius * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22155093Smarius * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23155093Smarius * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24155093Smarius * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25155093Smarius * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26155093Smarius * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27155093Smarius * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28155093Smarius * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29155093Smarius * POSSIBILITY OF SUCH DAMAGE. 30155093Smarius */ 31155093Smarius 32155093Smarius/*- 33155093Smarius * Copyright (c) 1992, 1993 34155093Smarius * The Regents of the University of California. All rights reserved. 35155093Smarius * 36155093Smarius * This code is derived from software contributed to Berkeley by 37155093Smarius * Ralph Campbell and Rick Macklem. 38155093Smarius * 39155093Smarius * Redistribution and use in source and binary forms, with or without 40155093Smarius * modification, are permitted provided that the following conditions 41155093Smarius * are met: 42155093Smarius * 1. Redistributions of source code must retain the above copyright 43155093Smarius * notice, this list of conditions and the following disclaimer. 44155093Smarius * 2. Redistributions in binary form must reproduce the above copyright 45155093Smarius * notice, this list of conditions and the following disclaimer in the 46155093Smarius * documentation and/or other materials provided with the distribution. 47155093Smarius * 3. Neither the name of the University nor the names of its contributors 48155093Smarius * may be used to endorse or promote products derived from this software 49155093Smarius * without specific prior written permission. 50155093Smarius * 51155093Smarius * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 52155093Smarius * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53155093Smarius * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54155093Smarius * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 55155093Smarius * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56155093Smarius * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57155093Smarius * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58155093Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59155093Smarius * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60155093Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61155093Smarius * SUCH DAMAGE. 62155093Smarius * 63155093Smarius * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93 64155093Smarius */ 65155093Smarius 66155093Smarius/* 67155093Smarius * Register description for the following Advanced Micro Devices 68155093Smarius * Ethernet chips: 69155093Smarius * 70155093Smarius * - Am7990 Local Area Network Controller for Ethernet (LANCE) 71155093Smarius * (and its descendent Am79c90 C-LANCE). 72155093Smarius * 73155093Smarius * - Am79c900 Integrated Local Area Communications Controller (ILACC) 74155093Smarius * 75155093Smarius * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA 76155093Smarius * 77155093Smarius * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller 78155093Smarius * for ISA 79155093Smarius * 80155093Smarius * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip 81155093Smarius * Ethernet Controller for ISA 82155093Smarius * 83155093Smarius * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller 84155093Smarius * (for VESA and 486 local busses) 85155093Smarius * 86155093Smarius * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 87155093Smarius * Local Bus 88155093Smarius * 89155093Smarius * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 90155093Smarius * for PCI Local Bus 91155093Smarius * 92155093Smarius * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 93155093Smarius * Ethernet Controller for PCI Local Bus 94155093Smarius * 95155093Smarius * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 96155093Smarius * with OnNow Support 97155093Smarius * 98155093Smarius * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 99155093Smarius * Ethernet Controller with Integrated PHY 100155093Smarius * 101155093Smarius * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home 102155093Smarius * Networking Controller. 103155093Smarius * 104155093Smarius * Initialization block, transmit descriptor, and receive descriptor 105155093Smarius * formats are described in two separate files: 106155093Smarius * 107155093Smarius * 16-bit software model (LANCE) am7990reg.h 108155093Smarius * 109155093Smarius * 32-bit software model (ILACC) am79900reg.h 110155093Smarius * 111155093Smarius * Note that the vast majority of the registers described in this file 112155093Smarius * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are 113155093Smarius * valid on the LANCE. 114155093Smarius */ 115155093Smarius 116155093Smarius/* $FreeBSD: releng/10.2/sys/dev/le/lancereg.h 263687 2014-03-24 13:48:04Z emaste $ */ 117155093Smarius 118155093Smarius#ifndef _DEV_LE_LANCEREG_H_ 119155093Smarius#define _DEV_LE_LANCEREG_H_ 120155093Smarius 121155093Smarius#define LEBLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 122155093Smarius/* LEMINSIZE should be ETHER_MIN_LEN when LE_MODE_DTCR is set. */ 123155093Smarius#define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN) 124155093Smarius 125155093Smarius#define LE_INITADDR(sc) (sc->sc_initaddr) 126155093Smarius#define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix)) 127155093Smarius#define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix)) 128155093Smarius#define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix)) 129155093Smarius#define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix)) 130155093Smarius 131155093Smarius/* 132155093Smarius * The byte count fields in descriptors are in two's complement. 133155093Smarius * This macro does the conversion for us on unsigned numbers. 134155093Smarius */ 135155093Smarius#define LE_BCNT(x) (~(x) + 1) 136155093Smarius 137155093Smarius/* 138155093Smarius * Control and Status Register addresses 139155093Smarius */ 140155093Smarius#define LE_CSR0 0x0000 /* Control and status register */ 141155093Smarius#define LE_CSR1 0x0001 /* low address of init block */ 142155093Smarius#define LE_CSR2 0x0002 /* high address of init block */ 143155093Smarius#define LE_CSR3 0x0003 /* Bus master and control */ 144155093Smarius#define LE_CSR4 0x0004 /* Test and features control */ 145155093Smarius#define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */ 146155093Smarius#define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */ 147155093Smarius#define LE_CSR7 0x0007 /* Extended control and interrupt 2 */ 148155093Smarius#define LE_CSR8 0x0008 /* Logical Address Filter 0 */ 149155093Smarius#define LE_CSR9 0x0009 /* Logical Address Filter 1 */ 150155093Smarius#define LE_CSR10 0x000a /* Logical Address Filter 2 */ 151155093Smarius#define LE_CSR11 0x000b /* Logical Address Filter 3 */ 152155093Smarius#define LE_CSR12 0x000c /* Physical Address 0 */ 153155093Smarius#define LE_CSR13 0x000d /* Physical Address 1 */ 154155093Smarius#define LE_CSR14 0x000e /* Physical Address 2 */ 155155093Smarius#define LE_CSR15 0x000f /* Mode */ 156155093Smarius#define LE_CSR16 0x0010 /* Initialization Block addr lower */ 157155093Smarius#define LE_CSR17 0x0011 /* Initialization Block addr upper */ 158155093Smarius#define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */ 159155093Smarius#define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */ 160155093Smarius#define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */ 161155093Smarius#define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */ 162155093Smarius#define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */ 163155093Smarius#define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */ 164155093Smarius#define LE_CSR24 0x0018 /* Base addr of Rx ring lower */ 165155093Smarius#define LE_CSR25 0x0019 /* Base addr of Rx ring upper */ 166155093Smarius#define LE_CSR26 0x001a /* Next Rx Desc addr lower */ 167155093Smarius#define LE_CSR27 0x001b /* Next Rx Desc addr upper */ 168155093Smarius#define LE_CSR28 0x001c /* Current Rx Desc addr lower */ 169155093Smarius#define LE_CSR29 0x001d /* Current Rx Desc addr upper */ 170155093Smarius#define LE_CSR30 0x001e /* Base addr of Tx ring lower */ 171155093Smarius#define LE_CSR31 0x001f /* Base addr of Tx ring upper */ 172155093Smarius#define LE_CSR32 0x0020 /* Next Tx Desc addr lower */ 173155093Smarius#define LE_CSR33 0x0021 /* Next Tx Desc addr upper */ 174155093Smarius#define LE_CSR34 0x0022 /* Current Tx Desc addr lower */ 175155093Smarius#define LE_CSR35 0x0023 /* Current Tx Desc addr upper */ 176155093Smarius#define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */ 177155093Smarius#define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */ 178155093Smarius#define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */ 179155093Smarius#define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */ 180155093Smarius#define LE_CSR40 0x0028 /* Current Rx Byte Count */ 181155093Smarius#define LE_CSR41 0x0029 /* Current Rx Status */ 182155093Smarius#define LE_CSR42 0x002a /* Current Tx Byte Count */ 183155093Smarius#define LE_CSR43 0x002b /* Current Tx Status */ 184155093Smarius#define LE_CSR44 0x002c /* Next Rx Byte Count */ 185155093Smarius#define LE_CSR45 0x002d /* Next Rx Status */ 186155093Smarius#define LE_CSR46 0x002e /* Tx Poll Time Counter */ 187155093Smarius#define LE_CSR47 0x002f /* Tx Polling Interval */ 188155093Smarius#define LE_CSR48 0x0030 /* Rx Poll Time Counter */ 189155093Smarius#define LE_CSR49 0x0031 /* Rx Polling Interval */ 190155093Smarius#define LE_CSR58 0x003a /* Software Style */ 191155093Smarius#define LE_CSR60 0x003c /* Previous Tx Desc addr lower */ 192155093Smarius#define LE_CSR61 0x003d /* Previous Tx Desc addr upper */ 193155093Smarius#define LE_CSR62 0x003e /* Previous Tx Byte Count */ 194155093Smarius#define LE_CSR63 0x003f /* Previous Tx Status */ 195155093Smarius#define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */ 196155093Smarius#define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */ 197155093Smarius#define LE_CSR66 0x0042 /* Next Tx Byte Count */ 198155093Smarius#define LE_CSR67 0x0043 /* Next Tx Status */ 199155093Smarius#define LE_CSR72 0x0048 /* Receive Ring Counter */ 200155093Smarius#define LE_CSR74 0x004a /* Transmit Ring Counter */ 201155093Smarius#define LE_CSR76 0x004c /* Receive Ring Length */ 202155093Smarius#define LE_CSR78 0x004e /* Transmit Ring Length */ 203155093Smarius#define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO 204155093Smarius Threshold Control */ 205155093Smarius#define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */ 206155093Smarius#define LE_CSR84 0x0054 /* DMA addr register lower */ 207155093Smarius#define LE_CSR85 0x0055 /* DMA addr register upper */ 208155093Smarius#define LE_CSR86 0x0056 /* Buffer Byte Counter */ 209155093Smarius#define LE_CSR88 0x0058 /* Chip ID Register lower */ 210155093Smarius#define LE_CSR89 0x0059 /* Chip ID Register upper */ 211155093Smarius#define LE_CSR92 0x005c /* Ring Length Conversion */ 212155093Smarius#define LE_CSR100 0x0064 /* Bus Timeout */ 213155093Smarius#define LE_CSR112 0x0070 /* Missed Frame Count */ 214155093Smarius#define LE_CSR114 0x0072 /* Receive Collision Count */ 215155093Smarius#define LE_CSR116 0x0074 /* OnNow Power Mode Register */ 216155093Smarius#define LE_CSR122 0x007a /* Advanced Feature Control */ 217155093Smarius#define LE_CSR124 0x007c /* Test Register 1 */ 218155093Smarius#define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */ 219155093Smarius 220155093Smarius/* 221155093Smarius * Bus Configuration Register addresses 222155093Smarius */ 223155093Smarius#define LE_BCR0 0x0000 /* Master Mode Read Active */ 224155093Smarius#define LE_BCR1 0x0001 /* Master Mode Write Active */ 225155093Smarius#define LE_BCR2 0x0002 /* Misc. Configuration */ 226155093Smarius#define LE_BCR4 0x0004 /* LED0 Status */ 227155093Smarius#define LE_BCR5 0x0005 /* LED1 Status */ 228155093Smarius#define LE_BCR6 0x0006 /* LED2 Status */ 229155093Smarius#define LE_BCR7 0x0007 /* LED3 Status */ 230155093Smarius#define LE_BCR9 0x0009 /* Full-duplex Control */ 231155093Smarius#define LE_BCR16 0x0010 /* I/O Base Address lower */ 232155093Smarius#define LE_BCR17 0x0011 /* I/O Base Address upper */ 233155093Smarius#define LE_BCR18 0x0012 /* Burst and Bus Control Register */ 234155093Smarius#define LE_BCR19 0x0013 /* EEPROM Control and Status */ 235155093Smarius#define LE_BCR20 0x0014 /* Software Style */ 236155093Smarius#define LE_BCR22 0x0016 /* PCI Latency Register */ 237155093Smarius#define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */ 238155093Smarius#define LE_BCR24 0x0018 /* PCI Subsystem ID */ 239155093Smarius#define LE_BCR25 0x0019 /* SRAM Size Register */ 240155093Smarius#define LE_BCR26 0x001a /* SRAM Boundary Register */ 241155093Smarius#define LE_BCR27 0x001b /* SRAM Interface Control Register */ 242155093Smarius#define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */ 243155093Smarius#define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */ 244155093Smarius#define LE_BCR30 0x001e /* Exp. Bus Data Port */ 245155093Smarius#define LE_BCR31 0x001f /* Software Timer Register */ 246155093Smarius#define LE_BCR32 0x0020 /* PHY Control and Status Register */ 247155093Smarius#define LE_BCR33 0x0021 /* PHY Address Register */ 248155093Smarius#define LE_BCR34 0x0022 /* PHY Management Data Register */ 249155093Smarius#define LE_BCR35 0x0023 /* PCI Vendor ID Register */ 250155093Smarius#define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */ 251155093Smarius#define LE_BCR37 0x0025 /* PCI DATA0 Alias */ 252155093Smarius#define LE_BCR38 0x0026 /* PCI DATA1 Alias */ 253155093Smarius#define LE_BCR39 0x0027 /* PCI DATA2 Alias */ 254155093Smarius#define LE_BCR40 0x0028 /* PCI DATA3 Alias */ 255155093Smarius#define LE_BCR41 0x0029 /* PCI DATA4 Alias */ 256155093Smarius#define LE_BCR42 0x002a /* PCI DATA5 Alias */ 257155093Smarius#define LE_BCR43 0x002b /* PCI DATA6 Alias */ 258155093Smarius#define LE_BCR44 0x002c /* PCI DATA7 Alias */ 259155093Smarius#define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */ 260155093Smarius#define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */ 261155093Smarius#define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */ 262155093Smarius#define LE_BCR48 0x0030 /* LED4 Status */ 263155093Smarius#define LE_BCR49 0x0031 /* PHY Select */ 264155093Smarius 265155093Smarius/* Control and status register 0 (csr0) */ 266155093Smarius#define LE_C0_ERR 0x8000 /* error summary */ 267155093Smarius#define LE_C0_BABL 0x4000 /* transmitter timeout error */ 268155093Smarius#define LE_C0_CERR 0x2000 /* collision */ 269155093Smarius#define LE_C0_MISS 0x1000 /* missed a packet */ 270155093Smarius#define LE_C0_MERR 0x0800 /* memory error */ 271155093Smarius#define LE_C0_RINT 0x0400 /* receiver interrupt */ 272155093Smarius#define LE_C0_TINT 0x0200 /* transmitter interrupt */ 273155093Smarius#define LE_C0_IDON 0x0100 /* initialization done */ 274155093Smarius#define LE_C0_INTR 0x0080 /* interrupt condition */ 275155093Smarius#define LE_C0_INEA 0x0040 /* interrupt enable */ 276155093Smarius#define LE_C0_RXON 0x0020 /* receiver on */ 277155093Smarius#define LE_C0_TXON 0x0010 /* transmitter on */ 278155093Smarius#define LE_C0_TDMD 0x0008 /* transmit demand */ 279155093Smarius#define LE_C0_STOP 0x0004 /* disable all external activity */ 280155093Smarius#define LE_C0_STRT 0x0002 /* enable external activity */ 281155093Smarius#define LE_C0_INIT 0x0001 /* begin initialization */ 282155093Smarius 283155093Smarius#define LE_C0_BITS \ 284155093Smarius "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 285155093Smarius\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 286155093Smarius 287155093Smarius/* Control and status register 3 (csr3) */ 288155093Smarius#define LE_C3_BABLM 0x4000 /* babble mask */ 289155093Smarius#define LE_C3_MISSM 0x1000 /* missed frame mask */ 290155093Smarius#define LE_C3_MERRM 0x0800 /* memory error mask */ 291155093Smarius#define LE_C3_RINTM 0x0400 /* receive interrupt mask */ 292155093Smarius#define LE_C3_TINTM 0x0200 /* transmit interrupt mask */ 293155093Smarius#define LE_C3_IDONM 0x0100 /* initialization done mask */ 294155093Smarius#define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */ 295155093Smarius#define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */ 296155093Smarius#define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */ 297155093Smarius#define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */ 298155093Smarius#define LE_C3_BSWP 0x0004 /* byte swap */ 299155093Smarius#define LE_C3_ACON 0x0002 /* ALE control, eh? */ 300155093Smarius#define LE_C3_BCON 0x0001 /* byte control */ 301155093Smarius 302155093Smarius/* Control and status register 4 (csr4) */ 303155093Smarius#define LE_C4_EN124 0x8000 /* enable CSR124 */ 304155093Smarius#define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */ 305155093Smarius#define LE_C4_TIMER 0x2000 /* enable bus activity timer */ 306155093Smarius#define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */ 307155093Smarius#define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */ 308155093Smarius#define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */ 309155093Smarius#define LE_C4_MFCO 0x0200 /* missed frame counter overflow */ 310155093Smarius#define LE_C4_MFCOM 0x0100 /* missed frame coutner overflow mask */ 311155093Smarius#define LE_C4_UINTCMD 0x0080 /* user interrupt command */ 312155093Smarius#define LE_C4_UINT 0x0040 /* user interrupt */ 313155093Smarius#define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */ 314155093Smarius#define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow 315155093Smarius mask */ 316155093Smarius#define LE_C4_TXSTRT 0x0008 /* transmit start status */ 317155093Smarius#define LE_C4_TXSTRTM 0x0004 /* transmit start mask */ 318155093Smarius 319155093Smarius/* Control and status register 5 (csr5) */ 320155093Smarius#define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */ 321155093Smarius#define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */ 322155093Smarius#define LE_C5_SINT 0x0800 /* system interrupt */ 323155093Smarius#define LE_C5_SINTE 0x0400 /* system interrupt enable */ 324155093Smarius#define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */ 325155093Smarius#define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */ 326155093Smarius#define LE_C5_MPPLBA 0x0020 /* magic packet physical logical 327155093Smarius broadcast accept */ 328155093Smarius#define LE_C5_MPINT 0x0010 /* magic packet interrupt */ 329155093Smarius#define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */ 330155093Smarius#define LE_C5_MPEN 0x0004 /* magic packet enable */ 331155093Smarius#define LE_C5_MPMODE 0x0002 /* magic packet mode */ 332155093Smarius#define LE_C5_SPND 0x0001 /* suspend */ 333155093Smarius 334155093Smarius/* Control and status register 6 (csr6) */ 335155093Smarius#define LE_C6_TLEN 0xf000 /* TLEN from init block */ 336155093Smarius#define LE_C6_RLEN 0x0f00 /* RLEN from init block */ 337155093Smarius 338155093Smarius/* Control and status register 7 (csr7) */ 339155093Smarius#define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */ 340155093Smarius#define LE_C7_RDMD 0x2000 /* receive demand */ 341155093Smarius#define LE_C7_RDXPOLL 0x1000 /* receive disable polling */ 342155093Smarius#define LE_C7_STINT 0x0800 /* software timer interrupt */ 343155093Smarius#define LE_C7_STINTE 0x0400 /* software timer interrupt enable */ 344155093Smarius#define LE_C7_MREINT 0x0200 /* PHY management read error intr */ 345155093Smarius#define LE_C7_MREINTE 0x0100 /* PHY management read error intr 346155093Smarius enable */ 347155093Smarius#define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */ 348155093Smarius#define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr 349155093Smarius enable */ 350155093Smarius#define LE_C7_MCCINT 0x0020 /* PHY management command complete 351155093Smarius interrupt */ 352155093Smarius#define LE_C7_MCCINTE 0x0010 /* PHY management command complete 353155093Smarius interrupt enable */ 354155093Smarius#define LE_C7_MCCIINT 0x0008 /* PHY management command complete 355155093Smarius internal interrupt */ 356155093Smarius#define LE_C7_MCCIINTE 0x0004 /* PHY management command complete 357155093Smarius internal interrupt enable */ 358155093Smarius#define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition 359155093Smarius interrupt */ 360155093Smarius#define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition 361155093Smarius interrupt enable */ 362155093Smarius 363155093Smarius/* Control and status register 15 (csr15) */ 364155093Smarius#define LE_C15_PROM 0x8000 /* promiscuous mode */ 365155093Smarius#define LE_C15_DRCVBC 0x4000 /* disable Rx of broadcast */ 366155093Smarius#define LE_C15_DRCVPA 0x2000 /* disable Rx of physical address */ 367155093Smarius#define LE_C15_DLNKTST 0x1000 /* disable link status */ 368155093Smarius#define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */ 369155093Smarius#define LE_C15_MENDECL 0x0400 /* MENDEC Loopback mode */ 370155093Smarius#define LE_C15_LRT 0x0200 /* low receive threshold (TMAU) */ 371155093Smarius#define LE_C15_TSEL 0x0200 /* transmit mode select (AUI) */ 372155093Smarius#define LE_C15_PORTSEL(x) ((x) << 7) /* port select */ 373155093Smarius#define LE_C15_INTL 0x0040 /* internal loopback */ 374155093Smarius#define LE_C15_DRTY 0x0020 /* disable retry */ 375155093Smarius#define LE_C15_FCOLL 0x0010 /* force collision */ 376155093Smarius#define LE_C15_DXMTFCS 0x0008 /* disable Tx FCS (ADD_FCS overrides) */ 377155093Smarius#define LE_C15_LOOP 0x0004 /* loopback enable */ 378155093Smarius#define LE_C15_DTX 0x0002 /* disable transmit */ 379155093Smarius#define LE_C15_DRX 0x0001 /* disable receiver */ 380155093Smarius 381155093Smarius#define LE_PORTSEL_AUI 0 382155093Smarius#define LE_PORTSEL_10T 1 383155093Smarius#define LE_PORTSEL_GPSI 2 384155093Smarius#define LE_PORTSEL_MII 3 385155093Smarius#define LE_PORTSEL_MASK 3 386155093Smarius 387155093Smarius/* control and status register 80 (csr80) */ 388155093Smarius#define LE_C80_RCVFW(x) ((x) << 12) /* Receive FIFO Watermark */ 389155093Smarius#define LE_C80_RCVFW_MAX 3 390155093Smarius#define LE_C80_XMTSP(x) ((x) << 10) /* Transmit Start Point */ 391155093Smarius#define LE_C80_XMTSP_MAX 3 392155093Smarius#define LE_C80_XMTFW(x) ((x) << 8) /* Transmit FIFO Watermark */ 393155093Smarius#define LE_C80_XMTFW_MAX 3 394155093Smarius#define LE_C80_DMATC 0x00ff /* DMA transfer counter */ 395155093Smarius 396155093Smarius/* control and status register 116 (csr116) */ 397155093Smarius#define LE_C116_PME_EN_OVR 0x0400 /* PME_EN overwrite */ 398155093Smarius#define LE_C116_LCDET 0x0200 /* link change detected */ 399155093Smarius#define LE_C116_LCMODE 0x0100 /* link change wakeup mode */ 400155093Smarius#define LE_C116_PMAT 0x0080 /* pattern matched */ 401155093Smarius#define LE_C116_EMPPLBA 0x0040 /* magic packet physical logical 402155093Smarius broadcast accept */ 403155093Smarius#define LE_C116_MPMAT 0x0020 /* magic packet match */ 404155093Smarius#define LE_C116_MPPEN 0x0010 /* magic packet pin enable */ 405155093Smarius#define LE_C116_RST_POL 0x0001 /* PHY_RST pin polarity */ 406155093Smarius 407155093Smarius/* control and status register 122 (csr122) */ 408155093Smarius#define LE_C122_RCVALGN 0x0001 /* receive packet align */ 409155093Smarius 410155093Smarius/* control and status register 124 (csr124) */ 411155093Smarius#define LE_C124_RPA 0x0008 /* runt packet accept */ 412155093Smarius 413155093Smarius/* control and status register 125 (csr125) */ 414155093Smarius#define LE_C125_IPG 0xff00 /* inter-packet gap */ 415155093Smarius#define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */ 416155093Smarius 417155093Smarius/* bus configuration register 0 (bcr0) */ 418155093Smarius#define LE_B0_MSRDA 0xffff /* reserved locations */ 419155093Smarius 420155093Smarius/* bus configuration register 1 (bcr1) */ 421155093Smarius#define LE_B1_MSWRA 0xffff /* reserved locations */ 422155093Smarius 423155093Smarius/* bus configuration register 2 (bcr2) */ 424155093Smarius#define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */ 425155093Smarius#define LE_B2_LEDPE 0x1000 /* LED program enable */ 426155093Smarius#define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */ 427155093Smarius#define LE_B2_INTLEVEL 0x0080 /* 1 == edge triggered */ 428155093Smarius#define LE_B2_DXCVRCTL 0x0020 /* DXCVR control */ 429155093Smarius#define LE_B2_DXCVRPOL 0x0010 /* DXCVR polarity */ 430155093Smarius#define LE_B2_EADISEL 0x0008 /* EADI select */ 431155093Smarius#define LE_B2_AWAKE 0x0004 /* power saving mode select */ 432155093Smarius#define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */ 433155093Smarius#define LE_B2_XMAUSEL 0x0001 /* reserved location */ 434155093Smarius 435155093Smarius/* bus configuration register 4 (bcr4) */ 436155093Smarius/* bus configuration register 5 (bcr5) */ 437155093Smarius/* bus configuration register 6 (bcr6) */ 438155093Smarius/* bus configuration register 7 (bcr7) */ 439155093Smarius/* bus configuration register 48 (bcr48) */ 440155093Smarius#define LE_B4_LEDOUT 0x8000 /* LED output active */ 441155093Smarius#define LE_B4_LEDPOL 0x4000 /* LED polarity */ 442155093Smarius#define LE_B4_LEDDIS 0x2000 /* LED disable */ 443155093Smarius#define LE_B4_100E 0x1000 /* 100Mb/s enable */ 444155093Smarius#define LE_B4_MPSE 0x0200 /* magic packet status enable */ 445155093Smarius#define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */ 446155093Smarius#define LE_B4_PSE 0x0080 /* pulse stretcher enable */ 447155093Smarius#define LE_B4_LNKSE 0x0040 /* link status enable */ 448155093Smarius#define LE_B4_RCVME 0x0020 /* receive match status enable */ 449155093Smarius#define LE_B4_XMTE 0x0010 /* transmit status enable */ 450155093Smarius#define LE_B4_POWER 0x0008 /* power enable */ 451155093Smarius#define LE_B4_RCVE 0x0004 /* receive status enable */ 452155093Smarius#define LE_B4_SPEED 0x0002 /* high speed enable */ 453155093Smarius#define LE_B4_COLE 0x0001 /* collision status enable */ 454155093Smarius 455155093Smarius/* bus configuration register 9 (bcr9) */ 456155093Smarius#define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept 457155093Smarius disable */ 458155093Smarius#define LE_B9_AUIFD 0x0002 /* AUI full-duplex */ 459155093Smarius#define LE_B9_FDEN 0x0001 /* full-duplex enable */ 460155093Smarius 461155093Smarius/* bus configuration register 18 (bcr18) */ 462155093Smarius#define LE_B18_ROMTMG 0xf000 /* expansion rom timing */ 463155093Smarius#define LE_B18_NOUFLO 0x0800 /* no underflow on transmit */ 464155093Smarius#define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */ 465155093Smarius#define LE_B18_EXTREQ 0x0100 /* extended request */ 466155093Smarius#define LE_B18_DWIO 0x0080 /* double-word I/O */ 467155093Smarius#define LE_B18_BREADE 0x0040 /* burst read enable */ 468155093Smarius#define LE_B18_BWRITE 0x0020 /* burst write enable */ 469155093Smarius#define LE_B18_PHYSEL1 0x0010 /* PHYSEL 1 */ 470155093Smarius#define LE_B18_PHYSEL0 0x0008 /* PHYSEL 0 */ 471155093Smarius /* 00 ex ROM/Flash */ 472155093Smarius /* 01 EADI/MII snoop */ 473155093Smarius /* 10 reserved */ 474155093Smarius /* 11 reserved */ 475155093Smarius#define LE_B18_LINBC 0x0007 /* reserved locations */ 476155093Smarius 477155093Smarius/* bus configuration register 19 (bcr19) */ 478155093Smarius#define LE_B19_PVALID 0x8000 /* EEPROM status valid */ 479155093Smarius#define LE_B19_PREAD 0x4000 /* EEPROM read command */ 480155093Smarius#define LE_B19_EEDET 0x2000 /* EEPROM detect */ 481155093Smarius#define LE_B19_EEN 0x0010 /* EEPROM port enable */ 482155093Smarius#define LE_B19_ECS 0x0004 /* EEPROM chip select */ 483155093Smarius#define LE_B19_ESK 0x0002 /* EEPROM serial clock */ 484155093Smarius#define LE_B19_EDI 0x0001 /* EEPROM data in */ 485155093Smarius#define LE_B19_EDO 0x0001 /* EEPROM data out */ 486155093Smarius 487155093Smarius/* bus configuration register 20 (bcr20) */ 488155093Smarius#define LE_B20_APERREN 0x0400 /* Advanced parity error handling */ 489155093Smarius#define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */ 490155093Smarius#define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */ 491155093Smarius#define LE_B20_SSTYLE 0x0007 /* Software Style */ 492155093Smarius#define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */ 493158663Smarius#define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */ 494155093Smarius#define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */ 495155093Smarius#define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */ 496155093Smarius 497155093Smarius/* bus configuration register 25 (bcr25) */ 498155093Smarius#define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */ 499155093Smarius 500155093Smarius/* bus configuration register 26 (bcr26) */ 501155093Smarius#define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */ 502155093Smarius 503155093Smarius/* bus configuration register 27 (bcr27) */ 504155093Smarius#define LE_B27_PTRTST 0x8000 /* reserved for manuf. tests */ 505155093Smarius#define LE_B27_LOLATRX 0x4000 /* low latency receive */ 506155093Smarius#define LE_B27_EBCS 0x0038 /* expansion bus clock source */ 507155093Smarius /* 000 CLK pin */ 508155093Smarius /* 001 time base clock */ 509155093Smarius /* 010 EBCLK pin */ 510155093Smarius /* 011 reserved */ 511155093Smarius /* 1xx reserved */ 512155093Smarius#define LE_B27_CLK_FAC 0x0007 /* clock factor */ 513155093Smarius /* 000 1 */ 514155093Smarius /* 001 1/2 */ 515155093Smarius /* 010 reserved */ 516155093Smarius /* 011 1/4 */ 517155093Smarius /* 1xx reserved */ 518155093Smarius 519155093Smarius/* bus configuration register 28 (bcr28) */ 520155093Smarius#define LE_B28_EADDRL 0xffff /* expansion port address lower */ 521155093Smarius 522155093Smarius/* bus configuration register 29 (bcr29) */ 523155093Smarius#define LE_B29_FLASH 0x8000 /* flash access */ 524155093Smarius#define LE_B29_LAAINC 0x4000 /* lower address auto increment */ 525155093Smarius#define LE_B29_EPADDRU 0x0007 /* expansion port address upper */ 526155093Smarius 527155093Smarius/* bus configuration register 30 (bcr30) */ 528155093Smarius#define LE_B30_EBDATA 0xffff /* expansion bus data port */ 529155093Smarius 530155093Smarius/* bus configuration register 31 (bcr31) */ 531155093Smarius#define LE_B31_STVAL 0xffff /* software timer value */ 532155093Smarius 533155093Smarius/* bus configuration register 32 (bcr32) */ 534155093Smarius#define LE_B32_ANTST 0x8000 /* reserved for manuf. tests */ 535155093Smarius#define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */ 536155093Smarius#define LE_B32_FMDC 0x3000 /* fast management data clock */ 537155093Smarius#define LE_B32_APEP 0x0800 /* auto-poll PHY */ 538155093Smarius#define LE_B32_APDW 0x0700 /* auto-poll dwell time */ 539155093Smarius#define LE_B32_DANAS 0x0080 /* disable autonegotiation */ 540155093Smarius#define LE_B32_XPHYRST 0x0040 /* PHY reset */ 541155093Smarius#define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */ 542155093Smarius#define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */ 543155093Smarius#define LE_B32_XPHYSP 0x0008 /* PHY speed */ 544155093Smarius#define LE_B32_MIIILP 0x0002 /* MII internal loopback */ 545155093Smarius 546155093Smarius/* bus configuration register 33 (bcr33) */ 547155093Smarius#define LE_B33_SHADOW 0x8000 /* shadow enable */ 548155093Smarius#define LE_B33_MII_SEL 0x4000 /* MII selected */ 549155093Smarius#define LE_B33_ACOMP 0x2000 /* internal PHY autonegotiation comp */ 550155093Smarius#define LE_B33_LINK 0x1000 /* link status */ 551155093Smarius#define LE_B33_FDX 0x0800 /* full-duplex */ 552155093Smarius#define LE_B33_SPEED 0x0400 /* 1 == high speed */ 553155093Smarius#define LE_B33_PHYAD 0x03e0 /* PHY address */ 554155093Smarius#define PHYAD_SHIFT 5 555155093Smarius#define LE_B33_REGAD 0x001f /* register address */ 556155093Smarius 557155093Smarius/* bus configuration register 34 (bcr34) */ 558155093Smarius#define LE_B34_MIIMD 0xffff /* MII data */ 559155093Smarius 560155093Smarius/* bus configuration register 49 (bcr49) */ 561155093Smarius#define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */ 562155093Smarius#define LE_B49_PHYSEL_D 0x0300 /* PHY_SEL_Default */ 563155093Smarius#define LE_B49_PHYSEL_L 0x0010 /* PHY_SEL_Lock */ 564155093Smarius#define LE_B49_PHYSEL 0x0003 /* PHYSEL */ 565155093Smarius /* 00 10baseT PHY */ 566155093Smarius /* 01 HomePNA PHY */ 567155093Smarius /* 10 external PHY */ 568155093Smarius /* 11 reserved */ 569155093Smarius 570155093Smarius/* Initialization block (mode) */ 571155093Smarius#define LE_MODE_PROM 0x8000 /* promiscuous mode */ 572155093Smarius/* 0x7f80 reserved, must be zero */ 573155093Smarius/* 0x4000 - 0x0080 are not available on LANCE 7990. */ 574155093Smarius#define LE_MODE_DRCVBC 0x4000 /* disable receive brodcast */ 575155093Smarius#define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */ 576155093Smarius#define LE_MODE_DLNKTST 0x1000 /* disable link status */ 577155093Smarius#define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */ 578155093Smarius#define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */ 579155093Smarius#define LE_MODE_LRTTSEL 0x0200 /* lower receive threshold / 580155093Smarius transmit mode selection */ 581155093Smarius#define LE_MODE_PSEL1 0x0100 /* port selection bit1 */ 582155093Smarius#define LE_MODE_PSEL0 0x0080 /* port selection bit0 */ 583155093Smarius#define LE_MODE_INTL 0x0040 /* internal loopback */ 584155093Smarius#define LE_MODE_DRTY 0x0020 /* disable retry */ 585155093Smarius#define LE_MODE_COLL 0x0010 /* force a collision */ 586155093Smarius#define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 587155093Smarius#define LE_MODE_LOOP 0x0004 /* loopback mode */ 588155093Smarius#define LE_MODE_DTX 0x0002 /* disable transmitter */ 589155093Smarius#define LE_MODE_DRX 0x0001 /* disable receiver */ 590155093Smarius#define LE_MODE_NORMAL 0 /* none of the above */ 591155093Smarius 592155093Smarius/* 593155093Smarius * Chip ID (CSR88 IDL, CSR89 IDU) values for various AMD PCnet parts 594155093Smarius */ 595155093Smarius#define CHIPID_MANFID(x) (((x) >> 1) & 0x3ff) 596155093Smarius#define CHIPID_PARTID(x) (((x) >> 12) & 0xffff) 597155093Smarius#define CHIPID_VER(x) (((x) >> 28) & 0x7) 598155093Smarius 599155093Smarius#define PARTID_Am79c960 0x0003 600155093Smarius#define PARTID_Am79c961 0x2260 601155093Smarius#define PARTID_Am79c961A 0x2261 602155093Smarius#define PARTID_Am79c965 0x2430 /* yes, these... */ 603155093Smarius#define PARTID_Am79c970 0x2430 /* ...are the same */ 604155093Smarius#define PARTID_Am79c970A 0x2621 605155093Smarius#define PARTID_Am79c971 0x2623 606155093Smarius#define PARTID_Am79c972 0x2624 607155093Smarius#define PARTID_Am79c973 0x2625 608155093Smarius#define PARTID_Am79c978 0x2626 609155093Smarius#define PARTID_Am79c975 0x2627 610155093Smarius#define PARTID_Am79c976 0x2628 611155093Smarius 612155093Smarius#endif /* !_DEV_LE_LANCEREG_H_ */ 613