ixgbe.h revision 243718
1277323Sdim/****************************************************************************** 2277323Sdim 3277323Sdim Copyright (c) 2001-2012, Intel Corporation 4277323Sdim All rights reserved. 5277323Sdim 6277323Sdim Redistribution and use in source and binary forms, with or without 7277323Sdim modification, are permitted provided that the following conditions are met: 8277323Sdim 9277323Sdim 1. Redistributions of source code must retain the above copyright notice, 10277323Sdim this list of conditions and the following disclaimer. 11277323Sdim 12277323Sdim 2. Redistributions in binary form must reproduce the above copyright 13277323Sdim notice, this list of conditions and the following disclaimer in the 14277323Sdim documentation and/or other materials provided with the distribution. 15277323Sdim 16277323Sdim 3. Neither the name of the Intel Corporation nor the names of its 17277323Sdim contributors may be used to endorse or promote products derived from 18277323Sdim this software without specific prior written permission. 19277323Sdim 20277323Sdim THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21277323Sdim AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22277323Sdim IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23277323Sdim ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24277323Sdim LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25277323Sdim CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26277323Sdim SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27277323Sdim INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28277323Sdim CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29277323Sdim ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30277323Sdim POSSIBILITY OF SUCH DAMAGE. 31277323Sdim 32277323Sdim******************************************************************************/ 33277323Sdim/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 243718 2012-11-30 22:41:32Z jfv $*/ 34288943Sdim 35288943Sdim 36277323Sdim#ifndef _IXGBE_H_ 37277323Sdim#define _IXGBE_H_ 38277323Sdim 39277323Sdim 40288943Sdim#include <sys/param.h> 41288943Sdim#include <sys/systm.h> 42288943Sdim#if __FreeBSD_version >= 800000 43288943Sdim#include <sys/buf_ring.h> 44288943Sdim#endif 45288943Sdim#include <sys/mbuf.h> 46288943Sdim#include <sys/protosw.h> 47277323Sdim#include <sys/socket.h> 48277323Sdim#include <sys/malloc.h> 49277323Sdim#include <sys/kernel.h> 50277323Sdim#include <sys/module.h> 51277323Sdim#include <sys/sockio.h> 52277323Sdim 53277323Sdim#include <net/if.h> 54277323Sdim#include <net/if_arp.h> 55277323Sdim#include <net/bpf.h> 56277323Sdim#include <net/ethernet.h> 57277323Sdim#include <net/if_dl.h> 58277323Sdim#include <net/if_media.h> 59277323Sdim 60277323Sdim#include <net/bpf.h> 61277323Sdim#include <net/if_types.h> 62277323Sdim#include <net/if_vlan_var.h> 63277323Sdim 64277323Sdim#include <netinet/in_systm.h> 65277323Sdim#include <netinet/in.h> 66277323Sdim#include <netinet/if_ether.h> 67277323Sdim#include <netinet/ip.h> 68288943Sdim#include <netinet/ip6.h> 69288943Sdim#include <netinet/tcp.h> 70288943Sdim#include <netinet/tcp_lro.h> 71277323Sdim#include <netinet/udp.h> 72277323Sdim 73277323Sdim#include <machine/in_cksum.h> 74277323Sdim 75288943Sdim#include <sys/bus.h> 76288943Sdim#include <machine/bus.h> 77288943Sdim#include <sys/rman.h> 78288943Sdim#include <machine/resource.h> 79288943Sdim#include <vm/vm.h> 80288943Sdim#include <vm/pmap.h> 81288943Sdim#include <machine/clock.h> 82288943Sdim#include <dev/pci/pcivar.h> 83277323Sdim#include <dev/pci/pcireg.h> 84277323Sdim#include <sys/proc.h> 85277323Sdim#include <sys/sysctl.h> 86277323Sdim#include <sys/endian.h> 87277323Sdim#include <sys/taskqueue.h> 88277323Sdim#include <sys/pcpu.h> 89277323Sdim#include <sys/smp.h> 90277323Sdim#include <machine/smp.h> 91277323Sdim 92277323Sdim#ifdef IXGBE_IEEE1588 93277323Sdim#include <sys/ieee1588.h> 94277323Sdim#endif 95277323Sdim 96277323Sdim#include "ixgbe_api.h" 97277323Sdim 98288943Sdim/* Tunables */ 99288943Sdim 100277323Sdim/* 101277323Sdim * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102277323Sdim * number of transmit descriptors allocated by the driver. Increasing this 103288943Sdim * value allows the driver to queue more transmits. Each descriptor is 16 104288943Sdim * bytes. Performance tests have show the 2K value to be optimal for top 105288943Sdim * performance. 106288943Sdim */ 107288943Sdim#define DEFAULT_TXD 1024 108288943Sdim#define PERFORM_TXD 2048 109277323Sdim#define MAX_TXD 4096 110277323Sdim#define MIN_TXD 64 111277323Sdim 112277323Sdim/* 113277323Sdim * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114277323Sdim * number of receive descriptors allocated for each RX queue. Increasing this 115277323Sdim * value allows the driver to buffer more incoming packets. Each descriptor 116277323Sdim * is 16 bytes. A receive buffer is also allocated for each descriptor. 117277323Sdim * 118277323Sdim * Note: with 8 rings and a dual port card, it is possible to bump up 119277323Sdim * against the system mbuf pool limit, you can tune nmbclusters 120277323Sdim * to adjust for this. 121277323Sdim */ 122277323Sdim#define DEFAULT_RXD 1024 123288943Sdim#define PERFORM_RXD 2048 124288943Sdim#define MAX_RXD 4096 125277323Sdim#define MIN_RXD 64 126277323Sdim 127277323Sdim/* Alignment for rings */ 128277323Sdim#define DBA_ALIGN 128 129277323Sdim 130277323Sdim/* 131277323Sdim * This parameter controls the maximum no of times the driver will loop in 132277323Sdim * the isr. Minimum Value = 1 133277323Sdim */ 134277323Sdim#define MAX_LOOP 10 135277323Sdim 136277323Sdim/* 137277323Sdim * This is the max watchdog interval, ie. the time that can 138277323Sdim * pass between any two TX clean operations, such only happening 139277323Sdim * when the TX hardware is functioning. 140277323Sdim */ 141277323Sdim#define IXGBE_WATCHDOG (10 * hz) 142277323Sdim 143277323Sdim/* 144277323Sdim * This parameters control when the driver calls the routine to reclaim 145288943Sdim * transmit descriptors. 146277323Sdim */ 147288943Sdim#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148288943Sdim#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149288943Sdim 150288943Sdim#define IXGBE_MAX_FRAME_SIZE 0x3F00 151288943Sdim 152277323Sdim/* Flow control constants */ 153277323Sdim#define IXGBE_FC_PAUSE 0xFFFF 154277323Sdim#define IXGBE_FC_HI 0x20000 155277323Sdim#define IXGBE_FC_LO 0x10000 156277323Sdim 157/* 158 * Used for optimizing small rx mbufs. Effort is made to keep the copy 159 * small and aligned for the CPU L1 cache. 160 * 161 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 162 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 163 * wasted. Getting 64 byte alignment, which _should_ be ideal for 164 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 165 * in observed efficiency of the optimization, 97.9% -> 81.8%. 166 */ 167#define IXGBE_RX_COPY_LEN 160 168#define IXGBE_RX_COPY_ALIGN (MHLEN - IXGBE_RX_COPY_LEN) 169 170/* Keep older OS drivers building... */ 171#if !defined(SYSCTL_ADD_UQUAD) 172#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 173#endif 174 175/* Defines for printing debug information */ 176#define DEBUG_INIT 0 177#define DEBUG_IOCTL 0 178#define DEBUG_HW 0 179 180#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 181#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 182#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 183#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 184#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 185#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 186#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 187#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 188#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 189 190#define MAX_NUM_MULTICAST_ADDRESSES 128 191#define IXGBE_82598_SCATTER 100 192#define IXGBE_82599_SCATTER 32 193#define MSIX_82598_BAR 3 194#define MSIX_82599_BAR 4 195#define IXGBE_TSO_SIZE 262140 196#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 197#define IXGBE_RX_HDR 128 198#define IXGBE_VFTA_SIZE 128 199#define IXGBE_BR_SIZE 4096 200#define IXGBE_QUEUE_MIN_FREE 32 201 202/* IOCTL define to gather SFP+ Diagnostic data */ 203#define SIOCGI2C SIOCGIFGENERIC 204 205/* Offload bits in mbuf flag */ 206#if __FreeBSD_version >= 800000 207#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 208#else 209#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 210#endif 211 212/* For 6.X code compatibility */ 213#if !defined(ETHER_BPF_MTAP) 214#define ETHER_BPF_MTAP BPF_MTAP 215#endif 216 217#if __FreeBSD_version < 700000 218#define CSUM_TSO 0 219#define IFCAP_TSO4 0 220#endif 221 222/* 223 * Interrupt Moderation parameters 224 */ 225#define IXGBE_LOW_LATENCY 128 226#define IXGBE_AVE_LATENCY 400 227#define IXGBE_BULK_LATENCY 1200 228#define IXGBE_LINK_ITR 2000 229 230/* 231 ***************************************************************************** 232 * vendor_info_array 233 * 234 * This array contains the list of Subvendor/Subdevice IDs on which the driver 235 * should load. 236 * 237 ***************************************************************************** 238 */ 239typedef struct _ixgbe_vendor_info_t { 240 unsigned int vendor_id; 241 unsigned int device_id; 242 unsigned int subvendor_id; 243 unsigned int subdevice_id; 244 unsigned int index; 245} ixgbe_vendor_info_t; 246 247/* This is used to get SFP+ module data */ 248struct ixgbe_i2c_req { 249 u8 dev_addr; 250 u8 offset; 251 u8 len; 252 u8 data[8]; 253}; 254 255struct ixgbe_tx_buf { 256 u32 eop_index; 257 struct mbuf *m_head; 258 bus_dmamap_t map; 259}; 260 261struct ixgbe_rx_buf { 262 struct mbuf *buf; 263 struct mbuf *fmp; 264 bus_dmamap_t map; 265 u_int flags; 266#define IXGBE_RX_COPY 0x01 267 uint64_t addr; 268}; 269 270/* 271 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 272 */ 273struct ixgbe_dma_alloc { 274 bus_addr_t dma_paddr; 275 caddr_t dma_vaddr; 276 bus_dma_tag_t dma_tag; 277 bus_dmamap_t dma_map; 278 bus_dma_segment_t dma_seg; 279 bus_size_t dma_size; 280 int dma_nseg; 281}; 282 283/* 284** Driver queue struct: this is the interrupt container 285** for the associated tx and rx ring. 286*/ 287struct ix_queue { 288 struct adapter *adapter; 289 u32 msix; /* This queue's MSIX vector */ 290 u32 eims; /* This queue's EIMS bit */ 291 u32 eitr_setting; 292 struct resource *res; 293 void *tag; 294 struct tx_ring *txr; 295 struct rx_ring *rxr; 296 struct task que_task; 297 struct taskqueue *tq; 298 u64 irqs; 299}; 300 301/* 302 * The transmit ring, one per queue 303 */ 304struct tx_ring { 305 struct adapter *adapter; 306 struct mtx tx_mtx; 307 u32 me; 308 enum { 309 IXGBE_QUEUE_IDLE, 310 IXGBE_QUEUE_WORKING, 311 IXGBE_QUEUE_HUNG, 312 } queue_status; 313 int watchdog_time; 314 union ixgbe_adv_tx_desc *tx_base; 315 struct ixgbe_dma_alloc txdma; 316 u32 next_avail_desc; 317 u32 next_to_clean; 318 struct ixgbe_tx_buf *tx_buffers; 319 volatile u16 tx_avail; 320 u32 txd_cmd; 321 bus_dma_tag_t txtag; 322 char mtx_name[16]; 323#if __FreeBSD_version >= 800000 324 struct buf_ring *br; 325 struct task txq_task; 326#endif 327#ifdef IXGBE_FDIR 328 u16 atr_sample; 329 u16 atr_count; 330#endif 331 u32 bytes; /* used for AIM */ 332 u32 packets; 333 /* Soft Stats */ 334 u64 no_desc_avail; 335 u64 total_packets; 336}; 337 338 339/* 340 * The Receive ring, one per rx queue 341 */ 342struct rx_ring { 343 struct adapter *adapter; 344 struct mtx rx_mtx; 345 u32 me; 346 union ixgbe_adv_rx_desc *rx_base; 347 struct ixgbe_dma_alloc rxdma; 348 struct lro_ctrl lro; 349 bool lro_enabled; 350 bool hw_rsc; 351 bool discard; 352 bool vtag_strip; 353 u32 next_to_refresh; 354 u32 next_to_check; 355 char mtx_name[16]; 356 struct ixgbe_rx_buf *rx_buffers; 357 bus_dma_tag_t tag; 358 359 u32 bytes; /* Used for AIM calc */ 360 u32 packets; 361 362 /* Soft stats */ 363 u64 rx_irq; 364 u64 rx_copies; 365 u64 rx_packets; 366 u64 rx_bytes; 367 u64 rx_discarded; 368 u64 rsc_num; 369#ifdef IXGBE_FDIR 370 u64 flm; 371#endif 372}; 373 374/* Our adapter structure */ 375struct adapter { 376 struct ifnet *ifp; 377 struct ixgbe_hw hw; 378 379 struct ixgbe_osdep osdep; 380 struct device *dev; 381 382 struct resource *pci_mem; 383 struct resource *msix_mem; 384 385 /* 386 * Interrupt resources: this set is 387 * either used for legacy, or for Link 388 * when doing MSIX 389 */ 390 void *tag; 391 struct resource *res; 392 393 struct ifmedia media; 394 struct callout timer; 395 int msix; 396 int if_flags; 397 398 struct mtx core_mtx; 399 400 eventhandler_tag vlan_attach; 401 eventhandler_tag vlan_detach; 402 403 u16 num_vlans; 404 u16 num_queues; 405 406 /* 407 ** Shadow VFTA table, this is needed because 408 ** the real vlan filter table gets cleared during 409 ** a soft reset and the driver needs to be able 410 ** to repopulate it. 411 */ 412 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 413 414 /* Info about the interface */ 415 u32 optics; 416 u32 fc; /* local flow ctrl setting */ 417 int advertise; /* link speeds */ 418 bool link_active; 419 u16 max_frame_size; 420 u16 num_segs; 421 u32 link_speed; 422 bool link_up; 423 u32 linkvec; 424 425 /* Mbuf cluster size */ 426 u32 rx_mbuf_sz; 427 428 /* Support for pluggable optics */ 429 bool sfp_probe; 430 struct task link_task; /* Link tasklet */ 431 struct task mod_task; /* SFP tasklet */ 432 struct task msf_task; /* Multispeed Fiber */ 433#ifdef IXGBE_FDIR 434 int fdir_reinit; 435 struct task fdir_task; 436#endif 437 struct taskqueue *tq; 438 439 /* 440 ** Queues: 441 ** This is the irq holder, it has 442 ** and RX/TX pair or rings associated 443 ** with it. 444 */ 445 struct ix_queue *queues; 446 447 /* 448 * Transmit rings: 449 * Allocated at run time, an array of rings. 450 */ 451 struct tx_ring *tx_rings; 452 int num_tx_desc; 453 454 /* 455 * Receive rings: 456 * Allocated at run time, an array of rings. 457 */ 458 struct rx_ring *rx_rings; 459 int num_rx_desc; 460 u64 que_mask; 461 u32 rx_process_limit; 462 463 /* Multicast array memory */ 464 u8 *mta; 465 466 /* Misc stats maintained by the driver */ 467 unsigned long dropped_pkts; 468 unsigned long mbuf_defrag_failed; 469 unsigned long mbuf_header_failed; 470 unsigned long mbuf_packet_failed; 471 unsigned long no_tx_map_avail; 472 unsigned long no_tx_dma_setup; 473 unsigned long watchdog_events; 474 unsigned long tso_tx; 475 unsigned long link_irq; 476 477 struct ixgbe_hw_stats stats; 478}; 479 480/* Precision Time Sync (IEEE 1588) defines */ 481#define ETHERTYPE_IEEE1588 0x88F7 482#define PICOSECS_PER_TICK 20833 483#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 484#define IXGBE_ADVTXD_TSTAMP 0x00080000 485 486 487#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 488 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 489#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 490#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 491#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 492#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 493#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 494#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 495#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 496#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 497#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 498#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 499#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 500#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 501 502 503static inline bool 504ixgbe_is_sfp(struct ixgbe_hw *hw) 505{ 506 switch (hw->phy.type) { 507 case ixgbe_phy_sfp_avago: 508 case ixgbe_phy_sfp_ftl: 509 case ixgbe_phy_sfp_intel: 510 case ixgbe_phy_sfp_unknown: 511 case ixgbe_phy_sfp_passive_tyco: 512 case ixgbe_phy_sfp_passive_unknown: 513 return TRUE; 514 default: 515 return FALSE; 516 } 517} 518 519/* Workaround to make 8.0 buildable */ 520#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 521static __inline int 522drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 523{ 524#ifdef ALTQ 525 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 526 return (1); 527#endif 528 return (!buf_ring_empty(br)); 529} 530#endif 531 532/* 533** Find the number of unrefreshed RX descriptors 534*/ 535static inline u16 536ixgbe_rx_unrefreshed(struct rx_ring *rxr) 537{ 538 struct adapter *adapter = rxr->adapter; 539 540 if (rxr->next_to_check > rxr->next_to_refresh) 541 return (rxr->next_to_check - rxr->next_to_refresh - 1); 542 else 543 return ((adapter->num_rx_desc + rxr->next_to_check) - 544 rxr->next_to_refresh - 1); 545} 546 547#endif /* _IXGBE_H_ */ 548