ixgbe.h revision 239940
1/****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 239940 2012-08-31 10:07:38Z scottl $*/ 34 35 36#ifndef _IXGBE_H_ 37#define _IXGBE_H_ 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#if __FreeBSD_version >= 800000 43#include <sys/buf_ring.h> 44#endif 45#include <sys/mbuf.h> 46#include <sys/protosw.h> 47#include <sys/socket.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/module.h> 51#include <sys/sockio.h> 52 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59 60#include <net/bpf.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in_systm.h> 65#include <netinet/in.h> 66#include <netinet/if_ether.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/tcp_lro.h> 71#include <netinet/udp.h> 72 73#include <machine/in_cksum.h> 74 75#include <sys/bus.h> 76#include <machine/bus.h> 77#include <sys/rman.h> 78#include <machine/resource.h> 79#include <vm/vm.h> 80#include <vm/pmap.h> 81#include <machine/clock.h> 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84#include <sys/proc.h> 85#include <sys/sysctl.h> 86#include <sys/endian.h> 87#include <sys/taskqueue.h> 88#include <sys/pcpu.h> 89#include <sys/smp.h> 90#include <machine/smp.h> 91 92#ifdef IXGBE_IEEE1588 93#include <sys/ieee1588.h> 94#endif 95 96#include "ixgbe_api.h" 97 98/* Tunables */ 99 100/* 101 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102 * number of transmit descriptors allocated by the driver. Increasing this 103 * value allows the driver to queue more transmits. Each descriptor is 16 104 * bytes. Performance tests have show the 2K value to be optimal for top 105 * performance. 106 */ 107#define DEFAULT_TXD 1024 108#define PERFORM_TXD 2048 109#define MAX_TXD 4096 110#define MIN_TXD 64 111 112/* 113 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114 * number of receive descriptors allocated for each RX queue. Increasing this 115 * value allows the driver to buffer more incoming packets. Each descriptor 116 * is 16 bytes. A receive buffer is also allocated for each descriptor. 117 * 118 * Note: with 8 rings and a dual port card, it is possible to bump up 119 * against the system mbuf pool limit, you can tune nmbclusters 120 * to adjust for this. 121 */ 122#define DEFAULT_RXD 1024 123#define PERFORM_RXD 2048 124#define MAX_RXD 4096 125#define MIN_RXD 64 126 127/* Alignment for rings */ 128#define DBA_ALIGN 128 129 130/* 131 * This parameter controls the maximum no of times the driver will loop in 132 * the isr. Minimum Value = 1 133 */ 134#define MAX_LOOP 10 135 136/* 137 * This is the max watchdog interval, ie. the time that can 138 * pass between any two TX clean operations, such only happening 139 * when the TX hardware is functioning. 140 */ 141#define IXGBE_WATCHDOG (10 * hz) 142 143/* 144 * This parameters control when the driver calls the routine to reclaim 145 * transmit descriptors. 146 */ 147#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149 150#define IXGBE_MAX_FRAME_SIZE 0x3F00 151 152/* Flow control constants */ 153#define IXGBE_FC_PAUSE 0xFFFF 154#define IXGBE_FC_HI 0x20000 155#define IXGBE_FC_LO 0x10000 156 157/* 158 * Used for optimizing small rx mbufs. Effort is made to keep the copy 159 * small and aligned for the CPU L1 cache. 160 * 161 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 162 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 163 * wasted. Getting 64 byte alignment, which _should_ be ideal for 164 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 165 * in observed efficiency of the optimization, 97.9% -> 81.8%. 166 */ 167#define IXGBE_RX_COPY_LEN 160 168#define IXGBE_RX_COPY_ALIGN (MHLEN - IXGBE_RX_COPY_LEN) 169 170/* Keep older OS drivers building... */ 171#if !defined(SYSCTL_ADD_UQUAD) 172#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 173#endif 174 175/* Defines for printing debug information */ 176#define DEBUG_INIT 0 177#define DEBUG_IOCTL 0 178#define DEBUG_HW 0 179 180#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 181#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 182#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 183#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 184#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 185#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 186#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 187#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 188#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 189 190#define MAX_NUM_MULTICAST_ADDRESSES 128 191#define IXGBE_82598_SCATTER 100 192#define IXGBE_82599_SCATTER 32 193#define MSIX_82598_BAR 3 194#define MSIX_82599_BAR 4 195#define IXGBE_TSO_SIZE 262140 196#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 197#define IXGBE_RX_HDR 128 198#define IXGBE_VFTA_SIZE 128 199#define IXGBE_BR_SIZE 4096 200#define IXGBE_QUEUE_MIN_FREE 32 201#define IXGBE_QUEUE_IDLE 1 202#define IXGBE_QUEUE_WORKING 2 203#define IXGBE_QUEUE_HUNG 4 204#define IXGBE_QUEUE_DEPLETED 8 205 206/* Offload bits in mbuf flag */ 207#if __FreeBSD_version >= 800000 208#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 209#else 210#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 211#endif 212 213/* For 6.X code compatibility */ 214#if !defined(ETHER_BPF_MTAP) 215#define ETHER_BPF_MTAP BPF_MTAP 216#endif 217 218#if __FreeBSD_version < 700000 219#define CSUM_TSO 0 220#define IFCAP_TSO4 0 221#endif 222 223/* 224 * Interrupt Moderation parameters 225 */ 226#define IXGBE_LOW_LATENCY 128 227#define IXGBE_AVE_LATENCY 400 228#define IXGBE_BULK_LATENCY 1200 229#define IXGBE_LINK_ITR 2000 230 231/* 232 ***************************************************************************** 233 * vendor_info_array 234 * 235 * This array contains the list of Subvendor/Subdevice IDs on which the driver 236 * should load. 237 * 238 ***************************************************************************** 239 */ 240typedef struct _ixgbe_vendor_info_t { 241 unsigned int vendor_id; 242 unsigned int device_id; 243 unsigned int subvendor_id; 244 unsigned int subdevice_id; 245 unsigned int index; 246} ixgbe_vendor_info_t; 247 248 249struct ixgbe_tx_buf { 250 u32 eop_index; 251 struct mbuf *m_head; 252 bus_dmamap_t map; 253}; 254 255struct ixgbe_rx_buf { 256 struct mbuf *m_head; 257 struct mbuf *m_pack; 258 struct mbuf *fmp; 259 bus_dmamap_t hmap; 260 bus_dmamap_t pmap; 261 u_int flags; 262#define IXGBE_RX_COPY 0x01 263 uint64_t paddr; 264}; 265 266/* 267 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 268 */ 269struct ixgbe_dma_alloc { 270 bus_addr_t dma_paddr; 271 caddr_t dma_vaddr; 272 bus_dma_tag_t dma_tag; 273 bus_dmamap_t dma_map; 274 bus_dma_segment_t dma_seg; 275 bus_size_t dma_size; 276 int dma_nseg; 277}; 278 279/* 280** Driver queue struct: this is the interrupt container 281** for the associated tx and rx ring. 282*/ 283struct ix_queue { 284 struct adapter *adapter; 285 u32 msix; /* This queue's MSIX vector */ 286 u32 eims; /* This queue's EIMS bit */ 287 u32 eitr_setting; 288 struct resource *res; 289 void *tag; 290 struct tx_ring *txr; 291 struct rx_ring *rxr; 292 struct task que_task; 293 struct taskqueue *tq; 294 u64 irqs; 295}; 296 297/* 298 * The transmit ring, one per queue 299 */ 300struct tx_ring { 301 struct adapter *adapter; 302 struct mtx tx_mtx; 303 u32 me; 304 int queue_status; 305 int watchdog_time; 306 union ixgbe_adv_tx_desc *tx_base; 307 struct ixgbe_dma_alloc txdma; 308 u32 next_avail_desc; 309 u32 next_to_clean; 310 struct ixgbe_tx_buf *tx_buffers; 311 volatile u16 tx_avail; 312 u32 txd_cmd; 313 bus_dma_tag_t txtag; 314 char mtx_name[16]; 315#if __FreeBSD_version >= 800000 316 struct buf_ring *br; 317#endif 318#ifdef IXGBE_FDIR 319 u16 atr_sample; 320 u16 atr_count; 321#endif 322 u32 bytes; /* used for AIM */ 323 u32 packets; 324 /* Soft Stats */ 325 u64 no_desc_avail; 326 u64 total_packets; 327}; 328 329 330/* 331 * The Receive ring, one per rx queue 332 */ 333struct rx_ring { 334 struct adapter *adapter; 335 struct mtx rx_mtx; 336 u32 me; 337 union ixgbe_adv_rx_desc *rx_base; 338 struct ixgbe_dma_alloc rxdma; 339 struct lro_ctrl lro; 340 bool lro_enabled; 341 bool hdr_split; 342 bool hw_rsc; 343 bool discard; 344 bool vtag_strip; 345 u32 next_to_refresh; 346 u32 next_to_check; 347 char mtx_name[16]; 348 struct ixgbe_rx_buf *rx_buffers; 349 bus_dma_tag_t htag; 350 bus_dma_tag_t ptag; 351 352 u32 bytes; /* Used for AIM calc */ 353 u32 packets; 354 355 /* Soft stats */ 356 u64 rx_irq; 357 u64 rx_split_packets; 358 u64 rx_copies; 359 u64 rx_packets; 360 u64 rx_bytes; 361 u64 rx_discarded; 362 u64 rsc_num; 363#ifdef IXGBE_FDIR 364 u64 flm; 365#endif 366}; 367 368/* Our adapter structure */ 369struct adapter { 370 struct ifnet *ifp; 371 struct ixgbe_hw hw; 372 373 struct ixgbe_osdep osdep; 374 struct device *dev; 375 376 struct resource *pci_mem; 377 struct resource *msix_mem; 378 379 /* 380 * Interrupt resources: this set is 381 * either used for legacy, or for Link 382 * when doing MSIX 383 */ 384 void *tag; 385 struct resource *res; 386 387 struct ifmedia media; 388 struct callout timer; 389 int msix; 390 int if_flags; 391 392 struct mtx core_mtx; 393 394 eventhandler_tag vlan_attach; 395 eventhandler_tag vlan_detach; 396 397 u16 num_vlans; 398 u16 num_queues; 399 400 /* 401 ** Shadow VFTA table, this is needed because 402 ** the real vlan filter table gets cleared during 403 ** a soft reset and the driver needs to be able 404 ** to repopulate it. 405 */ 406 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 407 408 /* Info about the interface */ 409 u32 optics; 410 u32 fc; /* local flow ctrl setting */ 411 int advertise; /* link speeds */ 412 bool link_active; 413 u16 max_frame_size; 414 u16 num_segs; 415 u32 link_speed; 416 bool link_up; 417 u32 linkvec; 418 419 /* Mbuf cluster size */ 420 u32 rx_mbuf_sz; 421 422 /* Support for pluggable optics */ 423 bool sfp_probe; 424 struct task link_task; /* Link tasklet */ 425 struct task mod_task; /* SFP tasklet */ 426 struct task msf_task; /* Multispeed Fiber */ 427#ifdef IXGBE_FDIR 428 int fdir_reinit; 429 struct task fdir_task; 430#endif 431 struct taskqueue *tq; 432 433 /* 434 ** Queues: 435 ** This is the irq holder, it has 436 ** and RX/TX pair or rings associated 437 ** with it. 438 */ 439 struct ix_queue *queues; 440 441 /* 442 * Transmit rings: 443 * Allocated at run time, an array of rings. 444 */ 445 struct tx_ring *tx_rings; 446 int num_tx_desc; 447 448 /* 449 * Receive rings: 450 * Allocated at run time, an array of rings. 451 */ 452 struct rx_ring *rx_rings; 453 int num_rx_desc; 454 u64 que_mask; 455 u32 rx_process_limit; 456 457 /* Multicast array memory */ 458 u8 *mta; 459 460 /* Misc stats maintained by the driver */ 461 unsigned long dropped_pkts; 462 unsigned long mbuf_defrag_failed; 463 unsigned long mbuf_header_failed; 464 unsigned long mbuf_packet_failed; 465 unsigned long no_tx_map_avail; 466 unsigned long no_tx_dma_setup; 467 unsigned long watchdog_events; 468 unsigned long tso_tx; 469 unsigned long link_irq; 470 471 struct ixgbe_hw_stats stats; 472}; 473 474/* Precision Time Sync (IEEE 1588) defines */ 475#define ETHERTYPE_IEEE1588 0x88F7 476#define PICOSECS_PER_TICK 20833 477#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 478#define IXGBE_ADVTXD_TSTAMP 0x00080000 479 480 481#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 482 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 483#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 484#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 485#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 486#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 487#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 488#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 489#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 490#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 491#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 492#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 493#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 494#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 495 496 497static inline bool 498ixgbe_is_sfp(struct ixgbe_hw *hw) 499{ 500 switch (hw->phy.type) { 501 case ixgbe_phy_sfp_avago: 502 case ixgbe_phy_sfp_ftl: 503 case ixgbe_phy_sfp_intel: 504 case ixgbe_phy_sfp_unknown: 505 case ixgbe_phy_sfp_passive_tyco: 506 case ixgbe_phy_sfp_passive_unknown: 507 return TRUE; 508 default: 509 return FALSE; 510 } 511} 512 513/* Workaround to make 8.0 buildable */ 514#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 515static __inline int 516drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 517{ 518#ifdef ALTQ 519 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 520 return (1); 521#endif 522 return (!buf_ring_empty(br)); 523} 524#endif 525 526/* 527** Find the number of unrefreshed RX descriptors 528*/ 529static inline u16 530ixgbe_rx_unrefreshed(struct rx_ring *rxr) 531{ 532 struct adapter *adapter = rxr->adapter; 533 534 if (rxr->next_to_check > rxr->next_to_refresh) 535 return (rxr->next_to_check - rxr->next_to_refresh - 1); 536 else 537 return ((adapter->num_rx_desc + rxr->next_to_check) - 538 rxr->next_to_refresh - 1); 539} 540 541#endif /* _IXGBE_H_ */ 542