ixgbe.h revision 205904 
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3  Copyright (c) 2001-2010, Intel Corporation
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32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 205904 2010-03-30 19:09:18Z jfv $*/
34
35
36#ifndef _IXGBE_H_
37#define _IXGBE_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#if __FreeBSD_version >= 800000
43#include <sys/buf_ring.h>
44#endif
45#include <sys/mbuf.h>
46#include <sys/protosw.h>
47#include <sys/socket.h>
48#include <sys/malloc.h>
49#include <sys/kernel.h>
50#include <sys/module.h>
51#include <sys/sockio.h>
52
53#include <net/if.h>
54#include <net/if_arp.h>
55#include <net/bpf.h>
56#include <net/ethernet.h>
57#include <net/if_dl.h>
58#include <net/if_media.h>
59
60#include <net/bpf.h>
61#include <net/if_types.h>
62#include <net/if_vlan_var.h>
63
64#include <netinet/in_systm.h>
65#include <netinet/in.h>
66#include <netinet/if_ether.h>
67#include <netinet/ip.h>
68#include <netinet/ip6.h>
69#include <netinet/tcp.h>
70#include <netinet/tcp_lro.h>
71#include <netinet/udp.h>
72
73#include <machine/in_cksum.h>
74
75#include <sys/bus.h>
76#include <machine/bus.h>
77#include <sys/rman.h>
78#include <machine/resource.h>
79#include <vm/vm.h>
80#include <vm/pmap.h>
81#include <machine/clock.h>
82#include <dev/pci/pcivar.h>
83#include <dev/pci/pcireg.h>
84#include <sys/proc.h>
85#include <sys/sysctl.h>
86#include <sys/endian.h>
87#include <sys/taskqueue.h>
88#include <sys/pcpu.h>
89#include <sys/smp.h>
90#include <machine/smp.h>
91
92#ifdef IXGBE_IEEE1588
93#include <sys/ieee1588.h>
94#endif
95
96#include "ixgbe_api.h"
97
98/* Tunables */
99
100/*
101 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
102 * number of transmit descriptors allocated by the driver. Increasing this
103 * value allows the driver to queue more transmits. Each descriptor is 16
104 * bytes. Performance tests have show the 2K value to be optimal for top
105 * performance.
106 */
107#define DEFAULT_TXD	1024
108#define PERFORM_TXD	2048
109#define MAX_TXD		4096
110#define MIN_TXD		64
111
112/*
113 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
114 * number of receive descriptors allocated for each RX queue. Increasing this
115 * value allows the driver to buffer more incoming packets. Each descriptor
116 * is 16 bytes.  A receive buffer is also allocated for each descriptor.
117 *
118 * Note: with 8 rings and a dual port card, it is possible to bump up
119 *	against the system mbuf pool limit, you can tune nmbclusters
120 *	to adjust for this.
121 */
122#define DEFAULT_RXD	1024
123#define PERFORM_RXD	2048
124#define MAX_RXD		4096
125#define MIN_RXD		64
126
127/* Alignment for rings */
128#define DBA_ALIGN	128
129
130/*
131 * This parameter controls the maximum no of times the driver will loop in
132 * the isr. Minimum Value = 1
133 */
134#define MAX_LOOP	10
135
136/*
137 * This is the max watchdog interval, ie. the time that can
138 * pass between any two TX clean operations, such only happening
139 * when the TX hardware is functioning.
140 */
141#define IXGBE_WATCHDOG                   (10 * hz)
142
143/*
144 * This parameters control when the driver calls the routine to reclaim
145 * transmit descriptors.
146 */
147#define IXGBE_TX_CLEANUP_THRESHOLD	(adapter->num_tx_desc / 8)
148#define IXGBE_TX_OP_THRESHOLD		(adapter->num_tx_desc / 32)
149
150#define IXGBE_MAX_FRAME_SIZE	0x3F00
151
152/* Flow control constants */
153#define IXGBE_FC_PAUSE		0xFFFF
154#define IXGBE_FC_HI		0x20000
155#define IXGBE_FC_LO		0x10000
156
157/* Defines for printing debug information */
158#define DEBUG_INIT  0
159#define DEBUG_IOCTL 0
160#define DEBUG_HW    0
161
162#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
163#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
164#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
165#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
166#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
167#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
168#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
169#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
170#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
171
172#define MAX_NUM_MULTICAST_ADDRESSES     128
173#define IXGBE_82598_SCATTER		100
174#define IXGBE_82599_SCATTER		32
175#define MSIX_82598_BAR			3
176#define MSIX_82599_BAR			4
177#define IXGBE_TSO_SIZE			65535
178#define IXGBE_TX_BUFFER_SIZE		((u32) 1514)
179#define IXGBE_RX_HDR			128
180#define IXGBE_VFTA_SIZE			128
181#define IXGBE_BR_SIZE			4096
182
183/* Offload bits in mbuf flag */
184#if __FreeBSD_version >= 800000
185#define CSUM_OFFLOAD		(CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
186#else
187#define CSUM_OFFLOAD		(CSUM_IP|CSUM_TCP|CSUM_UDP)
188#endif
189
190/* For 6.X code compatibility */
191#if !defined(ETHER_BPF_MTAP)
192#define ETHER_BPF_MTAP		BPF_MTAP
193#endif
194
195#if __FreeBSD_version < 700000
196#define CSUM_TSO		0
197#define IFCAP_TSO4		0
198#endif
199
200/*
201 * Interrupt Moderation parameters
202 */
203#define IXGBE_LOW_LATENCY	128
204#define IXGBE_AVE_LATENCY	400
205#define IXGBE_BULK_LATENCY	1200
206#define IXGBE_LINK_ITR		2000
207
208/* Header split args for get_bug */
209#define IXGBE_CLEAN_HDR		1
210#define IXGBE_CLEAN_PKT		2
211#define IXGBE_CLEAN_ALL		3
212
213/*
214 *****************************************************************************
215 * vendor_info_array
216 *
217 * This array contains the list of Subvendor/Subdevice IDs on which the driver
218 * should load.
219 *
220 *****************************************************************************
221 */
222typedef struct _ixgbe_vendor_info_t {
223	unsigned int    vendor_id;
224	unsigned int    device_id;
225	unsigned int    subvendor_id;
226	unsigned int    subdevice_id;
227	unsigned int    index;
228} ixgbe_vendor_info_t;
229
230
231struct ixgbe_tx_buf {
232	u32		eop_index;
233	struct mbuf	*m_head;
234	bus_dmamap_t	map;
235};
236
237struct ixgbe_rx_buf {
238	struct mbuf	*m_head;
239	struct mbuf	*m_pack;
240	struct mbuf	*fmp;
241	bus_dmamap_t	map;
242};
243
244/*
245 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
246 */
247struct ixgbe_dma_alloc {
248	bus_addr_t		dma_paddr;
249	caddr_t			dma_vaddr;
250	bus_dma_tag_t		dma_tag;
251	bus_dmamap_t		dma_map;
252	bus_dma_segment_t	dma_seg;
253	bus_size_t		dma_size;
254	int			dma_nseg;
255};
256
257/*
258** Driver queue struct: this is the interrupt container
259**  for the associated tx and rx ring.
260*/
261struct ix_queue {
262	struct adapter		*adapter;
263	u32			msix;           /* This queue's MSIX vector */
264	u32			eims;           /* This queue's EIMS bit */
265	u32			eitr_setting;
266	struct resource		*res;
267	void			*tag;
268	struct tx_ring		*txr;
269	struct rx_ring		*rxr;
270	struct task		que_task;
271	struct taskqueue	*tq;
272	u64			irqs;
273};
274
275/*
276 * The transmit ring, one per queue
277 */
278struct tx_ring {
279        struct adapter		*adapter;
280	struct mtx		tx_mtx;
281	u32			me;
282	bool			watchdog_check;
283	int			watchdog_time;
284	union ixgbe_adv_tx_desc	*tx_base;
285	struct ixgbe_dma_alloc	txdma;
286	u32			next_avail_desc;
287	u32			next_to_clean;
288	struct ixgbe_tx_buf	*tx_buffers;
289	volatile u16		tx_avail;
290	u32			txd_cmd;
291	bus_dma_tag_t		txtag;
292	char			mtx_name[16];
293#if __FreeBSD_version >= 800000
294	struct buf_ring		*br;
295#endif
296#ifdef IXGBE_FDIR
297	u16			atr_sample;
298	u16			atr_count;
299#endif
300	u32			bytes;  /* used for AIM */
301	u32			packets;
302	/* Soft Stats */
303	u64			no_desc_avail;
304	u64			total_packets;
305};
306
307
308/*
309 * The Receive ring, one per rx queue
310 */
311struct rx_ring {
312        struct adapter		*adapter;
313	struct mtx		rx_mtx;
314	u32			me;
315	union ixgbe_adv_rx_desc	*rx_base;
316	struct ixgbe_dma_alloc	rxdma;
317	struct lro_ctrl		lro;
318	bool			lro_enabled;
319	bool			hdr_split;
320	bool			hw_rsc;
321	bool			discard;
322        u32			next_to_refresh;
323        u32 			next_to_check;
324	char			mtx_name[16];
325	struct ixgbe_rx_buf	*rx_buffers;
326	bus_dma_tag_t		rxtag;
327	bus_dmamap_t		spare_map;
328
329	u32			bytes; /* Used for AIM calc */
330	u32			packets;
331
332	/* Soft stats */
333	u64			rx_irq;
334	u64			rx_split_packets;
335	u64			rx_packets;
336	u64 			rx_bytes;
337	u64 			rx_discarded;
338	u64 			rsc_num;
339#ifdef IXGBE_FDIR
340	u64			flm;
341#endif
342};
343
344/* Our adapter structure */
345struct adapter {
346	struct ifnet		*ifp;
347	struct ixgbe_hw		hw;
348
349	struct ixgbe_osdep	osdep;
350	struct device		*dev;
351
352	struct resource		*pci_mem;
353	struct resource		*msix_mem;
354
355	/*
356	 * Interrupt resources: this set is
357	 * either used for legacy, or for Link
358	 * when doing MSIX
359	 */
360	void			*tag;
361	struct resource 	*res;
362
363	struct ifmedia		media;
364	struct callout		timer;
365	int			msix;
366	int			if_flags;
367
368	struct mtx		core_mtx;
369
370	eventhandler_tag 	vlan_attach;
371	eventhandler_tag 	vlan_detach;
372
373	u16			num_vlans;
374	u16			num_queues;
375
376	/* Info about the board itself */
377	u32			optics;
378	bool			link_active;
379	u16			max_frame_size;
380	u32			link_speed;
381	bool			link_up;
382	u32 			linkvec;
383
384	/* Mbuf cluster size */
385	u32			rx_mbuf_sz;
386
387	/* Support for pluggable optics */
388	bool			sfp_probe;
389	struct task     	link_task;  /* Link tasklet */
390	struct task     	mod_task;   /* SFP tasklet */
391	struct task     	msf_task;   /* Multispeed Fiber */
392#ifdef IXGBE_FDIR
393	int			fdir_reinit;
394	struct task     	fdir_task;
395#endif
396	struct taskqueue	*tq;
397
398	/*
399	** Queues:
400	**   This is the irq holder, it has
401	**   and RX/TX pair or rings associated
402	**   with it.
403	*/
404	struct ix_queue		*queues;
405
406	/*
407	 * Transmit rings:
408	 *	Allocated at run time, an array of rings.
409	 */
410	struct tx_ring		*tx_rings;
411	int			num_tx_desc;
412
413	/*
414	 * Receive rings:
415	 *	Allocated at run time, an array of rings.
416	 */
417	struct rx_ring		*rx_rings;
418	int			num_rx_desc;
419	u64			que_mask;
420	u32			rx_process_limit;
421
422	/* Misc stats maintained by the driver */
423	unsigned long   	dropped_pkts;
424	unsigned long   	mbuf_defrag_failed;
425	unsigned long   	mbuf_header_failed;
426	unsigned long   	mbuf_packet_failed;
427	unsigned long   	no_tx_map_avail;
428	unsigned long   	no_tx_dma_setup;
429	unsigned long   	watchdog_events;
430	unsigned long   	tso_tx;
431	unsigned long		link_irq;
432
433	struct ixgbe_hw_stats 	stats;
434};
435
436/* Precision Time Sync (IEEE 1588) defines */
437#define ETHERTYPE_IEEE1588      0x88F7
438#define PICOSECS_PER_TICK       20833
439#define TSYNC_UDP_PORT          319 /* UDP port for the protocol */
440#define IXGBE_ADVTXD_TSTAMP	0x00080000
441
442
443#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
444        mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
445#define IXGBE_CORE_LOCK_DESTROY(_sc)      mtx_destroy(&(_sc)->core_mtx)
446#define IXGBE_TX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->tx_mtx)
447#define IXGBE_RX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->rx_mtx)
448#define IXGBE_CORE_LOCK(_sc)              mtx_lock(&(_sc)->core_mtx)
449#define IXGBE_TX_LOCK(_sc)                mtx_lock(&(_sc)->tx_mtx)
450#define IXGBE_TX_TRYLOCK(_sc)             mtx_trylock(&(_sc)->tx_mtx)
451#define IXGBE_RX_LOCK(_sc)                mtx_lock(&(_sc)->rx_mtx)
452#define IXGBE_CORE_UNLOCK(_sc)            mtx_unlock(&(_sc)->core_mtx)
453#define IXGBE_TX_UNLOCK(_sc)              mtx_unlock(&(_sc)->tx_mtx)
454#define IXGBE_RX_UNLOCK(_sc)              mtx_unlock(&(_sc)->rx_mtx)
455#define IXGBE_CORE_LOCK_ASSERT(_sc)       mtx_assert(&(_sc)->core_mtx, MA_OWNED)
456#define IXGBE_TX_LOCK_ASSERT(_sc)         mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
457
458
459static inline bool
460ixgbe_is_sfp(struct ixgbe_hw *hw)
461{
462	switch (hw->phy.type) {
463	case ixgbe_phy_sfp_avago:
464	case ixgbe_phy_sfp_ftl:
465	case ixgbe_phy_sfp_intel:
466	case ixgbe_phy_sfp_unknown:
467	case ixgbe_phy_sfp_passive_tyco:
468	case ixgbe_phy_sfp_passive_unknown:
469		return TRUE;
470	default:
471		return FALSE;
472	}
473}
474
475#endif /* _IXGBE_H_ */
476