ixgbe.h revision 205720
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 205720 2010-03-27 00:21:40Z jfv $*/ 34 35 36#ifndef _IXGBE_H_ 37#define _IXGBE_H_ 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#if __FreeBSD_version >= 800000 43#include <sys/buf_ring.h> 44#endif 45#include <sys/mbuf.h> 46#include <sys/protosw.h> 47#include <sys/socket.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/module.h> 51#include <sys/sockio.h> 52 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59 60#include <net/bpf.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in_systm.h> 65#include <netinet/in.h> 66#include <netinet/if_ether.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/tcp_lro.h> 71#include <netinet/udp.h> 72 73#include <machine/in_cksum.h> 74 75#include <sys/bus.h> 76#include <machine/bus.h> 77#include <sys/rman.h> 78#include <machine/resource.h> 79#include <vm/vm.h> 80#include <vm/pmap.h> 81#include <machine/clock.h> 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84#include <sys/proc.h> 85#include <sys/sysctl.h> 86#include <sys/endian.h> 87#include <sys/taskqueue.h> 88#include <sys/pcpu.h> 89#include <sys/smp.h> 90#include <machine/smp.h> 91 92#ifdef IXGBE_IEEE1588 93#include <sys/ieee1588.h> 94#endif 95 96#include "ixgbe_api.h" 97 98/* Tunables */ 99 100/* 101 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102 * number of transmit descriptors allocated by the driver. Increasing this 103 * value allows the driver to queue more transmits. Each descriptor is 16 104 * bytes. Performance tests have show the 2K value to be optimal for top 105 * performance. 106 */ 107#define DEFAULT_TXD 1024 108#define PERFORM_TXD 2048 109#define MAX_TXD 4096 110#define MIN_TXD 64 111 112/* 113 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114 * number of receive descriptors allocated for each RX queue. Increasing this 115 * value allows the driver to buffer more incoming packets. Each descriptor 116 * is 16 bytes. A receive buffer is also allocated for each descriptor. 117 * 118 * Note: with 8 rings and a dual port card, it is possible to bump up 119 * against the system mbuf pool limit, you can tune nmbclusters 120 * to adjust for this. 121 */ 122#define DEFAULT_RXD 1024 123#define PERFORM_RXD 2048 124#define MAX_RXD 4096 125#define MIN_RXD 64 126 127/* Alignment for rings */ 128#define DBA_ALIGN 128 129 130/* 131 * This parameter controls the maximum no of times the driver will loop in 132 * the isr. Minimum Value = 1 133 */ 134#define MAX_LOOP 10 135 136/* 137 * This is the max watchdog interval, ie. the time that can 138 * pass between any two TX clean operations, such only happening 139 * when the TX hardware is functioning. 140 */ 141#define IXGBE_WATCHDOG (10 * hz) 142 143/* 144 * This parameters control when the driver calls the routine to reclaim 145 * transmit descriptors. 146 */ 147#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149 150#define IXGBE_MAX_FRAME_SIZE 0x3F00 151 152/* Flow control constants */ 153#define IXGBE_FC_PAUSE 0xFFFF 154#define IXGBE_FC_HI 0x20000 155#define IXGBE_FC_LO 0x10000 156 157/* Defines for printing debug information */ 158#define DEBUG_INIT 0 159#define DEBUG_IOCTL 0 160#define DEBUG_HW 0 161 162#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 163#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 164#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 165#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 166#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 167#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 168#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 169#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 170#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 171 172#define MAX_NUM_MULTICAST_ADDRESSES 128 173#define IXGBE_82598_SCATTER 100 174#define IXGBE_82599_SCATTER 32 175#define MSIX_82598_BAR 3 176#define MSIX_82599_BAR 4 177#define IXGBE_TSO_SIZE 65535 178#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 179#define IXGBE_RX_HDR 128 180#define IXGBE_VFTA_SIZE 128 181#define IXGBE_BR_SIZE 4096 182#define CSUM_OFFLOAD 7 /* Bits in csum flags */ 183 184/* For 6.X code compatibility */ 185#if !defined(ETHER_BPF_MTAP) 186#define ETHER_BPF_MTAP BPF_MTAP 187#endif 188 189#if __FreeBSD_version < 700000 190#define CSUM_TSO 0 191#define IFCAP_TSO4 0 192#endif 193 194/* 195 * Interrupt Moderation parameters 196 */ 197#define IXGBE_LOW_LATENCY 128 198#define IXGBE_AVE_LATENCY 400 199#define IXGBE_BULK_LATENCY 1200 200#define IXGBE_LINK_ITR 2000 201 202/* Header split args for get_bug */ 203#define IXGBE_CLEAN_HDR 1 204#define IXGBE_CLEAN_PKT 2 205#define IXGBE_CLEAN_ALL 3 206 207/* 208 ***************************************************************************** 209 * vendor_info_array 210 * 211 * This array contains the list of Subvendor/Subdevice IDs on which the driver 212 * should load. 213 * 214 ***************************************************************************** 215 */ 216typedef struct _ixgbe_vendor_info_t { 217 unsigned int vendor_id; 218 unsigned int device_id; 219 unsigned int subvendor_id; 220 unsigned int subdevice_id; 221 unsigned int index; 222} ixgbe_vendor_info_t; 223 224 225struct ixgbe_tx_buf { 226 u32 eop_index; 227 struct mbuf *m_head; 228 bus_dmamap_t map; 229}; 230 231struct ixgbe_rx_buf { 232 struct mbuf *m_head; 233 struct mbuf *m_pack; 234 struct mbuf *fmp; 235 bus_dmamap_t map; 236}; 237 238/* 239 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 240 */ 241struct ixgbe_dma_alloc { 242 bus_addr_t dma_paddr; 243 caddr_t dma_vaddr; 244 bus_dma_tag_t dma_tag; 245 bus_dmamap_t dma_map; 246 bus_dma_segment_t dma_seg; 247 bus_size_t dma_size; 248 int dma_nseg; 249}; 250 251/* 252** Driver queue struct: this is the interrupt container 253** for the associated tx and rx ring. 254*/ 255struct ix_queue { 256 struct adapter *adapter; 257 u32 msix; /* This queue's MSIX vector */ 258 u32 eims; /* This queue's EIMS bit */ 259 u32 eitr_setting; 260 struct resource *res; 261 void *tag; 262 struct tx_ring *txr; 263 struct rx_ring *rxr; 264 struct task que_task; 265 struct taskqueue *tq; 266 u64 irqs; 267}; 268 269/* 270 * The transmit ring, one per queue 271 */ 272struct tx_ring { 273 struct adapter *adapter; 274 struct mtx tx_mtx; 275 u32 me; 276 bool watchdog_check; 277 int watchdog_time; 278 union ixgbe_adv_tx_desc *tx_base; 279 struct ixgbe_dma_alloc txdma; 280 u32 next_avail_desc; 281 u32 next_to_clean; 282 struct ixgbe_tx_buf *tx_buffers; 283 volatile u16 tx_avail; 284 u32 txd_cmd; 285 bus_dma_tag_t txtag; 286 char mtx_name[16]; 287#if __FreeBSD_version >= 800000 288 struct buf_ring *br; 289#endif 290#ifdef IXGBE_FDIR 291 u16 atr_sample; 292 u16 atr_count; 293#endif 294 u32 bytes; /* used for AIM */ 295 u32 packets; 296 /* Soft Stats */ 297 u64 no_desc_avail; 298 u64 total_packets; 299}; 300 301 302/* 303 * The Receive ring, one per rx queue 304 */ 305struct rx_ring { 306 struct adapter *adapter; 307 struct mtx rx_mtx; 308 u32 me; 309 union ixgbe_adv_rx_desc *rx_base; 310 struct ixgbe_dma_alloc rxdma; 311 struct lro_ctrl lro; 312 bool lro_enabled; 313 bool hdr_split; 314 bool hw_rsc; 315 bool discard; 316 u32 next_to_refresh; 317 u32 next_to_check; 318 char mtx_name[16]; 319 struct ixgbe_rx_buf *rx_buffers; 320 bus_dma_tag_t rxtag; 321 bus_dmamap_t spare_map; 322 323 u32 bytes; /* Used for AIM calc */ 324 u32 packets; 325 326 /* Soft stats */ 327 u64 rx_irq; 328 u64 rx_split_packets; 329 u64 rx_packets; 330 u64 rx_bytes; 331 u64 rx_discarded; 332 u64 rsc_num; 333#ifdef IXGBE_FDIR 334 u64 flm; 335#endif 336}; 337 338/* Our adapter structure */ 339struct adapter { 340 struct ifnet *ifp; 341 struct ixgbe_hw hw; 342 343 struct ixgbe_osdep osdep; 344 struct device *dev; 345 346 struct resource *pci_mem; 347 struct resource *msix_mem; 348 349 /* 350 * Interrupt resources: this set is 351 * either used for legacy, or for Link 352 * when doing MSIX 353 */ 354 void *tag; 355 struct resource *res; 356 357 struct ifmedia media; 358 struct callout timer; 359 int msix; 360 int if_flags; 361 362 struct mtx core_mtx; 363 364 eventhandler_tag vlan_attach; 365 eventhandler_tag vlan_detach; 366 367 u16 num_vlans; 368 u16 num_queues; 369 370 /* Info about the board itself */ 371 u32 optics; 372 bool link_active; 373 u16 max_frame_size; 374 u32 link_speed; 375 bool link_up; 376 u32 linkvec; 377 378 /* Mbuf cluster size */ 379 u32 rx_mbuf_sz; 380 381 /* Support for pluggable optics */ 382 bool sfp_probe; 383 struct task link_task; /* Link tasklet */ 384 struct task mod_task; /* SFP tasklet */ 385 struct task msf_task; /* Multispeed Fiber */ 386#ifdef IXGBE_FDIR 387 int fdir_reinit; 388 struct task fdir_task; 389#endif 390 struct taskqueue *tq; 391 392 /* 393 ** Queues: 394 ** This is the irq holder, it has 395 ** and RX/TX pair or rings associated 396 ** with it. 397 */ 398 struct ix_queue *queues; 399 400 /* 401 * Transmit rings: 402 * Allocated at run time, an array of rings. 403 */ 404 struct tx_ring *tx_rings; 405 int num_tx_desc; 406 407 /* 408 * Receive rings: 409 * Allocated at run time, an array of rings. 410 */ 411 struct rx_ring *rx_rings; 412 int num_rx_desc; 413 u64 que_mask; 414 u32 rx_process_limit; 415 416 /* Misc stats maintained by the driver */ 417 unsigned long dropped_pkts; 418 unsigned long mbuf_defrag_failed; 419 unsigned long mbuf_header_failed; 420 unsigned long mbuf_packet_failed; 421 unsigned long no_tx_map_avail; 422 unsigned long no_tx_dma_setup; 423 unsigned long watchdog_events; 424 unsigned long tso_tx; 425 unsigned long link_irq; 426 427 struct ixgbe_hw_stats stats; 428}; 429 430/* Precision Time Sync (IEEE 1588) defines */ 431#define ETHERTYPE_IEEE1588 0x88F7 432#define PICOSECS_PER_TICK 20833 433#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 434#define IXGBE_ADVTXD_TSTAMP 0x00080000 435 436 437#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 438 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 439#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 440#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 441#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 442#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 443#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 444#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 445#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 446#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 447#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 448#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 449#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 450#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 451 452 453static inline bool 454ixgbe_is_sfp(struct ixgbe_hw *hw) 455{ 456 switch (hw->phy.type) { 457 case ixgbe_phy_sfp_avago: 458 case ixgbe_phy_sfp_ftl: 459 case ixgbe_phy_sfp_intel: 460 case ixgbe_phy_sfp_unknown: 461 case ixgbe_phy_sfp_passive_tyco: 462 case ixgbe_phy_sfp_passive_unknown: 463 return TRUE; 464 default: 465 return FALSE; 466 } 467} 468 469#endif /* _IXGBE_H_ */ 470