ixgbe.h revision 251964
1254721Semaste/****************************************************************************** 2254721Semaste 3254721Semaste Copyright (c) 2001-2013, Intel Corporation 4254721Semaste All rights reserved. 5254721Semaste 6254721Semaste Redistribution and use in source and binary forms, with or without 7254721Semaste modification, are permitted provided that the following conditions are met: 8254721Semaste 9254721Semaste 1. Redistributions of source code must retain the above copyright notice, 10254721Semaste this list of conditions and the following disclaimer. 11254721Semaste 12254721Semaste 2. Redistributions in binary form must reproduce the above copyright 13254721Semaste notice, this list of conditions and the following disclaimer in the 14254721Semaste documentation and/or other materials provided with the distribution. 15254721Semaste 16254721Semaste 3. Neither the name of the Intel Corporation nor the names of its 17254721Semaste contributors may be used to endorse or promote products derived from 18254721Semaste this software without specific prior written permission. 19254721Semaste 20254721Semaste THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21254721Semaste AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22254721Semaste IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23254721Semaste ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24254721Semaste LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25254721Semaste CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26254721Semaste SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27254721Semaste INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28254721Semaste CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29254721Semaste ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30254721Semaste POSSIBILITY OF SUCH DAMAGE. 31254721Semaste 32254721Semaste******************************************************************************/ 33254721Semaste/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 251964 2013-06-18 21:28:19Z jfv $*/ 34254721Semaste 35254721Semaste 36254721Semaste#ifndef _IXGBE_H_ 37254721Semaste#define _IXGBE_H_ 38254721Semaste 39254721Semaste 40254721Semaste#include <sys/param.h> 41254721Semaste#include <sys/systm.h> 42254721Semaste#ifndef IXGBE_LEGACY_TX 43254721Semaste#include <sys/buf_ring.h> 44254721Semaste#endif 45254721Semaste#include <sys/mbuf.h> 46254721Semaste#include <sys/protosw.h> 47254721Semaste#include <sys/socket.h> 48254721Semaste#include <sys/malloc.h> 49254721Semaste#include <sys/kernel.h> 50254721Semaste#include <sys/module.h> 51254721Semaste#include <sys/sockio.h> 52254721Semaste 53254721Semaste#include <net/if.h> 54254721Semaste#include <net/if_arp.h> 55254721Semaste#include <net/bpf.h> 56254721Semaste#include <net/ethernet.h> 57254721Semaste#include <net/if_dl.h> 58254721Semaste#include <net/if_media.h> 59254721Semaste 60254721Semaste#include <net/bpf.h> 61254721Semaste#include <net/if_types.h> 62254721Semaste#include <net/if_vlan_var.h> 63254721Semaste 64254721Semaste#include <netinet/in_systm.h> 65254721Semaste#include <netinet/in.h> 66254721Semaste#include <netinet/if_ether.h> 67254721Semaste#include <netinet/ip.h> 68254721Semaste#include <netinet/ip6.h> 69254721Semaste#include <netinet/tcp.h> 70254721Semaste#include <netinet/tcp_lro.h> 71254721Semaste#include <netinet/udp.h> 72254721Semaste 73254721Semaste#include <machine/in_cksum.h> 74254721Semaste 75254721Semaste#include <sys/bus.h> 76254721Semaste#include <machine/bus.h> 77254721Semaste#include <sys/rman.h> 78254721Semaste#include <machine/resource.h> 79254721Semaste#include <vm/vm.h> 80254721Semaste#include <vm/pmap.h> 81254721Semaste#include <machine/clock.h> 82254721Semaste#include <dev/pci/pcivar.h> 83254721Semaste#include <dev/pci/pcireg.h> 84254721Semaste#include <sys/proc.h> 85254721Semaste#include <sys/sysctl.h> 86254721Semaste#include <sys/endian.h> 87254721Semaste#include <sys/taskqueue.h> 88254721Semaste#include <sys/pcpu.h> 89254721Semaste#include <sys/smp.h> 90254721Semaste#include <machine/smp.h> 91254721Semaste 92254721Semaste#include "ixgbe_api.h" 93254721Semaste 94254721Semaste/* Tunables */ 95254721Semaste 96254721Semaste/* 97254721Semaste * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 98254721Semaste * number of transmit descriptors allocated by the driver. Increasing this 99254721Semaste * value allows the driver to queue more transmits. Each descriptor is 16 100254721Semaste * bytes. Performance tests have show the 2K value to be optimal for top 101254721Semaste * performance. 102254721Semaste */ 103254721Semaste#define DEFAULT_TXD 1024 104254721Semaste#define PERFORM_TXD 2048 105254721Semaste#define MAX_TXD 4096 106254721Semaste#define MIN_TXD 64 107254721Semaste 108254721Semaste/* 109254721Semaste * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 110254721Semaste * number of receive descriptors allocated for each RX queue. Increasing this 111254721Semaste * value allows the driver to buffer more incoming packets. Each descriptor 112254721Semaste * is 16 bytes. A receive buffer is also allocated for each descriptor. 113254721Semaste * 114254721Semaste * Note: with 8 rings and a dual port card, it is possible to bump up 115254721Semaste * against the system mbuf pool limit, you can tune nmbclusters 116254721Semaste * to adjust for this. 117254721Semaste */ 118254721Semaste#define DEFAULT_RXD 1024 119254721Semaste#define PERFORM_RXD 2048 120254721Semaste#define MAX_RXD 4096 121254721Semaste#define MIN_RXD 64 122254721Semaste 123254721Semaste/* Alignment for rings */ 124254721Semaste#define DBA_ALIGN 128 125254721Semaste 126254721Semaste/* 127254721Semaste * This parameter controls the maximum no of times the driver will loop in 128254721Semaste * the isr. Minimum Value = 1 129254721Semaste */ 130254721Semaste#define MAX_LOOP 10 131254721Semaste 132254721Semaste/* 133254721Semaste * This is the max watchdog interval, ie. the time that can 134254721Semaste * pass between any two TX clean operations, such only happening 135254721Semaste * when the TX hardware is functioning. 136254721Semaste */ 137254721Semaste#define IXGBE_WATCHDOG (10 * hz) 138254721Semaste 139254721Semaste/* 140254721Semaste * This parameters control when the driver calls the routine to reclaim 141254721Semaste * transmit descriptors. 142254721Semaste */ 143254721Semaste#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 144254721Semaste#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 145254721Semaste 146254721Semaste#define IXGBE_MAX_FRAME_SIZE 0x3F00 147254721Semaste 148254721Semaste/* Flow control constants */ 149254721Semaste#define IXGBE_FC_PAUSE 0xFFFF 150254721Semaste#define IXGBE_FC_HI 0x20000 151254721Semaste#define IXGBE_FC_LO 0x10000 152254721Semaste 153254721Semaste/* 154254721Semaste * Used for optimizing small rx mbufs. Effort is made to keep the copy 155254721Semaste * small and aligned for the CPU L1 cache. 156254721Semaste * 157254721Semaste * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 158254721Semaste * 32 byte alignment needed for the fast bcopy results in 8 bytes being 159254721Semaste * wasted. Getting 64 byte alignment, which _should_ be ideal for 160254721Semaste * modern Intel CPUs, results in 40 bytes wasted and a significant drop 161254721Semaste * in observed efficiency of the optimization, 97.9% -> 81.8%. 162254721Semaste */ 163254721Semaste#define IXGBE_RX_COPY_LEN 160 164254721Semaste#define IXGBE_RX_COPY_ALIGN (MHLEN - IXGBE_RX_COPY_LEN) 165254721Semaste 166254721Semaste/* Keep older OS drivers building... */ 167254721Semaste#if !defined(SYSCTL_ADD_UQUAD) 168254721Semaste#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 169254721Semaste#endif 170254721Semaste 171254721Semaste/* Defines for printing debug information */ 172254721Semaste#define DEBUG_INIT 0 173254721Semaste#define DEBUG_IOCTL 0 174254721Semaste#define DEBUG_HW 0 175254721Semaste 176254721Semaste#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 177254721Semaste#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 178254721Semaste#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 179254721Semaste#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 180254721Semaste#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 181254721Semaste#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 182254721Semaste#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 183254721Semaste#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 184254721Semaste#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 185254721Semaste 186254721Semaste#define MAX_NUM_MULTICAST_ADDRESSES 128 187254721Semaste#define IXGBE_82598_SCATTER 100 188254721Semaste#define IXGBE_82599_SCATTER 32 189254721Semaste#define MSIX_82598_BAR 3 190254721Semaste#define MSIX_82599_BAR 4 191254721Semaste#define IXGBE_TSO_SIZE 262140 192254721Semaste#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 193254721Semaste#define IXGBE_RX_HDR 128 194254721Semaste#define IXGBE_VFTA_SIZE 128 195254721Semaste#define IXGBE_BR_SIZE 4096 196254721Semaste#define IXGBE_QUEUE_MIN_FREE 32 197254721Semaste 198254721Semaste/* IOCTL define to gather SFP+ Diagnostic data */ 199254721Semaste#define SIOCGI2C SIOCGIFGENERIC 200254721Semaste 201254721Semaste/* Offload bits in mbuf flag */ 202254721Semaste#if __FreeBSD_version >= 800000 203254721Semaste#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 204254721Semaste#else 205254721Semaste#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 206254721Semaste#endif 207254721Semaste 208254721Semaste/* 209254721Semaste * Interrupt Moderation parameters 210254721Semaste */ 211254721Semaste#define IXGBE_LOW_LATENCY 128 212254721Semaste#define IXGBE_AVE_LATENCY 400 213254721Semaste#define IXGBE_BULK_LATENCY 1200 214254721Semaste#define IXGBE_LINK_ITR 2000 215254721Semaste 216254721Semaste 217254721Semaste/* 218254721Semaste ***************************************************************************** 219254721Semaste * vendor_info_array 220254721Semaste * 221254721Semaste * This array contains the list of Subvendor/Subdevice IDs on which the driver 222254721Semaste * should load. 223254721Semaste * 224254721Semaste ***************************************************************************** 225254721Semaste */ 226254721Semastetypedef struct _ixgbe_vendor_info_t { 227254721Semaste unsigned int vendor_id; 228254721Semaste unsigned int device_id; 229254721Semaste unsigned int subvendor_id; 230254721Semaste unsigned int subdevice_id; 231254721Semaste unsigned int index; 232254721Semaste} ixgbe_vendor_info_t; 233254721Semaste 234254721Semaste 235254721Semaste/* This is used to get SFP+ module data */ 236254721Semastestruct ixgbe_i2c_req { 237254721Semaste u8 dev_addr; 238254721Semaste u8 offset; 239254721Semaste u8 len; 240254721Semaste u8 data[8]; 241254721Semaste}; 242254721Semaste 243254721Semastestruct ixgbe_tx_buf { 244254721Semaste union ixgbe_adv_tx_desc *eop; 245254721Semaste struct mbuf *m_head; 246254721Semaste bus_dmamap_t map; 247254721Semaste}; 248254721Semaste 249254721Semastestruct ixgbe_rx_buf { 250254721Semaste struct mbuf *buf; 251254721Semaste struct mbuf *fmp; 252254721Semaste bus_dmamap_t pmap; 253254721Semaste u_int flags; 254254721Semaste#define IXGBE_RX_COPY 0x01 255254721Semaste uint64_t addr; 256254721Semaste}; 257254721Semaste 258254721Semaste/* 259254721Semaste * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 260254721Semaste */ 261254721Semastestruct ixgbe_dma_alloc { 262254721Semaste bus_addr_t dma_paddr; 263254721Semaste caddr_t dma_vaddr; 264254721Semaste bus_dma_tag_t dma_tag; 265254721Semaste bus_dmamap_t dma_map; 266254721Semaste bus_dma_segment_t dma_seg; 267254721Semaste bus_size_t dma_size; 268254721Semaste int dma_nseg; 269254721Semaste}; 270254721Semaste 271254721Semaste/* 272254721Semaste** Driver queue struct: this is the interrupt container 273254721Semaste** for the associated tx and rx ring. 274254721Semaste*/ 275254721Semastestruct ix_queue { 276254721Semaste struct adapter *adapter; 277254721Semaste u32 msix; /* This queue's MSIX vector */ 278254721Semaste u32 eims; /* This queue's EIMS bit */ 279254721Semaste u32 eitr_setting; 280254721Semaste struct resource *res; 281254721Semaste void *tag; 282254721Semaste struct tx_ring *txr; 283254721Semaste struct rx_ring *rxr; 284254721Semaste struct task que_task; 285254721Semaste struct taskqueue *tq; 286254721Semaste u64 irqs; 287254721Semaste}; 288254721Semaste 289254721Semaste/* 290254721Semaste * The transmit ring, one per queue 291254721Semaste */ 292254721Semastestruct tx_ring { 293254721Semaste struct adapter *adapter; 294254721Semaste struct mtx tx_mtx; 295254721Semaste u32 me; 296254721Semaste int watchdog_time; 297254721Semaste union ixgbe_adv_tx_desc *tx_base; 298254721Semaste struct ixgbe_tx_buf *tx_buffers; 299254721Semaste struct ixgbe_dma_alloc txdma; 300254721Semaste volatile u16 tx_avail; 301254721Semaste u16 next_avail_desc; 302254721Semaste u16 next_to_clean; 303254721Semaste u16 process_limit; 304254721Semaste u16 num_desc; 305254721Semaste enum { 306254721Semaste IXGBE_QUEUE_IDLE, 307254721Semaste IXGBE_QUEUE_WORKING, 308254721Semaste IXGBE_QUEUE_HUNG, 309254721Semaste } queue_status; 310254721Semaste u32 txd_cmd; 311254721Semaste bus_dma_tag_t txtag; 312254721Semaste char mtx_name[16]; 313254721Semaste#ifndef IXGBE_LEGACY_TX 314254721Semaste struct buf_ring *br; 315254721Semaste struct task txq_task; 316254721Semaste#endif 317254721Semaste#ifdef IXGBE_FDIR 318254721Semaste u16 atr_sample; 319254721Semaste u16 atr_count; 320254721Semaste#endif 321254721Semaste u32 bytes; /* used for AIM */ 322254721Semaste u32 packets; 323254721Semaste /* Soft Stats */ 324254721Semaste unsigned long tso_tx; 325254721Semaste unsigned long no_tx_map_avail; 326254721Semaste unsigned long no_tx_dma_setup; 327254721Semaste u64 no_desc_avail; 328254721Semaste u64 total_packets; 329254721Semaste}; 330254721Semaste 331254721Semaste 332254721Semaste/* 333254721Semaste * The Receive ring, one per rx queue 334254721Semaste */ 335254721Semastestruct rx_ring { 336254721Semaste struct adapter *adapter; 337254721Semaste struct mtx rx_mtx; 338254721Semaste u32 me; 339254721Semaste union ixgbe_adv_rx_desc *rx_base; 340254721Semaste struct ixgbe_dma_alloc rxdma; 341254721Semaste struct lro_ctrl lro; 342254721Semaste bool lro_enabled; 343254721Semaste bool hw_rsc; 344254721Semaste bool discard; 345254721Semaste bool vtag_strip; 346254721Semaste u16 next_to_refresh; 347254721Semaste u16 next_to_check; 348254721Semaste u16 num_desc; 349254721Semaste u16 mbuf_sz; 350254721Semaste u16 process_limit; 351254721Semaste char mtx_name[16]; 352254721Semaste struct ixgbe_rx_buf *rx_buffers; 353254721Semaste bus_dma_tag_t ptag; 354254721Semaste 355254721Semaste u32 bytes; /* Used for AIM calc */ 356254721Semaste u32 packets; 357254721Semaste 358254721Semaste /* Soft stats */ 359254721Semaste u64 rx_irq; 360254721Semaste u64 rx_copies; 361254721Semaste u64 rx_packets; 362254721Semaste u64 rx_bytes; 363254721Semaste u64 rx_discarded; 364254721Semaste u64 rsc_num; 365254721Semaste#ifdef IXGBE_FDIR 366254721Semaste u64 flm; 367254721Semaste#endif 368254721Semaste}; 369254721Semaste 370254721Semaste/* Our adapter structure */ 371254721Semastestruct adapter { 372254721Semaste struct ifnet *ifp; 373254721Semaste struct ixgbe_hw hw; 374254721Semaste 375254721Semaste struct ixgbe_osdep osdep; 376254721Semaste struct device *dev; 377254721Semaste 378254721Semaste struct resource *pci_mem; 379254721Semaste struct resource *msix_mem; 380254721Semaste 381254721Semaste /* 382254721Semaste * Interrupt resources: this set is 383254721Semaste * either used for legacy, or for Link 384254721Semaste * when doing MSIX 385254721Semaste */ 386254721Semaste void *tag; 387254721Semaste struct resource *res; 388254721Semaste 389254721Semaste struct ifmedia media; 390254721Semaste struct callout timer; 391254721Semaste int msix; 392254721Semaste int if_flags; 393254721Semaste 394254721Semaste struct mtx core_mtx; 395254721Semaste 396254721Semaste eventhandler_tag vlan_attach; 397254721Semaste eventhandler_tag vlan_detach; 398 399 u16 num_vlans; 400 u16 num_queues; 401 402 /* 403 ** Shadow VFTA table, this is needed because 404 ** the real vlan filter table gets cleared during 405 ** a soft reset and the driver needs to be able 406 ** to repopulate it. 407 */ 408 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 409 410 /* Info about the interface */ 411 u32 optics; 412 u32 fc; /* local flow ctrl setting */ 413 int advertise; /* link speeds */ 414 bool link_active; 415 u16 max_frame_size; 416 u16 num_segs; 417 u32 link_speed; 418 bool link_up; 419 u32 linkvec; 420 421 /* Mbuf cluster size */ 422 u32 rx_mbuf_sz; 423 424 /* Support for pluggable optics */ 425 bool sfp_probe; 426 struct task link_task; /* Link tasklet */ 427 struct task mod_task; /* SFP tasklet */ 428 struct task msf_task; /* Multispeed Fiber */ 429#ifdef IXGBE_FDIR 430 int fdir_reinit; 431 struct task fdir_task; 432#endif 433 struct taskqueue *tq; 434 435 /* 436 ** Queues: 437 ** This is the irq holder, it has 438 ** and RX/TX pair or rings associated 439 ** with it. 440 */ 441 struct ix_queue *queues; 442 443 /* 444 * Transmit rings: 445 * Allocated at run time, an array of rings. 446 */ 447 struct tx_ring *tx_rings; 448 u32 num_tx_desc; 449 450 /* 451 * Receive rings: 452 * Allocated at run time, an array of rings. 453 */ 454 struct rx_ring *rx_rings; 455 u64 que_mask; 456 u32 num_rx_desc; 457 458 /* Multicast array memory */ 459 u8 *mta; 460 461 462 /* Misc stats maintained by the driver */ 463 unsigned long dropped_pkts; 464 unsigned long mbuf_defrag_failed; 465 unsigned long mbuf_header_failed; 466 unsigned long mbuf_packet_failed; 467 unsigned long watchdog_events; 468 unsigned long link_irq; 469 470 struct ixgbe_hw_stats stats; 471}; 472 473 474/* Precision Time Sync (IEEE 1588) defines */ 475#define ETHERTYPE_IEEE1588 0x88F7 476#define PICOSECS_PER_TICK 20833 477#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 478#define IXGBE_ADVTXD_TSTAMP 0x00080000 479 480 481#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 482 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 483#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 484#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 485#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 486#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 487#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 488#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 489#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 490#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 491#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 492#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 493#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 494#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 495 496/* For backward compatibility */ 497#if !defined(PCIER_LINK_STA) 498#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 499#endif 500 501static inline bool 502ixgbe_is_sfp(struct ixgbe_hw *hw) 503{ 504 switch (hw->phy.type) { 505 case ixgbe_phy_sfp_avago: 506 case ixgbe_phy_sfp_ftl: 507 case ixgbe_phy_sfp_intel: 508 case ixgbe_phy_sfp_unknown: 509 case ixgbe_phy_sfp_passive_tyco: 510 case ixgbe_phy_sfp_passive_unknown: 511 return TRUE; 512 default: 513 return FALSE; 514 } 515} 516 517/* Workaround to make 8.0 buildable */ 518#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 519static __inline int 520drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 521{ 522#ifdef ALTQ 523 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 524 return (1); 525#endif 526 return (!buf_ring_empty(br)); 527} 528#endif 529 530/* 531** Find the number of unrefreshed RX descriptors 532*/ 533static inline u16 534ixgbe_rx_unrefreshed(struct rx_ring *rxr) 535{ 536 if (rxr->next_to_check > rxr->next_to_refresh) 537 return (rxr->next_to_check - rxr->next_to_refresh - 1); 538 else 539 return ((rxr->num_desc + rxr->next_to_check) - 540 rxr->next_to_refresh - 1); 541} 542 543#endif /* _IXGBE_H_ */ 544