ixgbe.h revision 208762
1227569Sphilip/****************************************************************************** 2227569Sphilip 3227569Sphilip Copyright (c) 2001-2010, Intel Corporation 4227569Sphilip All rights reserved. 5227569Sphilip 6227569Sphilip Redistribution and use in source and binary forms, with or without 7227569Sphilip modification, are permitted provided that the following conditions are met: 8227569Sphilip 9227569Sphilip 1. Redistributions of source code must retain the above copyright notice, 10227569Sphilip this list of conditions and the following disclaimer. 11227569Sphilip 12227569Sphilip 2. Redistributions in binary form must reproduce the above copyright 13227569Sphilip notice, this list of conditions and the following disclaimer in the 14227569Sphilip documentation and/or other materials provided with the distribution. 15227569Sphilip 16227569Sphilip 3. Neither the name of the Intel Corporation nor the names of its 17227569Sphilip contributors may be used to endorse or promote products derived from 18227569Sphilip this software without specific prior written permission. 19227569Sphilip 20227569Sphilip THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21227569Sphilip AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22227569Sphilip IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23227569Sphilip ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24227569Sphilip LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25227569Sphilip CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26227569Sphilip SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27227569Sphilip INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28227569Sphilip CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29227569Sphilip ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30227569Sphilip POSSIBILITY OF SUCH DAMAGE. 31227569Sphilip 32227569Sphilip******************************************************************************/ 33227569Sphilip/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 208762 2010-06-03 00:00:45Z jfv $*/ 34227569Sphilip 35227569Sphilip 36227569Sphilip#ifndef _IXGBE_H_ 37227569Sphilip#define _IXGBE_H_ 38227569Sphilip 39227569Sphilip 40227569Sphilip#include <sys/param.h> 41227569Sphilip#include <sys/systm.h> 42227569Sphilip#if __FreeBSD_version >= 800000 43227569Sphilip#include <sys/buf_ring.h> 44227569Sphilip#endif 45227569Sphilip#include <sys/mbuf.h> 46227569Sphilip#include <sys/protosw.h> 47227569Sphilip#include <sys/socket.h> 48227569Sphilip#include <sys/malloc.h> 49227569Sphilip#include <sys/kernel.h> 50227569Sphilip#include <sys/module.h> 51227569Sphilip#include <sys/sockio.h> 52227569Sphilip 53227569Sphilip#include <net/if.h> 54227569Sphilip#include <net/if_arp.h> 55227569Sphilip#include <net/bpf.h> 56227569Sphilip#include <net/ethernet.h> 57227569Sphilip#include <net/if_dl.h> 58227569Sphilip#include <net/if_media.h> 59227569Sphilip 60227569Sphilip#include <net/bpf.h> 61227569Sphilip#include <net/if_types.h> 62227569Sphilip#include <net/if_vlan_var.h> 63227569Sphilip 64227569Sphilip#include <netinet/in_systm.h> 65227569Sphilip#include <netinet/in.h> 66227569Sphilip#include <netinet/if_ether.h> 67227569Sphilip#include <netinet/ip.h> 68227569Sphilip#include <netinet/ip6.h> 69227569Sphilip#include <netinet/tcp.h> 70227569Sphilip#include <netinet/tcp_lro.h> 71227569Sphilip#include <netinet/udp.h> 72227569Sphilip 73227569Sphilip#include <machine/in_cksum.h> 74227569Sphilip 75227569Sphilip#include <sys/bus.h> 76227569Sphilip#include <machine/bus.h> 77227569Sphilip#include <sys/rman.h> 78227569Sphilip#include <machine/resource.h> 79227569Sphilip#include <vm/vm.h> 80227569Sphilip#include <vm/pmap.h> 81227569Sphilip#include <machine/clock.h> 82227569Sphilip#include <dev/pci/pcivar.h> 83227569Sphilip#include <dev/pci/pcireg.h> 84227569Sphilip#include <sys/proc.h> 85227569Sphilip#include <sys/sysctl.h> 86227569Sphilip#include <sys/endian.h> 87227569Sphilip#include <sys/taskqueue.h> 88227569Sphilip#include <sys/pcpu.h> 89227569Sphilip#include <sys/smp.h> 90227569Sphilip#include <machine/smp.h> 91227569Sphilip 92227569Sphilip#ifdef IXGBE_IEEE1588 93227569Sphilip#include <sys/ieee1588.h> 94227569Sphilip#endif 95227569Sphilip 96227569Sphilip#include "ixgbe_api.h" 97227569Sphilip 98227569Sphilip/* Tunables */ 99227569Sphilip 100227569Sphilip/* 101227569Sphilip * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102227569Sphilip * number of transmit descriptors allocated by the driver. Increasing this 103227569Sphilip * value allows the driver to queue more transmits. Each descriptor is 16 104227569Sphilip * bytes. Performance tests have show the 2K value to be optimal for top 105227569Sphilip * performance. 106227569Sphilip */ 107227569Sphilip#define DEFAULT_TXD 1024 108227569Sphilip#define PERFORM_TXD 2048 109227569Sphilip#define MAX_TXD 4096 110227569Sphilip#define MIN_TXD 64 111227569Sphilip 112227569Sphilip/* 113227569Sphilip * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114227569Sphilip * number of receive descriptors allocated for each RX queue. Increasing this 115227569Sphilip * value allows the driver to buffer more incoming packets. Each descriptor 116227569Sphilip * is 16 bytes. A receive buffer is also allocated for each descriptor. 117227569Sphilip * 118227569Sphilip * Note: with 8 rings and a dual port card, it is possible to bump up 119227569Sphilip * against the system mbuf pool limit, you can tune nmbclusters 120227569Sphilip * to adjust for this. 121227569Sphilip */ 122227569Sphilip#define DEFAULT_RXD 1024 123227569Sphilip#define PERFORM_RXD 2048 124227569Sphilip#define MAX_RXD 4096 125227569Sphilip#define MIN_RXD 64 126227569Sphilip 127227569Sphilip/* Alignment for rings */ 128227569Sphilip#define DBA_ALIGN 128 129227569Sphilip 130227569Sphilip/* 131227569Sphilip * This parameter controls the maximum no of times the driver will loop in 132227569Sphilip * the isr. Minimum Value = 1 133227569Sphilip */ 134227569Sphilip#define MAX_LOOP 10 135227569Sphilip 136227569Sphilip/* 137227569Sphilip * This is the max watchdog interval, ie. the time that can 138227569Sphilip * pass between any two TX clean operations, such only happening 139227569Sphilip * when the TX hardware is functioning. 140227569Sphilip */ 141227569Sphilip#define IXGBE_WATCHDOG (10 * hz) 142227569Sphilip 143227569Sphilip/* 144227569Sphilip * This parameters control when the driver calls the routine to reclaim 145227569Sphilip * transmit descriptors. 146227569Sphilip */ 147227569Sphilip#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148227569Sphilip#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149227569Sphilip 150227569Sphilip#define IXGBE_MAX_FRAME_SIZE 0x3F00 151227569Sphilip 152227569Sphilip/* Flow control constants */ 153227569Sphilip#define IXGBE_FC_PAUSE 0xFFFF 154227569Sphilip#define IXGBE_FC_HI 0x20000 155227569Sphilip#define IXGBE_FC_LO 0x10000 156227569Sphilip 157227569Sphilip/* Defines for printing debug information */ 158227569Sphilip#define DEBUG_INIT 0 159227569Sphilip#define DEBUG_IOCTL 0 160227569Sphilip#define DEBUG_HW 0 161227569Sphilip 162227569Sphilip#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 163227569Sphilip#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 164227569Sphilip#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 165227569Sphilip#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 166227569Sphilip#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 167227569Sphilip#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 168227569Sphilip#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 169227569Sphilip#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 170227569Sphilip#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 171227569Sphilip 172227569Sphilip#define MAX_NUM_MULTICAST_ADDRESSES 128 173227569Sphilip#define IXGBE_82598_SCATTER 100 174227569Sphilip#define IXGBE_82599_SCATTER 32 175227569Sphilip#define MSIX_82598_BAR 3 176227569Sphilip#define MSIX_82599_BAR 4 177227569Sphilip#define IXGBE_TSO_SIZE 65535 178227569Sphilip#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 179227569Sphilip#define IXGBE_RX_HDR 128 180227569Sphilip#define IXGBE_VFTA_SIZE 128 181227569Sphilip#define IXGBE_BR_SIZE 4096 182227569Sphilip 183227569Sphilip/* Offload bits in mbuf flag */ 184227569Sphilip#if __FreeBSD_version >= 800000 185227569Sphilip#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 186227569Sphilip#else 187227569Sphilip#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 188227569Sphilip#endif 189227569Sphilip 190227569Sphilip/* For 6.X code compatibility */ 191227569Sphilip#if !defined(ETHER_BPF_MTAP) 192227569Sphilip#define ETHER_BPF_MTAP BPF_MTAP 193227569Sphilip#endif 194227569Sphilip 195227569Sphilip#if __FreeBSD_version < 700000 196227569Sphilip#define CSUM_TSO 0 197227569Sphilip#define IFCAP_TSO4 0 198227569Sphilip#endif 199227569Sphilip 200227569Sphilip/* 201227569Sphilip * Interrupt Moderation parameters 202227569Sphilip */ 203227569Sphilip#define IXGBE_LOW_LATENCY 128 204227569Sphilip#define IXGBE_AVE_LATENCY 400 205227569Sphilip#define IXGBE_BULK_LATENCY 1200 206227569Sphilip#define IXGBE_LINK_ITR 2000 207227569Sphilip 208227569Sphilip/* Header split args for get_bug */ 209227569Sphilip#define IXGBE_CLEAN_HDR 1 210227569Sphilip#define IXGBE_CLEAN_PKT 2 211227569Sphilip#define IXGBE_CLEAN_ALL 3 212227569Sphilip 213227569Sphilip/* 214227569Sphilip ***************************************************************************** 215227569Sphilip * vendor_info_array 216227569Sphilip * 217227569Sphilip * This array contains the list of Subvendor/Subdevice IDs on which the driver 218227569Sphilip * should load. 219227569Sphilip * 220227569Sphilip ***************************************************************************** 221227569Sphilip */ 222227569Sphiliptypedef struct _ixgbe_vendor_info_t { 223227569Sphilip unsigned int vendor_id; 224227569Sphilip unsigned int device_id; 225227569Sphilip unsigned int subvendor_id; 226227569Sphilip unsigned int subdevice_id; 227227569Sphilip unsigned int index; 228227569Sphilip} ixgbe_vendor_info_t; 229227569Sphilip 230227569Sphilip 231227569Sphilipstruct ixgbe_tx_buf { 232227569Sphilip u32 eop_index; 233227569Sphilip struct mbuf *m_head; 234227569Sphilip bus_dmamap_t map; 235227569Sphilip}; 236227569Sphilip 237227569Sphilipstruct ixgbe_rx_buf { 238227569Sphilip struct mbuf *m_head; 239227569Sphilip struct mbuf *m_pack; 240227569Sphilip struct mbuf *fmp; 241227569Sphilip bus_dmamap_t hmap; 242227569Sphilip bus_dmamap_t pmap; 243227569Sphilip}; 244227569Sphilip 245227569Sphilip/* 246227569Sphilip * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 247227569Sphilip */ 248227569Sphilipstruct ixgbe_dma_alloc { 249227569Sphilip bus_addr_t dma_paddr; 250227569Sphilip caddr_t dma_vaddr; 251227569Sphilip bus_dma_tag_t dma_tag; 252227569Sphilip bus_dmamap_t dma_map; 253227569Sphilip bus_dma_segment_t dma_seg; 254227569Sphilip bus_size_t dma_size; 255227569Sphilip int dma_nseg; 256227569Sphilip}; 257227569Sphilip 258227569Sphilip/* 259227569Sphilip** Driver queue struct: this is the interrupt container 260227569Sphilip** for the associated tx and rx ring. 261227569Sphilip*/ 262227569Sphilipstruct ix_queue { 263227569Sphilip struct adapter *adapter; 264227569Sphilip u32 msix; /* This queue's MSIX vector */ 265227569Sphilip u32 eims; /* This queue's EIMS bit */ 266227569Sphilip u32 eitr_setting; 267227569Sphilip struct resource *res; 268227569Sphilip void *tag; 269227569Sphilip struct tx_ring *txr; 270227569Sphilip struct rx_ring *rxr; 271227569Sphilip struct task que_task; 272227569Sphilip struct taskqueue *tq; 273227569Sphilip u64 irqs; 274227569Sphilip}; 275227569Sphilip 276227569Sphilip/* 277227569Sphilip * The transmit ring, one per queue 278227569Sphilip */ 279227569Sphilipstruct tx_ring { 280227569Sphilip struct adapter *adapter; 281227569Sphilip struct mtx tx_mtx; 282227569Sphilip u32 me; 283227569Sphilip bool watchdog_check; 284227569Sphilip int watchdog_time; 285227569Sphilip union ixgbe_adv_tx_desc *tx_base; 286227569Sphilip struct ixgbe_dma_alloc txdma; 287227569Sphilip u32 next_avail_desc; 288227569Sphilip u32 next_to_clean; 289227569Sphilip struct ixgbe_tx_buf *tx_buffers; 290227569Sphilip volatile u16 tx_avail; 291227569Sphilip u32 txd_cmd; 292227569Sphilip bus_dma_tag_t txtag; 293227569Sphilip char mtx_name[16]; 294227569Sphilip#if __FreeBSD_version >= 800000 295227569Sphilip struct buf_ring *br; 296227569Sphilip#endif 297227569Sphilip#ifdef IXGBE_FDIR 298227569Sphilip u16 atr_sample; 299227569Sphilip u16 atr_count; 300227569Sphilip#endif 301227569Sphilip u32 bytes; /* used for AIM */ 302227569Sphilip u32 packets; 303227569Sphilip /* Soft Stats */ 304227569Sphilip u64 no_desc_avail; 305227569Sphilip u64 total_packets; 306227569Sphilip}; 307227569Sphilip 308227569Sphilip 309227569Sphilip/* 310227569Sphilip * The Receive ring, one per rx queue 311227569Sphilip */ 312227569Sphilipstruct rx_ring { 313227569Sphilip struct adapter *adapter; 314227569Sphilip struct mtx rx_mtx; 315227569Sphilip u32 me; 316227569Sphilip union ixgbe_adv_rx_desc *rx_base; 317227569Sphilip struct ixgbe_dma_alloc rxdma; 318227569Sphilip struct lro_ctrl lro; 319227569Sphilip bool lro_enabled; 320227569Sphilip bool hdr_split; 321227569Sphilip bool hw_rsc; 322227569Sphilip bool discard; 323227569Sphilip u32 next_to_refresh; 324227569Sphilip u32 next_to_check; 325227569Sphilip char mtx_name[16]; 326227569Sphilip struct ixgbe_rx_buf *rx_buffers; 327227569Sphilip bus_dma_tag_t htag; 328227569Sphilip bus_dma_tag_t ptag; 329227569Sphilip 330227569Sphilip u32 bytes; /* Used for AIM calc */ 331227569Sphilip u32 packets; 332227569Sphilip 333227569Sphilip /* Soft stats */ 334227569Sphilip u64 rx_irq; 335227569Sphilip u64 rx_split_packets; 336227569Sphilip u64 rx_packets; 337227569Sphilip u64 rx_bytes; 338227569Sphilip u64 rx_discarded; 339227569Sphilip u64 rsc_num; 340227569Sphilip#ifdef IXGBE_FDIR 341227569Sphilip u64 flm; 342227569Sphilip#endif 343227569Sphilip}; 344227569Sphilip 345227569Sphilip/* Our adapter structure */ 346227569Sphilipstruct adapter { 347227569Sphilip struct ifnet *ifp; 348227569Sphilip struct ixgbe_hw hw; 349227569Sphilip 350227569Sphilip struct ixgbe_osdep osdep; 351227569Sphilip struct device *dev; 352227569Sphilip 353227569Sphilip struct resource *pci_mem; 354227569Sphilip struct resource *msix_mem; 355227569Sphilip 356227569Sphilip /* 357227569Sphilip * Interrupt resources: this set is 358227569Sphilip * either used for legacy, or for Link 359227569Sphilip * when doing MSIX 360227569Sphilip */ 361227569Sphilip void *tag; 362227569Sphilip struct resource *res; 363227569Sphilip 364227569Sphilip struct ifmedia media; 365227569Sphilip struct callout timer; 366227569Sphilip int msix; 367227569Sphilip int if_flags; 368227569Sphilip 369227569Sphilip struct mtx core_mtx; 370227569Sphilip 371227569Sphilip eventhandler_tag vlan_attach; 372227569Sphilip eventhandler_tag vlan_detach; 373227569Sphilip 374227569Sphilip u16 num_vlans; 375227569Sphilip u16 num_queues; 376227569Sphilip 377227569Sphilip /* Info about the board itself */ 378227569Sphilip u32 optics; 379227569Sphilip bool link_active; 380227569Sphilip u16 max_frame_size; 381227569Sphilip u32 link_speed; 382227569Sphilip bool link_up; 383227569Sphilip u32 linkvec; 384227569Sphilip 385227569Sphilip /* Mbuf cluster size */ 386227569Sphilip u32 rx_mbuf_sz; 387227569Sphilip 388227569Sphilip /* Support for pluggable optics */ 389227569Sphilip bool sfp_probe; 390227569Sphilip struct task link_task; /* Link tasklet */ 391227569Sphilip struct task mod_task; /* SFP tasklet */ 392227569Sphilip struct task msf_task; /* Multispeed Fiber */ 393227569Sphilip#ifdef IXGBE_FDIR 394227569Sphilip int fdir_reinit; 395227569Sphilip struct task fdir_task; 396227569Sphilip#endif 397227569Sphilip struct taskqueue *tq; 398227569Sphilip 399227569Sphilip /* 400227569Sphilip ** Queues: 401227569Sphilip ** This is the irq holder, it has 402227569Sphilip ** and RX/TX pair or rings associated 403227569Sphilip ** with it. 404227569Sphilip */ 405227569Sphilip struct ix_queue *queues; 406227569Sphilip 407227569Sphilip /* 408227569Sphilip * Transmit rings: 409227569Sphilip * Allocated at run time, an array of rings. 410227569Sphilip */ 411227569Sphilip struct tx_ring *tx_rings; 412227569Sphilip int num_tx_desc; 413227569Sphilip 414227569Sphilip /* 415227569Sphilip * Receive rings: 416227569Sphilip * Allocated at run time, an array of rings. 417227569Sphilip */ 418227569Sphilip struct rx_ring *rx_rings; 419227569Sphilip int num_rx_desc; 420227569Sphilip u64 que_mask; 421227569Sphilip u32 rx_process_limit; 422227569Sphilip 423227569Sphilip /* Misc stats maintained by the driver */ 424227569Sphilip unsigned long dropped_pkts; 425227569Sphilip unsigned long mbuf_defrag_failed; 426227569Sphilip unsigned long mbuf_header_failed; 427227569Sphilip unsigned long mbuf_packet_failed; 428227569Sphilip unsigned long no_tx_map_avail; 429227569Sphilip unsigned long no_tx_dma_setup; 430227569Sphilip unsigned long watchdog_events; 431227569Sphilip unsigned long tso_tx; 432227569Sphilip unsigned long link_irq; 433227569Sphilip 434227569Sphilip struct ixgbe_hw_stats stats; 435227569Sphilip}; 436227569Sphilip 437227569Sphilip/* Precision Time Sync (IEEE 1588) defines */ 438227569Sphilip#define ETHERTYPE_IEEE1588 0x88F7 439227569Sphilip#define PICOSECS_PER_TICK 20833 440227569Sphilip#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 441227569Sphilip#define IXGBE_ADVTXD_TSTAMP 0x00080000 442227569Sphilip 443227569Sphilip 444227569Sphilip#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 445227569Sphilip mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 446227569Sphilip#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 447227569Sphilip#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 448227569Sphilip#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 449227569Sphilip#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 450227569Sphilip#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 451227569Sphilip#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 452227569Sphilip#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 453227569Sphilip#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 454227569Sphilip#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 455227569Sphilip#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 456227569Sphilip#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 457227569Sphilip#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 458227569Sphilip 459227569Sphilip 460227569Sphilipstatic inline bool 461227569Sphilipixgbe_is_sfp(struct ixgbe_hw *hw) 462227569Sphilip{ 463227569Sphilip switch (hw->phy.type) { 464227569Sphilip case ixgbe_phy_sfp_avago: 465227569Sphilip case ixgbe_phy_sfp_ftl: 466227569Sphilip case ixgbe_phy_sfp_intel: 467227569Sphilip case ixgbe_phy_sfp_unknown: 468227569Sphilip case ixgbe_phy_sfp_passive_tyco: 469227569Sphilip case ixgbe_phy_sfp_passive_unknown: 470227569Sphilip return TRUE; 471227569Sphilip default: 472227569Sphilip return FALSE; 473227569Sphilip } 474227569Sphilip} 475227569Sphilip 476227569Sphilip/* Workaround to make 8.0 buildable */ 477227569Sphilip#if __FreeBSD_version < 800504 478227569Sphilipstatic __inline int 479227569Sphilipdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 480227569Sphilip{ 481227569Sphilip#ifdef ALTQ 482227569Sphilip if (ALTQ_IS_ENABLED(&ifp->if_snd)) 483227569Sphilip return (1); 484227569Sphilip#endif 485227569Sphilip return (!buf_ring_empty(br)); 486227569Sphilip} 487227569Sphilip#endif 488227569Sphilip 489227569Sphilip#endif /* _IXGBE_H_ */ 490227569Sphilip