1179055Sjfv/****************************************************************************** 2171384Sjfv 3283620Serj Copyright (c) 2001-2015, Intel Corporation 4179055Sjfv All rights reserved. 5179055Sjfv 6179055Sjfv Redistribution and use in source and binary forms, with or without 7179055Sjfv modification, are permitted provided that the following conditions are met: 8179055Sjfv 9179055Sjfv 1. Redistributions of source code must retain the above copyright notice, 10179055Sjfv this list of conditions and the following disclaimer. 11179055Sjfv 12179055Sjfv 2. Redistributions in binary form must reproduce the above copyright 13179055Sjfv notice, this list of conditions and the following disclaimer in the 14179055Sjfv documentation and/or other materials provided with the distribution. 15179055Sjfv 16179055Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17179055Sjfv contributors may be used to endorse or promote products derived from 18179055Sjfv this software without specific prior written permission. 19179055Sjfv 20179055Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21179055Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22179055Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23179055Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24179055Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25179055Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26179055Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27179055Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28179055Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29179055Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30179055Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: releng/10.2/sys/dev/ixgbe/ixgbe.h 283620 2015-05-27 17:44:11Z erj $*/ 34171384Sjfv 35185352Sjfv 36171384Sjfv#ifndef _IXGBE_H_ 37171384Sjfv#define _IXGBE_H_ 38171384Sjfv 39171384Sjfv 40171384Sjfv#include <sys/param.h> 41171384Sjfv#include <sys/systm.h> 42243725Sjfv#ifndef IXGBE_LEGACY_TX 43194875Sjfv#include <sys/buf_ring.h> 44194875Sjfv#endif 45171384Sjfv#include <sys/mbuf.h> 46171384Sjfv#include <sys/protosw.h> 47171384Sjfv#include <sys/socket.h> 48171384Sjfv#include <sys/malloc.h> 49171384Sjfv#include <sys/kernel.h> 50171384Sjfv#include <sys/module.h> 51171384Sjfv#include <sys/sockio.h> 52171384Sjfv 53171384Sjfv#include <net/if.h> 54171384Sjfv#include <net/if_arp.h> 55171384Sjfv#include <net/bpf.h> 56171384Sjfv#include <net/ethernet.h> 57171384Sjfv#include <net/if_dl.h> 58171384Sjfv#include <net/if_media.h> 59171384Sjfv 60171384Sjfv#include <net/bpf.h> 61171384Sjfv#include <net/if_types.h> 62171384Sjfv#include <net/if_vlan_var.h> 63171384Sjfv 64171384Sjfv#include <netinet/in_systm.h> 65171384Sjfv#include <netinet/in.h> 66171384Sjfv#include <netinet/if_ether.h> 67171384Sjfv#include <netinet/ip.h> 68171384Sjfv#include <netinet/ip6.h> 69171384Sjfv#include <netinet/tcp.h> 70190873Sjfv#include <netinet/tcp_lro.h> 71171384Sjfv#include <netinet/udp.h> 72171384Sjfv 73171384Sjfv#include <machine/in_cksum.h> 74171384Sjfv 75171384Sjfv#include <sys/bus.h> 76171384Sjfv#include <machine/bus.h> 77171384Sjfv#include <sys/rman.h> 78171384Sjfv#include <machine/resource.h> 79171384Sjfv#include <vm/vm.h> 80171384Sjfv#include <vm/pmap.h> 81171384Sjfv#include <machine/clock.h> 82171384Sjfv#include <dev/pci/pcivar.h> 83171384Sjfv#include <dev/pci/pcireg.h> 84171384Sjfv#include <sys/proc.h> 85171384Sjfv#include <sys/sysctl.h> 86171384Sjfv#include <sys/endian.h> 87171384Sjfv#include <sys/taskqueue.h> 88179055Sjfv#include <sys/pcpu.h> 89194875Sjfv#include <sys/smp.h> 90194875Sjfv#include <machine/smp.h> 91283620Serj#include <sys/sbuf.h> 92171384Sjfv 93171384Sjfv#include "ixgbe_api.h" 94283620Serj#include "ixgbe_common.h" 95283620Serj#include "ixgbe_phy.h" 96283620Serj#include "ixgbe_vf.h" 97171384Sjfv 98171384Sjfv/* Tunables */ 99171384Sjfv 100171384Sjfv/* 101172043Sjfv * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102171384Sjfv * number of transmit descriptors allocated by the driver. Increasing this 103171384Sjfv * value allows the driver to queue more transmits. Each descriptor is 16 104172043Sjfv * bytes. Performance tests have show the 2K value to be optimal for top 105172043Sjfv * performance. 106171384Sjfv */ 107190873Sjfv#define DEFAULT_TXD 1024 108172043Sjfv#define PERFORM_TXD 2048 109171384Sjfv#define MAX_TXD 4096 110171384Sjfv#define MIN_TXD 64 111171384Sjfv 112171384Sjfv/* 113172043Sjfv * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114172043Sjfv * number of receive descriptors allocated for each RX queue. Increasing this 115171384Sjfv * value allows the driver to buffer more incoming packets. Each descriptor 116172043Sjfv * is 16 bytes. A receive buffer is also allocated for each descriptor. 117171384Sjfv * 118172043Sjfv * Note: with 8 rings and a dual port card, it is possible to bump up 119172043Sjfv * against the system mbuf pool limit, you can tune nmbclusters 120172043Sjfv * to adjust for this. 121171384Sjfv */ 122190873Sjfv#define DEFAULT_RXD 1024 123172043Sjfv#define PERFORM_RXD 2048 124171384Sjfv#define MAX_RXD 4096 125171384Sjfv#define MIN_RXD 64 126171384Sjfv 127172043Sjfv/* Alignment for rings */ 128172043Sjfv#define DBA_ALIGN 128 129172043Sjfv 130171384Sjfv/* 131171384Sjfv * This parameter controls the maximum no of times the driver will loop in 132171384Sjfv * the isr. Minimum Value = 1 133171384Sjfv */ 134185352Sjfv#define MAX_LOOP 10 135171384Sjfv 136171384Sjfv/* 137200239Sjfv * This is the max watchdog interval, ie. the time that can 138200239Sjfv * pass between any two TX clean operations, such only happening 139200239Sjfv * when the TX hardware is functioning. 140171384Sjfv */ 141200239Sjfv#define IXGBE_WATCHDOG (10 * hz) 142171384Sjfv 143171384Sjfv/* 144171384Sjfv * This parameters control when the driver calls the routine to reclaim 145171384Sjfv * transmit descriptors. 146171384Sjfv */ 147171384Sjfv#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148171384Sjfv#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149171384Sjfv 150283620Serj/* These defines are used in MTU calculations */ 151283620Serj#define IXGBE_MAX_FRAME_SIZE 9728 152283620Serj#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 153283620Serj ETHER_VLAN_ENCAP_LEN) 154283620Serj#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 155171384Sjfv 156172043Sjfv/* Flow control constants */ 157200239Sjfv#define IXGBE_FC_PAUSE 0xFFFF 158172043Sjfv#define IXGBE_FC_HI 0x20000 159172043Sjfv#define IXGBE_FC_LO 0x10000 160171384Sjfv 161239940Sscottl/* 162239940Sscottl * Used for optimizing small rx mbufs. Effort is made to keep the copy 163239940Sscottl * small and aligned for the CPU L1 cache. 164239940Sscottl * 165239940Sscottl * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 166239940Sscottl * 32 byte alignment needed for the fast bcopy results in 8 bytes being 167239940Sscottl * wasted. Getting 64 byte alignment, which _should_ be ideal for 168239940Sscottl * modern Intel CPUs, results in 40 bytes wasted and a significant drop 169239940Sscottl * in observed efficiency of the optimization, 97.9% -> 81.8%. 170239940Sscottl */ 171281954Sngie#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) 172281954Sngie#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 173281954Sngie#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) 174239940Sscottl 175221189Sjfv/* Keep older OS drivers building... */ 176221189Sjfv#if !defined(SYSCTL_ADD_UQUAD) 177221189Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 178221189Sjfv#endif 179221189Sjfv 180171384Sjfv/* Defines for printing debug information */ 181171384Sjfv#define DEBUG_INIT 0 182171384Sjfv#define DEBUG_IOCTL 0 183171384Sjfv#define DEBUG_HW 0 184171384Sjfv 185171384Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 186171384Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 187171384Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 188171384Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 189171384Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 190171384Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 191171384Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 192171384Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 193171384Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 194171384Sjfv 195171384Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 196190873Sjfv#define IXGBE_82598_SCATTER 100 197190873Sjfv#define IXGBE_82599_SCATTER 32 198185352Sjfv#define MSIX_82598_BAR 3 199185352Sjfv#define MSIX_82599_BAR 4 200234620Sbz#define IXGBE_TSO_SIZE 262140 201171384Sjfv#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 202205720Sjfv#define IXGBE_RX_HDR 128 203194875Sjfv#define IXGBE_VFTA_SIZE 128 204194875Sjfv#define IXGBE_BR_SIZE 4096 205230775Sjfv#define IXGBE_QUEUE_MIN_FREE 32 206283620Serj#define IXGBE_MAX_TX_BUSY 10 207283620Serj#define IXGBE_QUEUE_HUNG 0x80000000 208171384Sjfv 209283620Serj#define IXV_EITR_DEFAULT 128 210243718Sjfv 211205904Sjfv/* Offload bits in mbuf flag */ 212205904Sjfv#if __FreeBSD_version >= 800000 213205904Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 214205904Sjfv#else 215205904Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 216205904Sjfv#endif 217205904Sjfv 218283620Serj/* Backward compatibility items for very old versions */ 219283620Serj#ifndef pci_find_cap 220283620Serj#define pci_find_cap pci_find_extcap 221283620Serj#endif 222283620Serj 223283620Serj#ifndef DEVMETHOD_END 224283620Serj#define DEVMETHOD_END { NULL, NULL } 225283620Serj#endif 226283620Serj 227171384Sjfv/* 228171384Sjfv * Interrupt Moderation parameters 229171384Sjfv */ 230185352Sjfv#define IXGBE_LOW_LATENCY 128 231185352Sjfv#define IXGBE_AVE_LATENCY 400 232185352Sjfv#define IXGBE_BULK_LATENCY 1200 233185352Sjfv#define IXGBE_LINK_ITR 2000 234171384Sjfv 235283620Serj/* MAC type macros */ 236283620Serj#define IXGBE_IS_X550VF(_adapter) \ 237283620Serj ((_adapter->hw.mac.type == ixgbe_mac_X550_vf) || \ 238283620Serj (_adapter->hw.mac.type == ixgbe_mac_X550EM_x_vf)) 239251964Sjfv 240283620Serj#define IXGBE_IS_VF(_adapter) \ 241283620Serj (IXGBE_IS_X550VF(_adapter) || \ 242283620Serj (_adapter->hw.mac.type == ixgbe_mac_X540_vf) || \ 243283620Serj (_adapter->hw.mac.type == ixgbe_mac_82599_vf)) 244283620Serj 245283620Serj 246171384Sjfv/* 247185352Sjfv ***************************************************************************** 248171384Sjfv * vendor_info_array 249171384Sjfv * 250171384Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 251171384Sjfv * should load. 252171384Sjfv * 253185352Sjfv ***************************************************************************** 254171384Sjfv */ 255171384Sjfvtypedef struct _ixgbe_vendor_info_t { 256171384Sjfv unsigned int vendor_id; 257171384Sjfv unsigned int device_id; 258171384Sjfv unsigned int subvendor_id; 259171384Sjfv unsigned int subdevice_id; 260171384Sjfv unsigned int index; 261185352Sjfv} ixgbe_vendor_info_t; 262171384Sjfv 263251964Sjfv 264243718Sjfv/* This is used to get SFP+ module data */ 265243718Sjfvstruct ixgbe_i2c_req { 266243718Sjfv u8 dev_addr; 267243718Sjfv u8 offset; 268243718Sjfv u8 len; 269243718Sjfv u8 data[8]; 270243718Sjfv}; 271171384Sjfv 272171384Sjfvstruct ixgbe_tx_buf { 273243736Sjfv union ixgbe_adv_tx_desc *eop; 274171384Sjfv struct mbuf *m_head; 275171384Sjfv bus_dmamap_t map; 276171384Sjfv}; 277171384Sjfv 278171384Sjfvstruct ixgbe_rx_buf { 279243714Sjfv struct mbuf *buf; 280205720Sjfv struct mbuf *fmp; 281244514Sluigi bus_dmamap_t pmap; 282239940Sscottl u_int flags; 283239940Sscottl#define IXGBE_RX_COPY 0x01 284243714Sjfv uint64_t addr; 285171384Sjfv}; 286171384Sjfv 287171384Sjfv/* 288171384Sjfv * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 289171384Sjfv */ 290171384Sjfvstruct ixgbe_dma_alloc { 291171384Sjfv bus_addr_t dma_paddr; 292171384Sjfv caddr_t dma_vaddr; 293171384Sjfv bus_dma_tag_t dma_tag; 294171384Sjfv bus_dmamap_t dma_map; 295171384Sjfv bus_dma_segment_t dma_seg; 296171384Sjfv bus_size_t dma_size; 297171384Sjfv int dma_nseg; 298171384Sjfv}; 299171384Sjfv 300171384Sjfv/* 301205720Sjfv** Driver queue struct: this is the interrupt container 302205720Sjfv** for the associated tx and rx ring. 303205720Sjfv*/ 304205720Sjfvstruct ix_queue { 305205720Sjfv struct adapter *adapter; 306205720Sjfv u32 msix; /* This queue's MSIX vector */ 307205720Sjfv u32 eims; /* This queue's EIMS bit */ 308205720Sjfv u32 eitr_setting; 309283620Serj u32 me; 310205720Sjfv struct resource *res; 311205720Sjfv void *tag; 312283620Serj int busy; 313205720Sjfv struct tx_ring *txr; 314205720Sjfv struct rx_ring *rxr; 315205720Sjfv struct task que_task; 316205720Sjfv struct taskqueue *tq; 317205720Sjfv u64 irqs; 318205720Sjfv}; 319205720Sjfv 320205720Sjfv/* 321205720Sjfv * The transmit ring, one per queue 322171384Sjfv */ 323171384Sjfvstruct tx_ring { 324171384Sjfv struct adapter *adapter; 325179055Sjfv struct mtx tx_mtx; 326171384Sjfv u32 me; 327283620Serj u32 tail; 328283620Serj int busy; 329243729Sjfv union ixgbe_adv_tx_desc *tx_base; 330243729Sjfv struct ixgbe_tx_buf *tx_buffers; 331243729Sjfv struct ixgbe_dma_alloc txdma; 332243729Sjfv volatile u16 tx_avail; 333243729Sjfv u16 next_avail_desc; 334243729Sjfv u16 next_to_clean; 335243729Sjfv u16 process_limit; 336243729Sjfv u16 num_desc; 337179055Sjfv u32 txd_cmd; 338171384Sjfv bus_dma_tag_t txtag; 339185352Sjfv char mtx_name[16]; 340243725Sjfv#ifndef IXGBE_LEGACY_TX 341194875Sjfv struct buf_ring *br; 342240968Sjhb struct task txq_task; 343194875Sjfv#endif 344200239Sjfv#ifdef IXGBE_FDIR 345200239Sjfv u16 atr_sample; 346200239Sjfv u16 atr_count; 347200239Sjfv#endif 348205720Sjfv u32 bytes; /* used for AIM */ 349205720Sjfv u32 packets; 350179055Sjfv /* Soft Stats */ 351243729Sjfv unsigned long tso_tx; 352243729Sjfv unsigned long no_tx_map_avail; 353243729Sjfv unsigned long no_tx_dma_setup; 354205720Sjfv u64 no_desc_avail; 355185352Sjfv u64 total_packets; 356171384Sjfv}; 357171384Sjfv 358171384Sjfv 359171384Sjfv/* 360171384Sjfv * The Receive ring, one per rx queue 361171384Sjfv */ 362171384Sjfvstruct rx_ring { 363179055Sjfv struct adapter *adapter; 364179055Sjfv struct mtx rx_mtx; 365179055Sjfv u32 me; 366283620Serj u32 tail; 367179055Sjfv union ixgbe_adv_rx_desc *rx_base; 368179055Sjfv struct ixgbe_dma_alloc rxdma; 369179055Sjfv struct lro_ctrl lro; 370194875Sjfv bool lro_enabled; 371200239Sjfv bool hw_rsc; 372230775Sjfv bool vtag_strip; 373243729Sjfv u16 next_to_refresh; 374243729Sjfv u16 next_to_check; 375243729Sjfv u16 num_desc; 376243729Sjfv u16 mbuf_sz; 377243729Sjfv u16 process_limit; 378205720Sjfv char mtx_name[16]; 379179055Sjfv struct ixgbe_rx_buf *rx_buffers; 380244514Sluigi bus_dma_tag_t ptag; 381185352Sjfv 382185352Sjfv u32 bytes; /* Used for AIM calc */ 383205720Sjfv u32 packets; 384185352Sjfv 385171384Sjfv /* Soft stats */ 386179055Sjfv u64 rx_irq; 387239940Sscottl u64 rx_copies; 388185352Sjfv u64 rx_packets; 389185352Sjfv u64 rx_bytes; 390205720Sjfv u64 rx_discarded; 391200239Sjfv u64 rsc_num; 392200239Sjfv#ifdef IXGBE_FDIR 393200239Sjfv u64 flm; 394200239Sjfv#endif 395171384Sjfv}; 396171384Sjfv 397171384Sjfv/* Our adapter structure */ 398171384Sjfvstruct adapter { 399205720Sjfv struct ifnet *ifp; 400205720Sjfv struct ixgbe_hw hw; 401171384Sjfv 402171384Sjfv struct ixgbe_osdep osdep; 403205720Sjfv struct device *dev; 404171384Sjfv 405205720Sjfv struct resource *pci_mem; 406205720Sjfv struct resource *msix_mem; 407179055Sjfv 408171384Sjfv /* 409194875Sjfv * Interrupt resources: this set is 410194875Sjfv * either used for legacy, or for Link 411194875Sjfv * when doing MSIX 412171384Sjfv */ 413205720Sjfv void *tag; 414205720Sjfv struct resource *res; 415171384Sjfv 416205720Sjfv struct ifmedia media; 417205720Sjfv struct callout timer; 418205720Sjfv int msix; 419205720Sjfv int if_flags; 420179055Sjfv 421205720Sjfv struct mtx core_mtx; 422179055Sjfv 423205720Sjfv eventhandler_tag vlan_attach; 424205720Sjfv eventhandler_tag vlan_detach; 425194875Sjfv 426205720Sjfv u16 num_vlans; 427205720Sjfv u16 num_queues; 428194875Sjfv 429215911Sjfv /* 430215911Sjfv ** Shadow VFTA table, this is needed because 431215911Sjfv ** the real vlan filter table gets cleared during 432215911Sjfv ** a soft reset and the driver needs to be able 433215911Sjfv ** to repopulate it. 434215911Sjfv */ 435215911Sjfv u32 shadow_vfta[IXGBE_VFTA_SIZE]; 436215911Sjfv 437215911Sjfv /* Info about the interface */ 438205720Sjfv u32 optics; 439230775Sjfv u32 fc; /* local flow ctrl setting */ 440209609Sjfv int advertise; /* link speeds */ 441205720Sjfv bool link_active; 442205720Sjfv u16 max_frame_size; 443217593Sjfv u16 num_segs; 444205720Sjfv u32 link_speed; 445205720Sjfv bool link_up; 446283620Serj u32 vector; 447283620Serj u16 dmac; 448283620Serj bool eee_support; 449283620Serj bool eee_enabled; 450171384Sjfv 451283620Serj /* Power management-related */ 452283620Serj bool wol_support; 453283620Serj u32 wufc; 454283620Serj 455185352Sjfv /* Mbuf cluster size */ 456205720Sjfv u32 rx_mbuf_sz; 457171384Sjfv 458190873Sjfv /* Support for pluggable optics */ 459205720Sjfv bool sfp_probe; 460205720Sjfv struct task link_task; /* Link tasklet */ 461205720Sjfv struct task mod_task; /* SFP tasklet */ 462205720Sjfv struct task msf_task; /* Multispeed Fiber */ 463200239Sjfv#ifdef IXGBE_FDIR 464200239Sjfv int fdir_reinit; 465200239Sjfv struct task fdir_task; 466200239Sjfv#endif 467283620Serj struct task phy_task; /* PHY intr tasklet */ 468190873Sjfv struct taskqueue *tq; 469185352Sjfv 470171384Sjfv /* 471205720Sjfv ** Queues: 472205720Sjfv ** This is the irq holder, it has 473205720Sjfv ** and RX/TX pair or rings associated 474205720Sjfv ** with it. 475205720Sjfv */ 476205720Sjfv struct ix_queue *queues; 477205720Sjfv 478205720Sjfv /* 479171384Sjfv * Transmit rings: 480171384Sjfv * Allocated at run time, an array of rings. 481171384Sjfv */ 482205720Sjfv struct tx_ring *tx_rings; 483243729Sjfv u32 num_tx_desc; 484171384Sjfv 485171384Sjfv /* 486171384Sjfv * Receive rings: 487171384Sjfv * Allocated at run time, an array of rings. 488171384Sjfv */ 489205720Sjfv struct rx_ring *rx_rings; 490283620Serj u64 active_queues; 491243729Sjfv u32 num_rx_desc; 492171384Sjfv 493215914Sjfv /* Multicast array memory */ 494215914Sjfv u8 *mta; 495215914Sjfv 496251964Sjfv 497171384Sjfv /* Misc stats maintained by the driver */ 498205720Sjfv unsigned long dropped_pkts; 499205720Sjfv unsigned long mbuf_defrag_failed; 500205720Sjfv unsigned long mbuf_header_failed; 501205720Sjfv unsigned long mbuf_packet_failed; 502205720Sjfv unsigned long watchdog_events; 503205720Sjfv unsigned long link_irq; 504283620Serj union { 505283620Serj struct ixgbe_hw_stats pf; 506283620Serj struct ixgbevf_hw_stats vf; 507283620Serj } stats; 508283620Serj#if __FreeBSD_version >= 1100036 509283620Serj /* counter(9) stats */ 510283620Serj u64 ipackets; 511283620Serj u64 ierrors; 512283620Serj u64 opackets; 513283620Serj u64 oerrors; 514283620Serj u64 ibytes; 515283620Serj u64 obytes; 516283620Serj u64 imcasts; 517283620Serj u64 omcasts; 518283620Serj u64 iqdrops; 519283620Serj u64 noproto; 520283620Serj#endif 521171384Sjfv}; 522171384Sjfv 523251964Sjfv 524190873Sjfv/* Precision Time Sync (IEEE 1588) defines */ 525190873Sjfv#define ETHERTYPE_IEEE1588 0x88F7 526190873Sjfv#define PICOSECS_PER_TICK 20833 527190873Sjfv#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 528190873Sjfv#define IXGBE_ADVTXD_TSTAMP 0x00080000 529190873Sjfv 530190873Sjfv 531179055Sjfv#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 532179055Sjfv mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 533179055Sjfv#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 534200239Sjfv#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 535200239Sjfv#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 536179055Sjfv#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 537200239Sjfv#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 538200239Sjfv#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 539200239Sjfv#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 540179055Sjfv#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 541179055Sjfv#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 542179055Sjfv#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 543179055Sjfv#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 544179055Sjfv#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 545179055Sjfv 546251964Sjfv/* For backward compatibility */ 547251964Sjfv#if !defined(PCIER_LINK_STA) 548251964Sjfv#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 549251964Sjfv#endif 550179055Sjfv 551283620Serj/* Stats macros */ 552283620Serj#if __FreeBSD_version >= 1100036 553283620Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 554283620Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 555283620Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 556283620Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 557283620Serj#define IXGBE_SET_COLLISIONS(sc, count) 558283620Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 559283620Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 560283620Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 561283620Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 562283620Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 563283620Serj#else 564283620Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count) 565283620Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count) 566283620Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count) 567283620Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count) 568283620Serj#define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count) 569283620Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) 570283620Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) 571283620Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) 572283620Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) 573283620Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) 574283620Serj#endif 575283620Serj 576283620Serj/* External PHY register addresses */ 577283620Serj#define IXGBE_PHY_CURRENT_TEMP 0xC820 578283620Serj#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 579283620Serj 580283620Serj/* Sysctl help messages; displayed with sysctl -d */ 581283620Serj#define IXGBE_SYSCTL_DESC_ADV_SPEED \ 582283620Serj "\nControl advertised link speed using these flags:\n" \ 583283620Serj "\t0x1 - advertise 100M\n" \ 584283620Serj "\t0x2 - advertise 1G\n" \ 585283620Serj "\t0x4 - advertise 10G\n\n" \ 586283620Serj "\t100M is only supported on certain 10GBaseT adapters.\n" 587283620Serj 588283620Serj#define IXGBE_SYSCTL_DESC_SET_FC \ 589283620Serj "\nSet flow control mode using these values:\n" \ 590283620Serj "\t0 - off\n" \ 591283620Serj "\t1 - rx pause\n" \ 592283620Serj "\t2 - tx pause\n" \ 593283620Serj "\t3 - tx and rx pause" 594283620Serj 595190873Sjfvstatic inline bool 596190873Sjfvixgbe_is_sfp(struct ixgbe_hw *hw) 597190873Sjfv{ 598190873Sjfv switch (hw->phy.type) { 599190873Sjfv case ixgbe_phy_sfp_avago: 600190873Sjfv case ixgbe_phy_sfp_ftl: 601190873Sjfv case ixgbe_phy_sfp_intel: 602190873Sjfv case ixgbe_phy_sfp_unknown: 603205720Sjfv case ixgbe_phy_sfp_passive_tyco: 604205720Sjfv case ixgbe_phy_sfp_passive_unknown: 605283620Serj case ixgbe_phy_qsfp_passive_unknown: 606283620Serj case ixgbe_phy_qsfp_active_unknown: 607283620Serj case ixgbe_phy_qsfp_intel: 608283620Serj case ixgbe_phy_qsfp_unknown: 609190873Sjfv return TRUE; 610190873Sjfv default: 611190873Sjfv return FALSE; 612190873Sjfv } 613190873Sjfv} 614190873Sjfv 615208762Sjfv/* Workaround to make 8.0 buildable */ 616217129Sjfv#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 617208762Sjfvstatic __inline int 618208762Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 619208762Sjfv{ 620208762Sjfv#ifdef ALTQ 621208762Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 622208762Sjfv return (1); 623208762Sjfv#endif 624208762Sjfv return (!buf_ring_empty(br)); 625208762Sjfv} 626208762Sjfv#endif 627208762Sjfv 628221041Sjfv/* 629221041Sjfv** Find the number of unrefreshed RX descriptors 630221041Sjfv*/ 631221041Sjfvstatic inline u16 632221041Sjfvixgbe_rx_unrefreshed(struct rx_ring *rxr) 633221041Sjfv{ 634221041Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 635221041Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 636221041Sjfv else 637243729Sjfv return ((rxr->num_desc + rxr->next_to_check) - 638221041Sjfv rxr->next_to_refresh - 1); 639221041Sjfv} 640221041Sjfv 641283620Serj/* 642283620Serj** This checks for a zero mac addr, something that will be likely 643283620Serj** unless the Admin on the Host has created one. 644283620Serj*/ 645283620Serjstatic inline bool 646283620Serjixv_check_ether_addr(u8 *addr) 647283620Serj{ 648283620Serj bool status = TRUE; 649283620Serj 650283620Serj if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 651283620Serj addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 652283620Serj status = FALSE; 653283620Serj return (status); 654283620Serj} 655283620Serj 656283620Serj/* Shared Prototypes */ 657283620Serj 658283620Serj#ifdef IXGBE_LEGACY_TX 659283620Serjvoid ixgbe_start(struct ifnet *); 660283620Serjvoid ixgbe_start_locked(struct tx_ring *, struct ifnet *); 661283620Serj#else /* ! IXGBE_LEGACY_TX */ 662283620Serjint ixgbe_mq_start(struct ifnet *, struct mbuf *); 663283620Serjint ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); 664283620Serjvoid ixgbe_qflush(struct ifnet *); 665283620Serjvoid ixgbe_deferred_mq_start(void *, int); 666283620Serj#endif /* IXGBE_LEGACY_TX */ 667283620Serj 668283620Serjint ixgbe_allocate_queues(struct adapter *); 669283620Serjint ixgbe_allocate_transmit_buffers(struct tx_ring *); 670283620Serjint ixgbe_setup_transmit_structures(struct adapter *); 671283620Serjvoid ixgbe_free_transmit_structures(struct adapter *); 672283620Serjint ixgbe_allocate_receive_buffers(struct rx_ring *); 673283620Serjint ixgbe_setup_receive_structures(struct adapter *); 674283620Serjvoid ixgbe_free_receive_structures(struct adapter *); 675283620Serjvoid ixgbe_txeof(struct tx_ring *); 676283620Serjbool ixgbe_rxeof(struct ix_queue *); 677283620Serj 678283620Serjint ixgbe_dma_malloc(struct adapter *, 679283620Serj bus_size_t, struct ixgbe_dma_alloc *, int); 680283620Serjvoid ixgbe_dma_free(struct adapter *, struct ixgbe_dma_alloc *); 681171384Sjfv#endif /* _IXGBE_H_ */ 682