138774Snsouch/*-
238774Snsouch * Copyright (c) 1998 Nicolas Souchu
338774Snsouch * All rights reserved.
438774Snsouch *
538774Snsouch * Redistribution and use in source and binary forms, with or without
638774Snsouch * modification, are permitted provided that the following conditions
738774Snsouch * are met:
838774Snsouch * 1. Redistributions of source code must retain the above copyright
938774Snsouch *    notice, this list of conditions and the following disclaimer.
1038774Snsouch * 2. Redistributions in binary form must reproduce the above copyright
1138774Snsouch *    notice, this list of conditions and the following disclaimer in the
1238774Snsouch *    documentation and/or other materials provided with the distribution.
1338774Snsouch *
1438774Snsouch * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1538774Snsouch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1638774Snsouch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1738774Snsouch * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
1838774Snsouch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
1938774Snsouch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2038774Snsouch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2138774Snsouch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2238774Snsouch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2338774Snsouch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2438774Snsouch * SUCH DAMAGE.
2538774Snsouch *
2650477Speter * $FreeBSD: releng/10.2/sys/dev/iicbus/iicbus.h 276278 2014-12-27 02:37:52Z ian $
2738774Snsouch *
2838774Snsouch */
2938774Snsouch#ifndef __IICBUS_H
3038774Snsouch#define __IICBUS_H
3138774Snsouch
32181304Sjhb#include <sys/_lock.h>
33181304Sjhb#include <sys/_mutex.h>
34181304Sjhb
35167854Simp#define IICBUS_IVAR(d) (struct iicbus_ivar *) device_get_ivars(d)
36167854Simp#define IICBUS_SOFTC(d) (struct iicbus_softc *) device_get_softc(d)
3738774Snsouch
38167854Simpstruct iicbus_softc
39167854Simp{
40167854Simp	device_t dev;		/* Myself */
4138774Snsouch	device_t owner;		/* iicbus owner device structure */
4242442Snsouch	u_char started;		/* address of the 'started' slave
4342442Snsouch				 * 0 if no start condition succeeded */
44228257Sadrian	u_char strict;		/* deny operations that violate the
45228257Sadrian				 * I2C protocol */
46181304Sjhb	struct mtx lock;
47276278Sian	u_int bus_freq;		/* Configured bus Hz. */
4838774Snsouch};
4938774Snsouch
50167854Simpstruct iicbus_ivar
51167854Simp{
52167854Simp	uint32_t	addr;
53274028Skib	bool		nostop;
54167854Simp};
55167854Simp
56167854Simpenum {
57274028Skib	IICBUS_IVAR_ADDR,		/* Address or base address */
58274028Skib	IICBUS_IVAR_NOSTOP,		/* nostop defaults */
59167854Simp};
60167854Simp
61167854Simp#define IICBUS_ACCESSOR(A, B, T)					\
62181304Sjhb	__BUS_ACCESSOR(iicbus, A, IICBUS, B, T)
63167854Simp
64167854SimpIICBUS_ACCESSOR(addr,		ADDR,		uint32_t)
65274028SkibIICBUS_ACCESSOR(nostop,		NOSTOP,		bool)
66167854Simp
67181304Sjhb#define	IICBUS_LOCK(sc)			mtx_lock(&(sc)->lock)
68181304Sjhb#define	IICBUS_UNLOCK(sc)      		mtx_unlock(&(sc)->lock)
69181304Sjhb#define	IICBUS_ASSERT_LOCKED(sc)       	mtx_assert(&(sc)->lock, MA_OWNED)
70181304Sjhb
71276278Sianint  iicbus_generic_intr(device_t dev, int event, char *buf);
72276278Sianvoid iicbus_init_frequency(device_t dev, u_int bus_freq);
7338774Snsouch
74160372Simpextern driver_t iicbus_driver;
75160372Simpextern devclass_t iicbus_devclass;
76160372Simp
7738774Snsouch#endif
78