upd7210.h revision 150153
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/ieee488/upd7210.h 150153 2005-09-15 13:07:38Z phk $ 27 * 28 * Locating an actual �PD7210 data book has proven quite impossible for me. 29 * There are a fair number of newer chips which are supersets of the �PD7210 30 * but they are particular eager to comprehensively mark what the extensions 31 * are and what is in the base set. Some even give the registers and their 32 * bits new names. 33 * 34 * The following information is based on a description of the �PD7210 found 35 * in an old manual for a VME board which used the chip. 36 */ 37 38#ifndef _DEV_IEEE488_UPD7210_H_ 39#define _DEV_IEEE488_UPD7210_H_ 40#ifdef _KERNEL 41 42struct upd7210; 43struct ibfoo; 44 45/* upd7210 interface definitions for HW drivers */ 46 47typedef int upd7210_irq_t(struct upd7210 *, int); 48 49struct upd7210 { 50 bus_space_handle_t reg_handle[8]; 51 bus_space_tag_t reg_tag[8]; 52 u_int reg_offset[8]; 53 int dmachan; 54 int unit; 55 56 /* private stuff */ 57 struct mtx mutex; 58 uint8_t rreg[8]; 59 uint8_t wreg[8 + 8]; 60 61 upd7210_irq_t *irq; 62 63 int busy; 64 u_char *buf; 65 size_t bufsize; 66 u_int buf_wp; 67 u_int buf_rp; 68 struct cdev *cdev; 69 70 struct ibfoo *ibfoo; 71}; 72 73#ifdef UPD7210_HW_DRIVER 74void upd7210intr(void *); 75void upd7210attach(struct upd7210 *); 76void upd7210detach(struct upd7210 *); 77#endif 78 79#ifdef UPD7210_SW_DRIVER 80 81/* upd7210 hardware definitions. */ 82 83/* Write registers */ 84enum upd7210_wreg { 85 CDOR = 0, /* Command/Data Out Register */ 86 IMR1 = 1, /* Interrupt Mask Register 1 */ 87 IMR2 = 2, /* Interrupt Mask Register 2 */ 88 SPMR = 3, /* Serial Poll Mode Register */ 89 ADMR = 4, /* ADdress Mode Register */ 90 AUXMR = 5, /* AUXilliary Mode Register */ 91 ICR = 5, /* Internal Counter Register */ 92 PPR = 5, /* Parallel Poll Register */ 93 AUXRA = 5, /* AUXilliary Register A */ 94 AUXRB = 5, /* AUXilliary Register B */ 95 AUXRE = 5, /* AUXilliary Register E */ 96 ADR = 6, /* ADdress Register */ 97 EOSR = 7, /* End-Of-String Register */ 98}; 99 100/* Read registers */ 101enum upd7210_rreg { 102 DIR = 0, /* Data In Register */ 103 ISR1 = 1, /* Interrupt Status Register 1 */ 104 ISR2 = 2, /* Interrupt Status Register 2 */ 105 SPSR = 3, /* Serial Poll Status Register */ 106 ADSR = 4, /* ADdress Status Register */ 107 CPTR = 5, /* Command Pass Though Register */ 108 ADR0 = 6, /* ADdress Register 0 */ 109 ADR1 = 7, /* ADdress Register 1 */ 110}; 111 112/* Bits for ISR1 and IMR1 */ 113#define IXR1_DI (1 << 0) /* Data In */ 114#define IXR1_DO (1 << 1) /* Data Out */ 115#define IXR1_ERR (1 << 2) /* Error */ 116#define IXR1_DEC (1 << 3) /* Device Clear */ 117#define IXR1_ENDRX (1 << 4) /* End Received */ 118#define IXR1_DET (1 << 5) /* Device Execute Trigger */ 119#define IXR1_APT (1 << 6) /* Address Pass-Through */ 120#define IXR1_CPT (1 << 7) /* Command Pass-Through */ 121 122/* Bits for ISR2 and IMR2 */ 123#define IXR2_ADSC (1 << 0) /* Addressed Status Change */ 124#define IXR2_REMC (1 << 1) /* Remote Change */ 125#define IXR2_LOKC (1 << 2) /* Lockout Change */ 126#define IXR2_CO (1 << 3) /* Command Out */ 127#define ISR2_REM (1 << 4) /* Remove */ 128#define IMR2_DMAI (1 << 4) /* DMA In Enable */ 129#define ISR2_LOK (1 << 5) /* Lockout */ 130#define IMR2_DMAO (1 << 5) /* DMA Out Enable */ 131#define IXR2_SRQI (1 << 6) /* Service Request Input */ 132#define ISR2_INT (1 << 7) /* Interrupt */ 133 134#define SPSR_PEND (1 << 6) /* Pending */ 135#define SPMR_RSV (1 << 6) /* Request SerVice */ 136 137#define ADSR_MJMN (1 << 0) /* MaJor MiNor */ 138#define ADSR_TA (1 << 1) /* Talker Active */ 139#define ADSR_LA (1 << 2) /* Listener Active */ 140#define ADSR_TPAS (1 << 3) /* Talker Primary Addr. State */ 141#define ADSR_LPAS (1 << 4) /* Listener Primary Addr. State */ 142#define ADSR_SPMS (1 << 5) /* Serial Poll Mode State */ 143#define ADSR_ATN (1 << 6) /* Attention */ 144#define ADSR_CIC (1 << 7) /* Controller In Charge */ 145 146#define ADMR_ADM0 (1 << 0) /* Address Mode 0 */ 147#define ADMR_ADM1 (1 << 1) /* Address Mode 1 */ 148#define ADMR_TRM0 (1 << 4) /* Transmit/Receive Mode 0 */ 149#define ADMR_TRM1 (1 << 5) /* Transmit/Receive Mode 1 */ 150#define ADMR_LON (1 << 6) /* Listen Only */ 151#define ADMR_TON (1 << 7) /* Talk Only */ 152 153/* Constant part of overloaded write registers */ 154#define C_ICR 0x20 155#define C_PPR 0x60 156#define C_AUXA 0x80 157#define C_AUXB 0xa0 158#define C_AUXE 0xc0 159 160#define AUXMR_PON 0x00 /* Immediate Execute pon */ 161#define AUXMR_CPP 0x01 /* Clear Parallel Poll */ 162#define AUXMR_CRST 0x02 /* Chip Reset */ 163#define AUXMR_RFD 0x03 /* Finish Handshake */ 164#define AUXMR_TRIG 0x04 /* Trigger */ 165#define AUXMR_RTL 0x05 /* Return to local */ 166#define AUXMR_SEOI 0x06 /* Send EOI */ 167#define AUXMR_NVSA 0x07 /* Non-Valid Secondary cmd/addr */ 168 /* 0x08 undefined/unknown */ 169#define AUXMR_SPP 0x09 /* Set Parallel Poll */ 170 /* 0x0a undefined/unknown */ 171 /* 0x0b undefined/unknown */ 172 /* 0x0c undefined/unknown */ 173 /* 0x0d undefined/unknown */ 174 /* 0x0e undefined/unknown */ 175#define AUXMR_VSA 0x0f /* Valid Secondary cmd/addr */ 176#define AUXMR_GTS 0x10 /* Go to Standby */ 177#define AUXMR_TCA 0x11 /* Take Control Async (pulsed) */ 178#define AUXMR_TCS 0x12 /* Take Control Synchronously */ 179#define AUXMR_LISTEN 0x13 /* Listen */ 180#define AUXMR_DSC 0x14 /* Disable System Control */ 181 /* 0x15 undefined/unknown */ 182#define AUXMR_SIFC 0x16 /* Set IFC */ 183#define AUXMR_CREN 0x17 /* Clear REN */ 184 /* 0x18 undefined/unknown */ 185 /* 0x19 undefined/unknown */ 186#define AUXMR_TCSE 0x1a /* Take Control Sync on End */ 187#define AUXMR_LCM 0x1b /* Listen Continuously Mode */ 188#define AUXMR_LUNL 0x1c /* Local Unlisten */ 189#define AUXMR_EPP 0x1d /* Execute Parallel Poll */ 190#define AUXMR_CIFC 0x1e /* Clear IFC */ 191#define AUXMR_SREN 0x1f /* Set REN */ 192 193#define PPR_U (1 << 4) /* Unconfigure */ 194#define PPR_S (1 << 3) /* Status Polarity */ 195 196#define AUXA_HLDA (1 << 0) /* Holdoff on All */ 197#define AUXA_HLDE (1 << 1) /* Holdoff on END */ 198#define AUXA_REOS (1 << 2) /* End on EOS received */ 199#define AUXA_XEOS (1 << 3) /* Transmit END with EOS */ 200#define AUXA_BIN (1 << 4) /* Binary */ 201 202#define AUXB_CPTE (1 << 0) /* Cmd Pass Through Enable */ 203#define AUXB_SPEOI (1 << 1) /* Send Serial Poll EOI */ 204#define AUXB_TRI (1 << 2) /* Three-State Timing */ 205#define AUXB_INV (1 << 3) /* Invert */ 206#define AUXB_ISS (1 << 4) /* Individual Status Select */ 207 208#define AUXE_DHDT (1 << 0) /* DAC Holdoff on DTAS */ 209#define AUXE_DHDC (1 << 1) /* DAC Holdoff on DCAS */ 210 211#define ADR0_DL0 (1 << 5) /* Disable Listener 0 */ 212#define ADR0_DT0 (1 << 6) /* Disable Talker 0 */ 213 214#define ADR_DL (1 << 5) /* Disable Listener */ 215#define ADR_DT (1 << 6) /* Disable Talker */ 216#define ADR_ARS (1 << 7) /* Address Register Select */ 217 218#define ADR1_DL1 (1 << 5) /* Disable Listener 1 */ 219#define ADR1_DT1 (1 << 6) /* Disable Talker 1 */ 220#define ADR1_EOI (1 << 7) /* End or Identify */ 221 222/* Stuff from software drivers */ 223extern struct cdevsw gpib_ib_cdevsw; 224 225/* Stuff from upd7210.c */ 226void upd7210_print_isr(u_int isr1, u_int isr2); 227u_int upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg); 228void upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val); 229int upd7210_take_ctrl_async(struct upd7210 *u); 230int upd7210_goto_standby(struct upd7210 *u); 231 232#endif /* UPD7210_SW_DRIVER */ 233 234#endif /* _KERNEL */ 235#endif /* _DEV_IEEE488_UPD7210_H_ */ 236