upd7210.h revision 148920
190792Sgshapiro/*- 2261363Sgshapiro * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 390792Sgshapiro * All rights reserved. 490792Sgshapiro * 590792Sgshapiro * Redistribution and use in source and binary forms, with or without 690792Sgshapiro * modification, are permitted provided that the following conditions 790792Sgshapiro * are met: 890792Sgshapiro * 1. Redistributions of source code must retain the above copyright 990792Sgshapiro * notice, this list of conditions and the following disclaimer. 1090792Sgshapiro * 2. Redistributions in binary form must reproduce the above copyright 1190792Sgshapiro * notice, this list of conditions and the following disclaimer in the 1290792Sgshapiro * documentation and/or other materials provided with the distribution. 1390792Sgshapiro * 1490792Sgshapiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1590792Sgshapiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16266692Sgshapiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1790792Sgshapiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1890792Sgshapiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19157001Sgshapiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2090792Sgshapiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2190792Sgshapiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2290792Sgshapiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2390792Sgshapiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2490792Sgshapiro * SUCH DAMAGE. 2590792Sgshapiro * 2690792Sgshapiro * $FreeBSD: head/sys/dev/ieee488/upd7210.h 148920 2005-08-10 07:10:02Z obrien $ 27141858Sgshapiro * 28141858Sgshapiro * Locating an actual �PD7210 data book has proven quite impossible for me. 2990792Sgshapiro * There are a fair number of newer chips which are supersets of the �PD7210 3090792Sgshapiro * but they are particular eager to comprehensively mark what the extensions 3190792Sgshapiro * are and what is in the base set. Some even give the registers and their 3290792Sgshapiro * bits new names. 3390792Sgshapiro * 3490792Sgshapiro * The following information is based on a description of the �PD7210 found 3590792Sgshapiro * in an old manual for a VME board which used the chip. 3690792Sgshapiro */ 3790792Sgshapiro 3890792Sgshapiro#ifndef _DEV_IEEE488_UPD7210_H_ 3990792Sgshapiro#define _DEV_IEEE488_UPD7210_H_ 4090792Sgshapiro#ifdef _KERNEL 4190792Sgshapiro 4290792Sgshapirostruct upd7210; 4390792Sgshapirostruct ibfoo; 4490792Sgshapiro 4590792Sgshapiro/* upd7210 interface definitions for HW drivers */ 4690792Sgshapiro 4790792Sgshapirotypedef int upd7210_irq_t(struct upd7210 *, int); 4890792Sgshapiro 4990792Sgshapirostruct upd7210 { 5090792Sgshapiro bus_space_handle_t reg_handle[8]; 5190792Sgshapiro bus_space_tag_t reg_tag[8]; 5290792Sgshapiro u_int reg_offset[8]; 5390792Sgshapiro int dmachan; 5490792Sgshapiro 5590792Sgshapiro /* private stuff */ 5690792Sgshapiro struct mtx mutex; 5790792Sgshapiro uint8_t rreg[8]; 5890792Sgshapiro uint8_t wreg[8 + 8]; 5990792Sgshapiro 6090792Sgshapiro upd7210_irq_t *irq; 6190792Sgshapiro 6290792Sgshapiro int busy; 6390792Sgshapiro u_char *buf; 6490792Sgshapiro size_t bufsize; 6590792Sgshapiro u_int buf_wp; 6690792Sgshapiro u_int buf_rp; 6790792Sgshapiro struct cdev *cdev; 6890792Sgshapiro 6990792Sgshapiro struct ibfoo *ibfoo; 7090792Sgshapiro}; 7190792Sgshapiro 7290792Sgshapiro#ifdef UPD7210_HW_DRIVER 7390792Sgshapirovoid upd7210intr(void *); 7490792Sgshapirovoid upd7210attach(struct upd7210 *); 7590792Sgshapiro#endif 7690792Sgshapiro 7790792Sgshapiro#ifdef UPD7210_SW_DRIVER 7890792Sgshapiro 7990792Sgshapiro/* upd7210 hardware definitions. */ 8090792Sgshapiro 8190792Sgshapiro/* Write registers */ 8290792Sgshapiroenum upd7210_wreg { 8390792Sgshapiro CDOR = 0, /* Command/Data Out Register */ 8490792Sgshapiro IMR1 = 1, /* Interrupt Mask Register 1 */ 8590792Sgshapiro IMR2 = 2, /* Interrupt Mask Register 2 */ 8690792Sgshapiro SPMR = 3, /* Serial Poll Mode Register */ 8790792Sgshapiro ADMR = 4, /* ADdress Mode Register */ 8890792Sgshapiro AUXMR = 5, /* AUXilliary Mode Register */ 8990792Sgshapiro ICR = 5, /* Internal Counter Register */ 9090792Sgshapiro PPR = 5, /* Parallel Poll Register */ 9190792Sgshapiro AUXRA = 5, /* AUXilliary Register A */ 9290792Sgshapiro AUXRB = 5, /* AUXilliary Register B */ 9390792Sgshapiro AUXRE = 5, /* AUXilliary Register E */ 9490792Sgshapiro ADR = 6, /* ADdress Register */ 9590792Sgshapiro EOSR = 7, /* End-Of-String Register */ 9690792Sgshapiro}; 9790792Sgshapiro 9890792Sgshapiro/* Read registers */ 9990792Sgshapiroenum upd7210_rreg { 10090792Sgshapiro DIR = 0, /* Data In Register */ 10190792Sgshapiro ISR1 = 1, /* Interrupt Status Register 1 */ 10290792Sgshapiro ISR2 = 2, /* Interrupt Status Register 2 */ 10390792Sgshapiro SPSR = 3, /* Serial Poll Status Register */ 10490792Sgshapiro ADSR = 4, /* ADdress Status Register */ 10590792Sgshapiro CPTR = 5, /* Command Pass Though Register */ 10690792Sgshapiro ADR0 = 6, /* ADdress Register 0 */ 10790792Sgshapiro ADR1 = 7, /* ADdress Register 1 */ 10890792Sgshapiro}; 10990792Sgshapiro 11090792Sgshapiro/* Bits for ISR1 and IMR1 */ 11190792Sgshapiro#define IXR1_DI (1 << 0) /* Data In */ 11290792Sgshapiro#define IXR1_DO (1 << 1) /* Data Out */ 11390792Sgshapiro#define IXR1_ERR (1 << 2) /* Error */ 11490792Sgshapiro#define IXR1_DEC (1 << 3) /* Device Clear */ 11590792Sgshapiro#define IXR1_ENDRX (1 << 4) /* End Received */ 11690792Sgshapiro#define IXR1_DET (1 << 5) /* Device Execute Trigger */ 11790792Sgshapiro#define IXR1_APT (1 << 6) /* Address Pass-Through */ 11890792Sgshapiro#define IXR1_CPT (1 << 7) /* Command Pass-Through */ 11990792Sgshapiro 12090792Sgshapiro/* Bits for ISR2 and IMR2 */ 12190792Sgshapiro#define IXR2_ADSC (1 << 0) /* Addressed Status Change */ 12290792Sgshapiro#define IXR2_REMC (1 << 1) /* Remote Change */ 12390792Sgshapiro#define IXR2_LOKC (1 << 2) /* Lockout Change */ 12490792Sgshapiro#define IXR2_CO (1 << 3) /* Command Out */ 12590792Sgshapiro#define ISR2_REM (1 << 4) /* Remove */ 12690792Sgshapiro#define IMR2_DMAI (1 << 4) /* DMA In Enable */ 12790792Sgshapiro#define ISR2_LOK (1 << 5) /* Lockout */ 12890792Sgshapiro#define IMR2_DMAO (1 << 5) /* DMA Out Enable */ 12990792Sgshapiro#define IXR2_SRQI (1 << 6) /* Service Request Input */ 13090792Sgshapiro#define ISR2_INT (1 << 7) /* Interrupt */ 13190792Sgshapiro 13290792Sgshapiro#define SPSR_PEND (1 << 6) /* Pending */ 13390792Sgshapiro#define SPMR_RSV (1 << 6) /* Request SerVice */ 13490792Sgshapiro 13590792Sgshapiro#define ADSR_MJMN (1 << 0) /* MaJor MiNor */ 13690792Sgshapiro#define ADSR_TA (1 << 1) /* Talker Active */ 13790792Sgshapiro#define ADSR_LA (1 << 2) /* Listener Active */ 13890792Sgshapiro#define ADSR_TPAS (1 << 3) /* Talker Primary Addr. State */ 13990792Sgshapiro#define ADSR_LPAS (1 << 4) /* Listener Primary Addr. State */ 14090792Sgshapiro#define ADSR_SPMS (1 << 5) /* Serial Poll Mode State */ 14190792Sgshapiro#define ADSR_ATN (1 << 6) /* Attention */ 14290792Sgshapiro#define ADSR_CIC (1 << 7) /* Controller In Charge */ 14390792Sgshapiro 14490792Sgshapiro#define ADMR_ADM0 (1 << 0) /* Address Mode 0 */ 14590792Sgshapiro#define ADMR_ADM1 (1 << 1) /* Address Mode 1 */ 14690792Sgshapiro#define ADMR_TRM0 (1 << 4) /* Transmit/Receive Mode 0 */ 14790792Sgshapiro#define ADMR_TRM1 (1 << 5) /* Transmit/Receive Mode 1 */ 14890792Sgshapiro#define ADMR_LON (1 << 6) /* Listen Only */ 14990792Sgshapiro#define ADMR_TON (1 << 7) /* Talk Only */ 15090792Sgshapiro 15190792Sgshapiro/* Constant part of overloaded write registers */ 15290792Sgshapiro#define C_ICR 0x20 15390792Sgshapiro#define C_PPR 0x60 15490792Sgshapiro#define C_AUXA 0x80 15590792Sgshapiro#define C_AUXB 0xa0 15690792Sgshapiro#define C_AUXE 0xc0 15790792Sgshapiro 15890792Sgshapiro#define AUXMR_PON 0x00 /* Immediate Execute pon */ 15990792Sgshapiro#define AUXMR_CPP 0x01 /* Clear Parallel Poll */ 16090792Sgshapiro#define AUXMR_CRST 0x02 /* Chip Reset */ 16190792Sgshapiro#define AUXMR_RFD 0x03 /* Finish Handshake */ 16290792Sgshapiro#define AUXMR_TRIG 0x04 /* Trigger */ 16390792Sgshapiro#define AUXMR_RTL 0x05 /* Return to local */ 16490792Sgshapiro#define AUXMR_SEOI 0x06 /* Send EOI */ 16590792Sgshapiro#define AUXMR_NVSA 0x07 /* Non-Valid Secondary cmd/addr */ 16690792Sgshapiro /* 0x08 undefined/unknown */ 16790792Sgshapiro#define AUXMR_SPP 0x09 /* Set Parallel Poll */ 16890792Sgshapiro /* 0x0a undefined/unknown */ 16990792Sgshapiro /* 0x0b undefined/unknown */ 17090792Sgshapiro /* 0x0c undefined/unknown */ 17190792Sgshapiro /* 0x0d undefined/unknown */ 17290792Sgshapiro /* 0x0e undefined/unknown */ 17390792Sgshapiro#define AUXMR_VSA 0x0f /* Valid Secondary cmd/addr */ 17490792Sgshapiro#define AUXMR_GTS 0x10 /* Go to Standby */ 17590792Sgshapiro#define AUXMR_TCA 0x11 /* Take Control Async (pulsed) */ 17690792Sgshapiro#define AUXMR_TCS 0x12 /* Take Control Synchronously */ 17790792Sgshapiro#define AUXMR_LISTEN 0x13 /* Listen */ 17890792Sgshapiro#define AUXMR_DSC 0x14 /* Disable System Control */ 17990792Sgshapiro /* 0x15 undefined/unknown */ 18090792Sgshapiro#define AUXMR_SIFC 0x16 /* Set IFC */ 18190792Sgshapiro#define AUXMR_CREN 0x17 /* Clear REN */ 18290792Sgshapiro /* 0x18 undefined/unknown */ 18390792Sgshapiro /* 0x19 undefined/unknown */ 18490792Sgshapiro#define AUXMR_TCSE 0x1a /* Take Control Sync on End */ 18590792Sgshapiro#define AUXMR_LCM 0x1b /* Listen Continuously Mode */ 18690792Sgshapiro#define AUXMR_LUNL 0x1c /* Local Unlisten */ 18790792Sgshapiro#define AUXMR_EPP 0x1d /* Execute Parallel Poll */ 18890792Sgshapiro#define AUXMR_CIFC 0x1e /* Clear IFC */ 18990792Sgshapiro#define AUXMR_SREN 0x1f /* Set REN */ 19090792Sgshapiro 19190792Sgshapiro#define PPR_U (1 << 4) /* Unconfigure */ 19290792Sgshapiro#define PPR_S (1 << 3) /* Status Polarity */ 19390792Sgshapiro 19490792Sgshapiro#define AUXA_HLDA (1 << 0) /* Holdoff on All */ 19590792Sgshapiro#define AUXA_HLDE (1 << 1) /* Holdoff on END */ 19690792Sgshapiro#define AUXA_REOS (1 << 2) /* End on EOS received */ 19790792Sgshapiro#define AUXA_XEOS (1 << 3) /* Transmit END with EOS */ 19890792Sgshapiro#define AUXA_BIN (1 << 4) /* Binary */ 19990792Sgshapiro 20090792Sgshapiro#define AUXB_CPTE (1 << 0) /* Cmd Pass Through Enable */ 20190792Sgshapiro#define AUXB_SPEOI (1 << 1) /* Send Serial Poll EOI */ 20290792Sgshapiro#define AUXB_TRI (1 << 2) /* Three-State Timing */ 20390792Sgshapiro#define AUXB_INV (1 << 3) /* Invert */ 20490792Sgshapiro#define AUXB_ISS (1 << 4) /* Individual Status Select */ 20590792Sgshapiro 20690792Sgshapiro#define AUXE_DHDT (1 << 0) /* DAC Holdoff on DTAS */ 20790792Sgshapiro#define AUXE_DHDC (1 << 1) /* DAC Holdoff on DCAS */ 20890792Sgshapiro 20990792Sgshapiro#define ADR0_DL0 (1 << 5) /* Disable Listener 0 */ 21090792Sgshapiro#define ADR0_DT0 (1 << 6) /* Disable Talker 0 */ 21190792Sgshapiro 21290792Sgshapiro#define ADR_DL (1 << 5) /* Disable Listener */ 21390792Sgshapiro#define ADR_DT (1 << 6) /* Disable Talker */ 21490792Sgshapiro#define ADR_ARS (1 << 7) /* Address Register Select */ 21590792Sgshapiro 21690792Sgshapiro#define ADR1_DL1 (1 << 5) /* Disable Listener 1 */ 21790792Sgshapiro#define ADR1_DT1 (1 << 6) /* Disable Talker 1 */ 21890792Sgshapiro#define ADR1_EOI (1 << 7) /* End or Identify */ 21990792Sgshapiro 22090792Sgshapiro/* Stuff from software drivers */ 22190792Sgshapiroextern struct cdevsw gpib_ib_cdevsw; 22290792Sgshapiro 22390792Sgshapiro/* Stuff from upd7210.c */ 22490792Sgshapirovoid upd7210_print_isr(u_int isr1, u_int isr2); 22590792Sgshapirou_int upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg); 22690792Sgshapirovoid upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val); 22790792Sgshapiroint upd7210_take_ctrl_async(struct upd7210 *u); 22890792Sgshapiroint upd7210_goto_standby(struct upd7210 *u); 22990792Sgshapiro 23090792Sgshapiro#endif /* UPD7210_SW_DRIVER */ 23190792Sgshapiro 23290792Sgshapiro#endif /* _KERNEL */ 23390792Sgshapiro#endif /* _DEV_IEEE488_UPD7210_H_ */ 23490792Sgshapiro