ichwd.h revision 244977
1139749Simp/*- 2129124Sdes * Copyright (c) 2004 Texas A&M University 3129124Sdes * All rights reserved. 4129124Sdes * 5129124Sdes * Developer: Wm. Daryl Hawkins 6129124Sdes * 7129124Sdes * Redistribution and use in source and binary forms, with or without 8129124Sdes * modification, are permitted provided that the following conditions 9129124Sdes * are met: 10129124Sdes * 1. Redistributions of source code must retain the above copyright 11129124Sdes * notice, this list of conditions and the following disclaimer. 12129124Sdes * 2. Redistributions in binary form must reproduce the above copyright 13129124Sdes * notice, this list of conditions and the following disclaimer in the 14129124Sdes * documentation and/or other materials provided with the distribution. 15129124Sdes * 16129124Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17129124Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18129124Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19129124Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20129124Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21129124Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22129124Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23129124Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24129124Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25129124Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26129124Sdes * SUCH DAMAGE. 27129124Sdes * 28129124Sdes * $FreeBSD: head/sys/dev/ichwd/ichwd.h 244977 2013-01-02 21:45:20Z jfv $ 29129124Sdes */ 30129124Sdes 31129124Sdes#ifndef _ICHWD_H_ 32129124Sdes#define _ICHWD_H_ 33129124Sdes 34129124Sdesstruct ichwd_device { 35129124Sdes uint16_t device; 36129124Sdes char *desc; 37171820Sdes unsigned int version; 38129124Sdes}; 39129124Sdes 40129124Sdesstruct ichwd_softc { 41129124Sdes device_t device; 42171820Sdes device_t ich; 43175012Sdes int ich_version; 44129124Sdes 45129124Sdes int active; 46129124Sdes unsigned int timeout; 47129124Sdes 48221015Sattilio int smi_enabled; 49129124Sdes int smi_rid; 50129124Sdes struct resource *smi_res; 51129124Sdes 52129124Sdes int tco_rid; 53129124Sdes struct resource *tco_res; 54129124Sdes 55171820Sdes int gcs_rid; 56171820Sdes struct resource *gcs_res; 57171820Sdes 58129124Sdes eventhandler_tag ev_tag; 59129124Sdes}; 60129124Sdes 61129124Sdes#define VENDORID_INTEL 0x8086 62211908Sjfv#define DEVICEID_CPT0 0x1c40 63211908Sjfv#define DEVICEID_CPT1 0x1c41 64211908Sjfv#define DEVICEID_CPT2 0x1c42 65211908Sjfv#define DEVICEID_CPT3 0x1c43 66211908Sjfv#define DEVICEID_CPT4 0x1c44 67211908Sjfv#define DEVICEID_CPT5 0x1c45 68211908Sjfv#define DEVICEID_CPT6 0x1c46 69211908Sjfv#define DEVICEID_CPT7 0x1c47 70211908Sjfv#define DEVICEID_CPT8 0x1c48 71211908Sjfv#define DEVICEID_CPT9 0x1c49 72211908Sjfv#define DEVICEID_CPT10 0x1c4a 73211908Sjfv#define DEVICEID_CPT11 0x1c4b 74211908Sjfv#define DEVICEID_CPT12 0x1c4c 75211908Sjfv#define DEVICEID_CPT13 0x1c4d 76211908Sjfv#define DEVICEID_CPT14 0x1c4e 77211908Sjfv#define DEVICEID_CPT15 0x1c4f 78211908Sjfv#define DEVICEID_CPT16 0x1c50 79211908Sjfv#define DEVICEID_CPT17 0x1c51 80211908Sjfv#define DEVICEID_CPT18 0x1c52 81211908Sjfv#define DEVICEID_CPT19 0x1c53 82211908Sjfv#define DEVICEID_CPT20 0x1c54 83211908Sjfv#define DEVICEID_CPT21 0x1c55 84211908Sjfv#define DEVICEID_CPT22 0x1c56 85211908Sjfv#define DEVICEID_CPT23 0x1c57 86211908Sjfv#define DEVICEID_CPT24 0x1c58 87211908Sjfv#define DEVICEID_CPT25 0x1c59 88211908Sjfv#define DEVICEID_CPT26 0x1c5a 89211908Sjfv#define DEVICEID_CPT27 0x1c5b 90211908Sjfv#define DEVICEID_CPT28 0x1c5c 91211908Sjfv#define DEVICEID_CPT29 0x1c5d 92211908Sjfv#define DEVICEID_CPT30 0x1c5e 93211908Sjfv#define DEVICEID_CPT31 0x1c5f 94218149Sjfv#define DEVICEID_PATSBURG_LPC1 0x1d40 95218149Sjfv#define DEVICEID_PATSBURG_LPC2 0x1d41 96221789Sjfv#define DEVICEID_PPT0 0x1e40 97221789Sjfv#define DEVICEID_PPT1 0x1e41 98221789Sjfv#define DEVICEID_PPT2 0x1e42 99221789Sjfv#define DEVICEID_PPT3 0x1e43 100221789Sjfv#define DEVICEID_PPT4 0x1e44 101221789Sjfv#define DEVICEID_PPT5 0x1e45 102221789Sjfv#define DEVICEID_PPT6 0x1e46 103221789Sjfv#define DEVICEID_PPT7 0x1e47 104221789Sjfv#define DEVICEID_PPT8 0x1e48 105221789Sjfv#define DEVICEID_PPT9 0x1e49 106221789Sjfv#define DEVICEID_PPT10 0x1e4a 107221789Sjfv#define DEVICEID_PPT11 0x1e4b 108221789Sjfv#define DEVICEID_PPT12 0x1e4c 109221789Sjfv#define DEVICEID_PPT13 0x1e4d 110221789Sjfv#define DEVICEID_PPT14 0x1e4e 111221789Sjfv#define DEVICEID_PPT15 0x1e4f 112221789Sjfv#define DEVICEID_PPT16 0x1e50 113221789Sjfv#define DEVICEID_PPT17 0x1e51 114221789Sjfv#define DEVICEID_PPT18 0x1e52 115221789Sjfv#define DEVICEID_PPT19 0x1e53 116221789Sjfv#define DEVICEID_PPT20 0x1e54 117221789Sjfv#define DEVICEID_PPT21 0x1e55 118221789Sjfv#define DEVICEID_PPT22 0x1e56 119221789Sjfv#define DEVICEID_PPT23 0x1e57 120221789Sjfv#define DEVICEID_PPT24 0x1e58 121221789Sjfv#define DEVICEID_PPT25 0x1e59 122221789Sjfv#define DEVICEID_PPT26 0x1e5a 123221789Sjfv#define DEVICEID_PPT27 0x1e5b 124221789Sjfv#define DEVICEID_PPT28 0x1e5c 125221789Sjfv#define DEVICEID_PPT29 0x1e5d 126221789Sjfv#define DEVICEID_PPT30 0x1e5e 127221789Sjfv#define DEVICEID_PPT31 0x1e5f 128218140Sjfv#define DEVICEID_DH89XXCC_LPC 0x2310 129129124Sdes#define DEVICEID_82801AA 0x2410 130129124Sdes#define DEVICEID_82801AB 0x2420 131129124Sdes#define DEVICEID_82801BA 0x2440 132129124Sdes#define DEVICEID_82801BAM 0x244c 133129124Sdes#define DEVICEID_82801CA 0x2480 134129124Sdes#define DEVICEID_82801CAM 0x248c 135129124Sdes#define DEVICEID_82801DB 0x24c0 136129124Sdes#define DEVICEID_82801DBM 0x24cc 137129124Sdes#define DEVICEID_82801E 0x2450 138182161Sjhb#define DEVICEID_82801EB 0x24dc 139129124Sdes#define DEVICEID_82801EBR 0x24d0 140155785Sambrisko#define DEVICEID_6300ESB 0x25a1 141155785Sambrisko#define DEVICEID_82801FBR 0x2640 142171820Sdes#define DEVICEID_ICH6M 0x2641 143171820Sdes#define DEVICEID_ICH6W 0x2642 144173661Sjfv#define DEVICEID_63XXESB 0x2670 145171820Sdes#define DEVICEID_ICH7 0x27b8 146182161Sjhb#define DEVICEID_ICH7DH 0x27b0 147171820Sdes#define DEVICEID_ICH7M 0x27b9 148202917Sremko#define DEVICEID_NM10 0x27bc 149171820Sdes#define DEVICEID_ICH7MDH 0x27bd 150171820Sdes#define DEVICEID_ICH8 0x2810 151171820Sdes#define DEVICEID_ICH8DH 0x2812 152171820Sdes#define DEVICEID_ICH8DO 0x2814 153175128Sdes#define DEVICEID_ICH8M 0x2815 154182161Sjhb#define DEVICEID_ICH8ME 0x2811 155175013Sdes#define DEVICEID_ICH9 0x2918 156175013Sdes#define DEVICEID_ICH9DH 0x2912 157175013Sdes#define DEVICEID_ICH9DO 0x2914 158182161Sjhb#define DEVICEID_ICH9M 0x2919 159182161Sjhb#define DEVICEID_ICH9ME 0x2917 160182161Sjhb#define DEVICEID_ICH9R 0x2916 161182161Sjhb#define DEVICEID_ICH10 0x3a18 162182161Sjhb#define DEVICEID_ICH10D 0x3a1a 163182161Sjhb#define DEVICEID_ICH10DO 0x3a14 164182161Sjhb#define DEVICEID_ICH10R 0x3a16 165211908Sjfv#define DEVICEID_PCH 0x3b00 166211908Sjfv#define DEVICEID_PCHM 0x3b01 167211908Sjfv#define DEVICEID_P55 0x3b02 168211908Sjfv#define DEVICEID_PM55 0x3b03 169202812Semaste#define DEVICEID_H55 0x3b06 170211908Sjfv#define DEVICEID_QM57 0x3b07 171211908Sjfv#define DEVICEID_H57 0x3b08 172211908Sjfv#define DEVICEID_HM55 0x3b09 173211908Sjfv#define DEVICEID_Q57 0x3b0a 174211908Sjfv#define DEVICEID_HM57 0x3b0b 175211908Sjfv#define DEVICEID_PCHMSFF 0x3b0d 176211908Sjfv#define DEVICEID_QS57 0x3b0f 177211908Sjfv#define DEVICEID_3400 0x3b12 178211908Sjfv#define DEVICEID_3420 0x3b14 179211908Sjfv#define DEVICEID_3450 0x3b16 180244977Sjfv#define DEVICEID_LPT0 0x8c40 181244977Sjfv#define DEVICEID_LPT1 0x8c41 182244977Sjfv#define DEVICEID_LPT2 0x8c42 183244977Sjfv#define DEVICEID_LPT3 0x8c43 184244977Sjfv#define DEVICEID_LPT4 0x8c44 185244977Sjfv#define DEVICEID_LPT5 0x8c45 186244977Sjfv#define DEVICEID_LPT6 0x8c46 187244977Sjfv#define DEVICEID_LPT7 0x8c47 188244977Sjfv#define DEVICEID_LPT8 0x8c48 189244977Sjfv#define DEVICEID_LPT9 0x8c49 190244977Sjfv#define DEVICEID_LPT10 0x8c4a 191244977Sjfv#define DEVICEID_LPT11 0x8c4b 192244977Sjfv#define DEVICEID_LPT12 0x8c4c 193244977Sjfv#define DEVICEID_LPT13 0x8c4d 194244977Sjfv#define DEVICEID_LPT14 0x8c4e 195244977Sjfv#define DEVICEID_LPT15 0x8c4f 196244977Sjfv#define DEVICEID_LPT16 0x8c50 197244977Sjfv#define DEVICEID_LPT17 0x8c51 198244977Sjfv#define DEVICEID_LPT18 0x8c52 199244977Sjfv#define DEVICEID_LPT19 0x8c53 200244977Sjfv#define DEVICEID_LPT20 0x8c54 201244977Sjfv#define DEVICEID_LPT21 0x8c55 202244977Sjfv#define DEVICEID_LPT22 0x8c56 203244977Sjfv#define DEVICEID_LPT23 0x8c57 204244977Sjfv#define DEVICEID_LPT24 0x8c58 205244977Sjfv#define DEVICEID_LPT25 0x8c59 206244977Sjfv#define DEVICEID_LPT26 0x8c5a 207244977Sjfv#define DEVICEID_LPT27 0x8c5b 208244977Sjfv#define DEVICEID_LPT28 0x8c5c 209244977Sjfv#define DEVICEID_LPT29 0x8c5d 210244977Sjfv#define DEVICEID_LPT30 0x8c5e 211244977Sjfv#define DEVICEID_LPT31 0x8c5f 212129124Sdes 213171820Sdes/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 214129124Sdes#define ICH_GEN_STA 0xd4 215129124Sdes#define ICH_GEN_STA_NO_REBOOT 0x02 216129124Sdes#define ICH_PMBASE 0x40 /* ACPI base address register */ 217129124Sdes#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 218129124Sdes 219171820Sdes/* ICH Chipset Configuration Registers (ICH6 and newer) */ 220171820Sdes#define ICH_RCBA 0xf0 221171820Sdes#define ICH_GCS_OFFSET 0x3410 222171820Sdes#define ICH_GCS_SIZE 0x4 223171820Sdes#define ICH_GCS_NO_REBOOT 0x20 224171820Sdes 225129124Sdes/* register names and locations (relative to PMBASE) */ 226129124Sdes#define SMI_BASE 0x30 /* base address for SMI registers */ 227129124Sdes#define SMI_LEN 0x08 228129124Sdes#define SMI_EN 0x00 /* SMI Control and Enable Register */ 229129124Sdes#define SMI_STS 0x04 /* SMI Status Register */ 230129124Sdes#define TCO_BASE 0x60 /* base address for TCO registers */ 231171820Sdes#define TCO_LEN 0x20 232129124Sdes#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 233171820Sdes#define TCO_TMR1 0x01 /* TCO Timer Initial Value 234171820Sdes (ICH5 and older, 8 bits) */ 235171820Sdes#define TCO_TMR2 0x12 /* TCO Timer Initial Value 236171820Sdes (ICH6 and newer, 16 bits) */ 237129124Sdes#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 238129124Sdes#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 239129124Sdes#define TCO1_STS 0x04 /* TCO Status 1 */ 240129124Sdes#define TCO2_STS 0x06 /* TCO Status 2 */ 241129124Sdes#define TCO1_CNT 0x08 /* TCO Control 1 */ 242171820Sdes#define TCO2_CNT 0x08 /* TCO Control 2 */ 243220925Sattilio#define TCO_MESSAGE1 0x0c /* TCO Message 1 */ 244220925Sattilio#define TCO_MESSAGE2 0x0d /* TCO Message 2 */ 245129124Sdes 246129124Sdes/* bit definitions for SMI_EN and SMI_STS */ 247129124Sdes#define SMI_TCO_EN 0x2000 248129124Sdes#define SMI_TCO_STS 0x2000 249220925Sattilio#define SMI_GBL_EN 0x0001 250129124Sdes 251129124Sdes/* timer value mask for TCO_RLD and TCO_TMR */ 252129124Sdes#define TCO_TIMER_MASK 0x1f 253129124Sdes 254129124Sdes/* status bits for TCO1_STS */ 255220925Sattilio#define TCO_NEWCENTURY 0x80 /* set for RTC year roll over (99 to 00) */ 256129124Sdes#define TCO_TIMEOUT 0x08 /* timed out */ 257129124Sdes#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 258129124Sdes#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 259129124Sdes 260129124Sdes/* status bits for TCO2_STS */ 261129124Sdes#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 262129124Sdes#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 263129124Sdes 264129124Sdes/* control bits for TCO1_CNT */ 265220925Sattilio#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 266220925Sattilio#define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */ 267220925Sattilio#define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */ 268220925Sattilio#define TCO_NMI_NOW 0x0100 /* trigger an NMI */ 269129124Sdes 270216298Sattilio/* 271216298Sattilio * Masks for the TCO timer value field in TCO_RLD. 272216298Sattilio * If the datasheets are to be believed, the minimum value actually varies 273216298Sattilio * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 274216298Sattilio * I suspect this is a bug in the ICH5 datasheet and that the minimum is 275216298Sattilio * uniformly 2, but I'd rather err on the side of caution. 276216298Sattilio */ 277216298Sattilio#define TCO_RLD_TMR_MIN 0x0004 278216298Sattilio#define TCO_RLD1_TMR_MAX 0x003f 279216298Sattilio#define TCO_RLD2_TMR_MAX 0x03ff 280216298Sattilio 281171820Sdes/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 282171820Sdes#define ICHWD_TICK 600000000 283129124Sdes 284129124Sdes#endif 285