ichwd.h revision 218149
11592Srgrimes/*- 21592Srgrimes * Copyright (c) 2004 Texas A&M University 31592Srgrimes * All rights reserved. 41592Srgrimes * 51592Srgrimes * Developer: Wm. Daryl Hawkins 61592Srgrimes * 71592Srgrimes * Redistribution and use in source and binary forms, with or without 81592Srgrimes * modification, are permitted provided that the following conditions 91592Srgrimes * are met: 101592Srgrimes * 1. Redistributions of source code must retain the above copyright 111592Srgrimes * notice, this list of conditions and the following disclaimer. 121592Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 131592Srgrimes * notice, this list of conditions and the following disclaimer in the 141592Srgrimes * documentation and/or other materials provided with the distribution. 151592Srgrimes * 161592Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 171592Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 181592Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 191592Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 201592Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 211592Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 221592Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 231592Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 241592Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 251592Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 261592Srgrimes * SUCH DAMAGE. 271592Srgrimes * 281592Srgrimes * $FreeBSD: head/sys/dev/ichwd/ichwd.h 218149 2011-02-01 01:05:11Z jfv $ 291592Srgrimes */ 301592Srgrimes 311592Srgrimes#ifndef _ICHWD_H_ 321592Srgrimes#define _ICHWD_H_ 331592Srgrimes 341592Srgrimesstruct ichwd_device { 3531512Scharnier uint16_t device; 361592Srgrimes char *desc; 371592Srgrimes unsigned int version; 381592Srgrimes}; 391592Srgrimes 401592Srgrimesstruct ichwd_softc { 4131512Scharnier device_t device; 421592Srgrimes device_t ich; 4331512Scharnier int ich_version; 441592Srgrimes 45207608Simp int active; 46207608Simp unsigned int timeout; 471592Srgrimes 481592Srgrimes int smi_rid; 491592Srgrimes struct resource *smi_res; 501592Srgrimes bus_space_tag_t smi_bst; 511592Srgrimes bus_space_handle_t smi_bsh; 521592Srgrimes 531592Srgrimes int tco_rid; 541592Srgrimes struct resource *tco_res; 551592Srgrimes bus_space_tag_t tco_bst; 561592Srgrimes bus_space_handle_t tco_bsh; 571592Srgrimes 581592Srgrimes int gcs_rid; 591592Srgrimes struct resource *gcs_res; 601592Srgrimes bus_space_tag_t gcs_bst; 611592Srgrimes bus_space_handle_t gcs_bsh; 621592Srgrimes 631592Srgrimes eventhandler_tag ev_tag; 641592Srgrimes}; 651592Srgrimes 661592Srgrimes#define VENDORID_INTEL 0x8086 6731512Scharnier#define DEVICEID_CPT0 0x1c40 681592Srgrimes#define DEVICEID_CPT1 0x1c41 691592Srgrimes#define DEVICEID_CPT2 0x1c42 701592Srgrimes#define DEVICEID_CPT3 0x1c43 711592Srgrimes#define DEVICEID_CPT4 0x1c44 72207608Simp#define DEVICEID_CPT5 0x1c45 731592Srgrimes#define DEVICEID_CPT6 0x1c46 741592Srgrimes#define DEVICEID_CPT7 0x1c47 75207608Simp#define DEVICEID_CPT8 0x1c48 76207608Simp#define DEVICEID_CPT9 0x1c49 77207608Simp#define DEVICEID_CPT10 0x1c4a 78207608Simp#define DEVICEID_CPT11 0x1c4b 79207608Simp#define DEVICEID_CPT12 0x1c4c 801592Srgrimes#define DEVICEID_CPT13 0x1c4d 81207608Simp#define DEVICEID_CPT14 0x1c4e 82207608Simp#define DEVICEID_CPT15 0x1c4f 831592Srgrimes#define DEVICEID_CPT16 0x1c50 841592Srgrimes#define DEVICEID_CPT17 0x1c51 851592Srgrimes#define DEVICEID_CPT18 0x1c52 861592Srgrimes#define DEVICEID_CPT19 0x1c53 871592Srgrimes#define DEVICEID_CPT20 0x1c54 881592Srgrimes#define DEVICEID_CPT21 0x1c55 891592Srgrimes#define DEVICEID_CPT22 0x1c56 901592Srgrimes#define DEVICEID_CPT23 0x1c57 911592Srgrimes#define DEVICEID_CPT24 0x1c58 921592Srgrimes#define DEVICEID_CPT25 0x1c59 93112452Sdwmalone#define DEVICEID_CPT26 0x1c5a 941592Srgrimes#define DEVICEID_CPT27 0x1c5b 951592Srgrimes#define DEVICEID_CPT28 0x1c5c 961592Srgrimes#define DEVICEID_CPT29 0x1c5d 971592Srgrimes#define DEVICEID_CPT30 0x1c5e 9871616Sbillf#define DEVICEID_CPT31 0x1c5f 99129680Smdodd#define DEVICEID_PATSBURG_LPC1 0x1d40 100213099Smarius#define DEVICEID_PATSBURG_LPC2 0x1d41 101173852Sedwin#define DEVICEID_DH89XXCC_LPC 0x2310 102207608Simp#define DEVICEID_82801AA 0x2410 1031592Srgrimes#define DEVICEID_82801AB 0x2420 104207608Simp#define DEVICEID_82801BA 0x2440 105207608Simp#define DEVICEID_82801BAM 0x244c 106207608Simp#define DEVICEID_82801CA 0x2480 107207608Simp#define DEVICEID_82801CAM 0x248c 108207608Simp#define DEVICEID_82801DB 0x24c0 1091592Srgrimes#define DEVICEID_82801DBM 0x24cc 110207608Simp#define DEVICEID_82801E 0x2450 111112452Sdwmalone#define DEVICEID_82801EB 0x24dc 112207608Simp#define DEVICEID_82801EBR 0x24d0 113207608Simp#define DEVICEID_6300ESB 0x25a1 114207608Simp#define DEVICEID_82801FBR 0x2640 115207608Simp#define DEVICEID_ICH6M 0x2641 116207608Simp#define DEVICEID_ICH6W 0x2642 117207608Simp#define DEVICEID_63XXESB 0x2670 118207608Simp#define DEVICEID_ICH7 0x27b8 119207608Simp#define DEVICEID_ICH7DH 0x27b0 120207608Simp#define DEVICEID_ICH7M 0x27b9 1211592Srgrimes#define DEVICEID_NM10 0x27bc 12290333Simp#define DEVICEID_ICH7MDH 0x27bd 1231592Srgrimes#define DEVICEID_ICH8 0x2810 12490333Simp#define DEVICEID_ICH8DH 0x2812 125207608Simp#define DEVICEID_ICH8DO 0x2814 126207608Simp#define DEVICEID_ICH8M 0x2815 127207608Simp#define DEVICEID_ICH8ME 0x2811 128207608Simp#define DEVICEID_ICH9 0x2918 129207608Simp#define DEVICEID_ICH9DH 0x2912 130207608Simp#define DEVICEID_ICH9DO 0x2914 131207608Simp#define DEVICEID_ICH9M 0x2919 132207608Simp#define DEVICEID_ICH9ME 0x2917 133207608Simp#define DEVICEID_ICH9R 0x2916 1341592Srgrimes#define DEVICEID_ICH10 0x3a18 135130839Sbrian#define DEVICEID_ICH10D 0x3a1a 136207608Simp#define DEVICEID_ICH10DO 0x3a14 137130839Sbrian#define DEVICEID_ICH10R 0x3a16 138207608Simp#define DEVICEID_PCH 0x3b00 139207608Simp#define DEVICEID_PCHM 0x3b01 1401592Srgrimes#define DEVICEID_P55 0x3b02 14171616Sbillf#define DEVICEID_PM55 0x3b03 14271616Sbillf#define DEVICEID_H55 0x3b06 14371616Sbillf#define DEVICEID_QM57 0x3b07 14471616Sbillf#define DEVICEID_H57 0x3b08 14571616Sbillf#define DEVICEID_HM55 0x3b09 14671616Sbillf#define DEVICEID_Q57 0x3b0a 147207608Simp#define DEVICEID_HM57 0x3b0b 148207608Simp#define DEVICEID_PCHMSFF 0x3b0d 149207608Simp#define DEVICEID_QS57 0x3b0f 150207608Simp#define DEVICEID_3400 0x3b12 151207608Simp#define DEVICEID_3420 0x3b14 152207608Simp#define DEVICEID_3450 0x3b16 153173852Sedwin 154173852Sedwin/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 155173852Sedwin#define ICH_GEN_STA 0xd4 1561592Srgrimes#define ICH_GEN_STA_NO_REBOOT 0x02 1571592Srgrimes#define ICH_PMBASE 0x40 /* ACPI base address register */ 1581592Srgrimes#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 1591592Srgrimes 1601592Srgrimes/* ICH Chipset Configuration Registers (ICH6 and newer) */ 1611592Srgrimes#define ICH_RCBA 0xf0 162207608Simp#define ICH_GCS_OFFSET 0x3410 163207608Simp#define ICH_GCS_SIZE 0x4 164207608Simp#define ICH_GCS_NO_REBOOT 0x20 165207608Simp 166207608Simp/* register names and locations (relative to PMBASE) */ 167207608Simp#define SMI_BASE 0x30 /* base address for SMI registers */ 168207608Simp#define SMI_LEN 0x08 169207608Simp#define SMI_EN 0x00 /* SMI Control and Enable Register */ 170207608Simp#define SMI_STS 0x04 /* SMI Status Register */ 171207608Simp#define TCO_BASE 0x60 /* base address for TCO registers */ 172207608Simp#define TCO_LEN 0x20 173207608Simp#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 17418458Simp#define TCO_TMR1 0x01 /* TCO Timer Initial Value 17518458Simp (ICH5 and older, 8 bits) */ 17618458Simp#define TCO_TMR2 0x12 /* TCO Timer Initial Value 17765850Swollman (ICH6 and newer, 16 bits) */ 17865850Swollman#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 17965850Swollman#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 180129680Smdodd#define TCO1_STS 0x04 /* TCO Status 1 */ 181129680Smdodd#define TCO2_STS 0x06 /* TCO Status 2 */ 182129680Smdodd#define TCO1_CNT 0x08 /* TCO Control 1 */ 183129680Smdodd#define TCO2_CNT 0x08 /* TCO Control 2 */ 184129680Smdodd 185129680Smdodd/* bit definitions for SMI_EN and SMI_STS */ 186173852Sedwin#define SMI_TCO_EN 0x2000 187173852Sedwin#define SMI_TCO_STS 0x2000 188173852Sedwin 189173852Sedwin/* timer value mask for TCO_RLD and TCO_TMR */ 1901592Srgrimes#define TCO_TIMER_MASK 0x1f 191207608Simp 192207608Simp/* status bits for TCO1_STS */ 1931592Srgrimes#define TCO_TIMEOUT 0x08 /* timed out */ 1941592Srgrimes#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 1951592Srgrimes#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 1961592Srgrimes 1971592Srgrimes/* status bits for TCO2_STS */ 1981592Srgrimes#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 1991592Srgrimes#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 2001592Srgrimes 2011592Srgrimes/* control bits for TCO1_CNT */ 2021592Srgrimes#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 2031592Srgrimes#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ 2041592Srgrimes 2051592Srgrimes/* 2061592Srgrimes * Masks for the TCO timer value field in TCO_RLD. 2071592Srgrimes * If the datasheets are to be believed, the minimum value actually varies 20818458Simp * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 20918458Simp * I suspect this is a bug in the ICH5 datasheet and that the minimum is 21018458Simp * uniformly 2, but I'd rather err on the side of caution. 21118458Simp */ 212113714Sbillf#define TCO_RLD_TMR_MIN 0x0004 213207608Simp#define TCO_RLD1_TMR_MAX 0x003f 21471616Sbillf#define TCO_RLD2_TMR_MAX 0x03ff 21571616Sbillf 2161592Srgrimes/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 217129680Smdodd#define ICHWD_TICK 600000000 218129680Smdodd 219207608Simp#endif 220207608Simp