ichwd.h revision 216298
1139749Simp/*- 2129124Sdes * Copyright (c) 2004 Texas A&M University 3129124Sdes * All rights reserved. 4129124Sdes * 5129124Sdes * Developer: Wm. Daryl Hawkins 6129124Sdes * 7129124Sdes * Redistribution and use in source and binary forms, with or without 8129124Sdes * modification, are permitted provided that the following conditions 9129124Sdes * are met: 10129124Sdes * 1. Redistributions of source code must retain the above copyright 11129124Sdes * notice, this list of conditions and the following disclaimer. 12129124Sdes * 2. Redistributions in binary form must reproduce the above copyright 13129124Sdes * notice, this list of conditions and the following disclaimer in the 14129124Sdes * documentation and/or other materials provided with the distribution. 15129124Sdes * 16129124Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17129124Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18129124Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19129124Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20129124Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21129124Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22129124Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23129124Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24129124Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25129124Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26129124Sdes * SUCH DAMAGE. 27129124Sdes * 28129124Sdes * $FreeBSD: head/sys/dev/ichwd/ichwd.h 216298 2010-12-08 15:32:54Z attilio $ 29129124Sdes */ 30129124Sdes 31129124Sdes#ifndef _ICHWD_H_ 32129124Sdes#define _ICHWD_H_ 33129124Sdes 34129124Sdesstruct ichwd_device { 35129124Sdes uint16_t device; 36129124Sdes char *desc; 37171820Sdes unsigned int version; 38129124Sdes}; 39129124Sdes 40129124Sdesstruct ichwd_softc { 41129124Sdes device_t device; 42171820Sdes device_t ich; 43175012Sdes int ich_version; 44129124Sdes 45129124Sdes int active; 46129124Sdes unsigned int timeout; 47129124Sdes 48221015Sattilio int smi_rid; 49129124Sdes struct resource *smi_res; 50129124Sdes bus_space_tag_t smi_bst; 51129124Sdes bus_space_handle_t smi_bsh; 52129124Sdes 53129124Sdes int tco_rid; 54129124Sdes struct resource *tco_res; 55171820Sdes bus_space_tag_t tco_bst; 56171820Sdes bus_space_handle_t tco_bsh; 57171820Sdes 58129124Sdes int gcs_rid; 59129124Sdes struct resource *gcs_res; 60129124Sdes bus_space_tag_t gcs_bst; 61129124Sdes bus_space_handle_t gcs_bsh; 62211908Sjfv 63211908Sjfv eventhandler_tag ev_tag; 64211908Sjfv}; 65211908Sjfv 66211908Sjfv#define VENDORID_INTEL 0x8086 67211908Sjfv#define DEVICEID_CPT0 0x1c40 68211908Sjfv#define DEVICEID_CPT1 0x1c41 69211908Sjfv#define DEVICEID_CPT2 0x1c42 70211908Sjfv#define DEVICEID_CPT3 0x1c43 71211908Sjfv#define DEVICEID_CPT4 0x1c44 72211908Sjfv#define DEVICEID_CPT5 0x1c45 73211908Sjfv#define DEVICEID_CPT6 0x1c46 74211908Sjfv#define DEVICEID_CPT7 0x1c47 75211908Sjfv#define DEVICEID_CPT8 0x1c48 76211908Sjfv#define DEVICEID_CPT9 0x1c49 77211908Sjfv#define DEVICEID_CPT10 0x1c4a 78211908Sjfv#define DEVICEID_CPT11 0x1c4b 79211908Sjfv#define DEVICEID_CPT12 0x1c4c 80211908Sjfv#define DEVICEID_CPT13 0x1c4d 81211908Sjfv#define DEVICEID_CPT14 0x1c4e 82211908Sjfv#define DEVICEID_CPT15 0x1c4f 83211908Sjfv#define DEVICEID_CPT16 0x1c50 84211908Sjfv#define DEVICEID_CPT17 0x1c51 85211908Sjfv#define DEVICEID_CPT18 0x1c52 86211908Sjfv#define DEVICEID_CPT19 0x1c53 87211908Sjfv#define DEVICEID_CPT20 0x1c54 88211908Sjfv#define DEVICEID_CPT21 0x1c55 89211908Sjfv#define DEVICEID_CPT22 0x1c56 90211908Sjfv#define DEVICEID_CPT23 0x1c57 91211908Sjfv#define DEVICEID_CPT24 0x1c58 92211908Sjfv#define DEVICEID_CPT25 0x1c59 93211908Sjfv#define DEVICEID_CPT26 0x1c5a 94218149Sjfv#define DEVICEID_CPT27 0x1c5b 95218149Sjfv#define DEVICEID_CPT28 0x1c5c 96221789Sjfv#define DEVICEID_CPT29 0x1c5d 97221789Sjfv#define DEVICEID_CPT30 0x1c5e 98221789Sjfv#define DEVICEID_CPT31 0x1c5f 99221789Sjfv#define DEVICEID_82801AA 0x2410 100221789Sjfv#define DEVICEID_82801AB 0x2420 101221789Sjfv#define DEVICEID_82801BA 0x2440 102221789Sjfv#define DEVICEID_82801BAM 0x244c 103221789Sjfv#define DEVICEID_82801CA 0x2480 104221789Sjfv#define DEVICEID_82801CAM 0x248c 105221789Sjfv#define DEVICEID_82801DB 0x24c0 106221789Sjfv#define DEVICEID_82801DBM 0x24cc 107221789Sjfv#define DEVICEID_82801E 0x2450 108221789Sjfv#define DEVICEID_82801EB 0x24dc 109221789Sjfv#define DEVICEID_82801EBR 0x24d0 110221789Sjfv#define DEVICEID_6300ESB 0x25a1 111221789Sjfv#define DEVICEID_82801FBR 0x2640 112221789Sjfv#define DEVICEID_ICH6M 0x2641 113221789Sjfv#define DEVICEID_ICH6W 0x2642 114221789Sjfv#define DEVICEID_63XXESB 0x2670 115221789Sjfv#define DEVICEID_ICH7 0x27b8 116221789Sjfv#define DEVICEID_ICH7DH 0x27b0 117221789Sjfv#define DEVICEID_ICH7M 0x27b9 118221789Sjfv#define DEVICEID_NM10 0x27bc 119221789Sjfv#define DEVICEID_ICH7MDH 0x27bd 120221789Sjfv#define DEVICEID_ICH8 0x2810 121221789Sjfv#define DEVICEID_ICH8DH 0x2812 122221789Sjfv#define DEVICEID_ICH8DO 0x2814 123221789Sjfv#define DEVICEID_ICH8M 0x2815 124221789Sjfv#define DEVICEID_ICH8ME 0x2811 125221789Sjfv#define DEVICEID_ICH9 0x2918 126221789Sjfv#define DEVICEID_ICH9DH 0x2912 127221789Sjfv#define DEVICEID_ICH9DO 0x2914 128218140Sjfv#define DEVICEID_ICH9M 0x2919 129253475Sjfv#define DEVICEID_ICH9ME 0x2917 130129124Sdes#define DEVICEID_ICH9R 0x2916 131129124Sdes#define DEVICEID_ICH10 0x3a18 132129124Sdes#define DEVICEID_ICH10D 0x3a1a 133129124Sdes#define DEVICEID_ICH10DO 0x3a14 134129124Sdes#define DEVICEID_ICH10R 0x3a16 135129124Sdes#define DEVICEID_PCH 0x3b00 136129124Sdes#define DEVICEID_PCHM 0x3b01 137129124Sdes#define DEVICEID_P55 0x3b02 138129124Sdes#define DEVICEID_PM55 0x3b03 139182161Sjhb#define DEVICEID_H55 0x3b06 140129124Sdes#define DEVICEID_QM57 0x3b07 141155785Sambrisko#define DEVICEID_H57 0x3b08 142155785Sambrisko#define DEVICEID_HM55 0x3b09 143171820Sdes#define DEVICEID_Q57 0x3b0a 144171820Sdes#define DEVICEID_HM57 0x3b0b 145173661Sjfv#define DEVICEID_PCHMSFF 0x3b0d 146171820Sdes#define DEVICEID_QS57 0x3b0f 147182161Sjhb#define DEVICEID_3400 0x3b12 148171820Sdes#define DEVICEID_3420 0x3b14 149202917Sremko#define DEVICEID_3450 0x3b16 150171820Sdes 151171820Sdes/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 152171820Sdes#define ICH_GEN_STA 0xd4 153171820Sdes#define ICH_GEN_STA_NO_REBOOT 0x02 154175128Sdes#define ICH_PMBASE 0x40 /* ACPI base address register */ 155182161Sjhb#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 156175013Sdes 157175013Sdes/* ICH Chipset Configuration Registers (ICH6 and newer) */ 158175013Sdes#define ICH_RCBA 0xf0 159182161Sjhb#define ICH_GCS_OFFSET 0x3410 160182161Sjhb#define ICH_GCS_SIZE 0x4 161182161Sjhb#define ICH_GCS_NO_REBOOT 0x20 162182161Sjhb 163182161Sjhb/* register names and locations (relative to PMBASE) */ 164182161Sjhb#define SMI_BASE 0x30 /* base address for SMI registers */ 165182161Sjhb#define SMI_LEN 0x08 166211908Sjfv#define SMI_EN 0x00 /* SMI Control and Enable Register */ 167211908Sjfv#define SMI_STS 0x04 /* SMI Status Register */ 168211908Sjfv#define TCO_BASE 0x60 /* base address for TCO registers */ 169211908Sjfv#define TCO_LEN 0x20 170202812Semaste#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 171211908Sjfv#define TCO_TMR1 0x01 /* TCO Timer Initial Value 172211908Sjfv (ICH5 and older, 8 bits) */ 173211908Sjfv#define TCO_TMR2 0x12 /* TCO Timer Initial Value 174211908Sjfv (ICH6 and newer, 16 bits) */ 175211908Sjfv#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 176211908Sjfv#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 177211908Sjfv#define TCO1_STS 0x04 /* TCO Status 1 */ 178211908Sjfv#define TCO2_STS 0x06 /* TCO Status 2 */ 179211908Sjfv#define TCO1_CNT 0x08 /* TCO Control 1 */ 180211908Sjfv#define TCO2_CNT 0x08 /* TCO Control 2 */ 181244977Sjfv 182244977Sjfv/* bit definitions for SMI_EN and SMI_STS */ 183244977Sjfv#define SMI_TCO_EN 0x2000 184244977Sjfv#define SMI_TCO_STS 0x2000 185244977Sjfv 186244977Sjfv/* timer value mask for TCO_RLD and TCO_TMR */ 187244977Sjfv#define TCO_TIMER_MASK 0x1f 188244977Sjfv 189244977Sjfv/* status bits for TCO1_STS */ 190244977Sjfv#define TCO_TIMEOUT 0x08 /* timed out */ 191244977Sjfv#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 192244977Sjfv#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 193244977Sjfv 194244977Sjfv/* status bits for TCO2_STS */ 195244977Sjfv#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 196244977Sjfv#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 197244977Sjfv 198244977Sjfv/* control bits for TCO1_CNT */ 199244977Sjfv#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 200244977Sjfv#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ 201244977Sjfv 202244977Sjfv/* 203244977Sjfv * Masks for the TCO timer value field in TCO_RLD. 204244977Sjfv * If the datasheets are to be believed, the minimum value actually varies 205244977Sjfv * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 206244977Sjfv * I suspect this is a bug in the ICH5 datasheet and that the minimum is 207244977Sjfv * uniformly 2, but I'd rather err on the side of caution. 208244977Sjfv */ 209244977Sjfv#define TCO_RLD_TMR_MIN 0x0004 210244977Sjfv#define TCO_RLD1_TMR_MAX 0x003f 211244977Sjfv#define TCO_RLD2_TMR_MAX 0x03ff 212244977Sjfv 213275439Smav/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 214275439Smav#define ICHWD_TICK 600000000 215275439Smav 216129124Sdes#endif 217171820Sdes