ichwd.h revision 202812
1139749Simp/*- 2129124Sdes * Copyright (c) 2004 Texas A&M University 3129124Sdes * All rights reserved. 4129124Sdes * 5129124Sdes * Developer: Wm. Daryl Hawkins 6129124Sdes * 7129124Sdes * Redistribution and use in source and binary forms, with or without 8129124Sdes * modification, are permitted provided that the following conditions 9129124Sdes * are met: 10129124Sdes * 1. Redistributions of source code must retain the above copyright 11129124Sdes * notice, this list of conditions and the following disclaimer. 12129124Sdes * 2. Redistributions in binary form must reproduce the above copyright 13129124Sdes * notice, this list of conditions and the following disclaimer in the 14129124Sdes * documentation and/or other materials provided with the distribution. 15129124Sdes * 16129124Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17129124Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18129124Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19129124Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20129124Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21129124Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22129124Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23129124Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24129124Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25129124Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26129124Sdes * SUCH DAMAGE. 27129124Sdes * 28129124Sdes * $FreeBSD: head/sys/dev/ichwd/ichwd.h 202812 2010-01-22 16:05:10Z emaste $ 29129124Sdes */ 30129124Sdes 31129124Sdes#ifndef _ICHWD_H_ 32129124Sdes#define _ICHWD_H_ 33129124Sdes 34129124Sdesstruct ichwd_device { 35129124Sdes uint16_t device; 36129124Sdes char *desc; 37171820Sdes unsigned int version; 38129124Sdes}; 39129124Sdes 40129124Sdesstruct ichwd_softc { 41129124Sdes device_t device; 42171820Sdes device_t ich; 43175012Sdes int ich_version; 44129124Sdes 45129124Sdes int active; 46129124Sdes unsigned int timeout; 47129124Sdes 48129124Sdes int smi_rid; 49129124Sdes struct resource *smi_res; 50129124Sdes bus_space_tag_t smi_bst; 51129124Sdes bus_space_handle_t smi_bsh; 52129124Sdes 53129124Sdes int tco_rid; 54129124Sdes struct resource *tco_res; 55129124Sdes bus_space_tag_t tco_bst; 56129124Sdes bus_space_handle_t tco_bsh; 57129124Sdes 58171820Sdes int gcs_rid; 59171820Sdes struct resource *gcs_res; 60171820Sdes bus_space_tag_t gcs_bst; 61171820Sdes bus_space_handle_t gcs_bsh; 62171820Sdes 63129124Sdes eventhandler_tag ev_tag; 64129124Sdes}; 65129124Sdes 66129124Sdes#define VENDORID_INTEL 0x8086 67129124Sdes#define DEVICEID_82801AA 0x2410 68129124Sdes#define DEVICEID_82801AB 0x2420 69129124Sdes#define DEVICEID_82801BA 0x2440 70129124Sdes#define DEVICEID_82801BAM 0x244c 71129124Sdes#define DEVICEID_82801CA 0x2480 72129124Sdes#define DEVICEID_82801CAM 0x248c 73129124Sdes#define DEVICEID_82801DB 0x24c0 74129124Sdes#define DEVICEID_82801DBM 0x24cc 75129124Sdes#define DEVICEID_82801E 0x2450 76182161Sjhb#define DEVICEID_82801EB 0x24dc 77129124Sdes#define DEVICEID_82801EBR 0x24d0 78155785Sambrisko#define DEVICEID_6300ESB 0x25a1 79155785Sambrisko#define DEVICEID_82801FBR 0x2640 80171820Sdes#define DEVICEID_ICH6M 0x2641 81171820Sdes#define DEVICEID_ICH6W 0x2642 82173661Sjfv#define DEVICEID_63XXESB 0x2670 83171820Sdes#define DEVICEID_ICH7 0x27b8 84182161Sjhb#define DEVICEID_ICH7DH 0x27b0 85171820Sdes#define DEVICEID_ICH7M 0x27b9 86171820Sdes#define DEVICEID_ICH7MDH 0x27bd 87171820Sdes#define DEVICEID_ICH8 0x2810 88171820Sdes#define DEVICEID_ICH8DH 0x2812 89171820Sdes#define DEVICEID_ICH8DO 0x2814 90175128Sdes#define DEVICEID_ICH8M 0x2815 91182161Sjhb#define DEVICEID_ICH8ME 0x2811 92175013Sdes#define DEVICEID_ICH9 0x2918 93175013Sdes#define DEVICEID_ICH9DH 0x2912 94175013Sdes#define DEVICEID_ICH9DO 0x2914 95182161Sjhb#define DEVICEID_ICH9M 0x2919 96182161Sjhb#define DEVICEID_ICH9ME 0x2917 97182161Sjhb#define DEVICEID_ICH9R 0x2916 98182161Sjhb#define DEVICEID_ICH10 0x3a18 99182161Sjhb#define DEVICEID_ICH10D 0x3a1a 100182161Sjhb#define DEVICEID_ICH10DO 0x3a14 101182161Sjhb#define DEVICEID_ICH10R 0x3a16 102202812Semaste#define DEVICEID_H55 0x3b06 103129124Sdes 104171820Sdes/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 105129124Sdes#define ICH_GEN_STA 0xd4 106129124Sdes#define ICH_GEN_STA_NO_REBOOT 0x02 107129124Sdes#define ICH_PMBASE 0x40 /* ACPI base address register */ 108129124Sdes#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 109129124Sdes 110171820Sdes/* ICH Chipset Configuration Registers (ICH6 and newer) */ 111171820Sdes#define ICH_RCBA 0xf0 112171820Sdes#define ICH_GCS_OFFSET 0x3410 113171820Sdes#define ICH_GCS_SIZE 0x4 114171820Sdes#define ICH_GCS_NO_REBOOT 0x20 115171820Sdes 116129124Sdes/* register names and locations (relative to PMBASE) */ 117129124Sdes#define SMI_BASE 0x30 /* base address for SMI registers */ 118129124Sdes#define SMI_LEN 0x08 119129124Sdes#define SMI_EN 0x00 /* SMI Control and Enable Register */ 120129124Sdes#define SMI_STS 0x04 /* SMI Status Register */ 121129124Sdes#define TCO_BASE 0x60 /* base address for TCO registers */ 122171820Sdes#define TCO_LEN 0x20 123129124Sdes#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 124171820Sdes#define TCO_TMR1 0x01 /* TCO Timer Initial Value 125171820Sdes (ICH5 and older, 8 bits) */ 126171820Sdes#define TCO_TMR2 0x12 /* TCO Timer Initial Value 127171820Sdes (ICH6 and newer, 16 bits) */ 128129124Sdes#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 129129124Sdes#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 130129124Sdes#define TCO1_STS 0x04 /* TCO Status 1 */ 131129124Sdes#define TCO2_STS 0x06 /* TCO Status 2 */ 132129124Sdes#define TCO1_CNT 0x08 /* TCO Control 1 */ 133171820Sdes#define TCO2_CNT 0x08 /* TCO Control 2 */ 134129124Sdes 135129124Sdes/* bit definitions for SMI_EN and SMI_STS */ 136129124Sdes#define SMI_TCO_EN 0x2000 137129124Sdes#define SMI_TCO_STS 0x2000 138129124Sdes 139129124Sdes/* timer value mask for TCO_RLD and TCO_TMR */ 140129124Sdes#define TCO_TIMER_MASK 0x1f 141129124Sdes 142129124Sdes/* status bits for TCO1_STS */ 143129124Sdes#define TCO_TIMEOUT 0x08 /* timed out */ 144129124Sdes#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 145129124Sdes#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 146129124Sdes 147129124Sdes/* status bits for TCO2_STS */ 148129124Sdes#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 149129124Sdes#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 150129124Sdes 151129124Sdes/* control bits for TCO1_CNT */ 152129124Sdes#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 153129124Sdes#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ 154129124Sdes 155171820Sdes/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 156171820Sdes#define ICHWD_TICK 600000000 157129124Sdes 158129124Sdes#endif 159