ichwd.c revision 275439
1/*-
2 * Copyright (c) 2004 Texas A&M University
3 * All rights reserved.
4 *
5 * Developer: Wm. Daryl Hawkins
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * Intel ICH Watchdog Timer (WDT) driver
31 *
32 * Originally developed by Wm. Daryl Hawkins of Texas A&M
33 * Heavily modified by <des@FreeBSD.org>
34 *
35 * This is a tricky one.  The ICH WDT can't be treated as a regular PCI
36 * device as it's actually an integrated function of the ICH LPC interface
37 * bridge.  Detection is also awkward, because we can only infer the
38 * presence of the watchdog timer from the fact that the machine has an
39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT'
40 * ACPI table (although this driver does not support the ACPI detection
41 * method).
42 *
43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
44 * way of knowing if the WDT is permanently disabled (either by the BIOS
45 * or in hardware).
46 *
47 * The WDT is programmed through I/O registers in the ACPI I/O space.
48 * Intel swears it's always at offset 0x60, so we use that.
49 *
50 * For details about the ICH WDT, see Intel Application Note AP-725
51 * (document no. 292273-001).  The WDT is also described in the individual
52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet
53 * (document no. 252516-001) sections 9.10 and 9.11.
54 *
55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
56 */
57
58#include <sys/cdefs.h>
59__FBSDID("$FreeBSD: stable/10/sys/dev/ichwd/ichwd.c 275439 2014-12-03 06:53:49Z mav $");
60
61#include <sys/param.h>
62#include <sys/kernel.h>
63#include <sys/module.h>
64#include <sys/systm.h>
65#include <sys/bus.h>
66#include <machine/bus.h>
67#include <sys/rman.h>
68#include <machine/resource.h>
69#include <sys/watchdog.h>
70
71#include <isa/isavar.h>
72#include <dev/pci/pcivar.h>
73
74#include <dev/ichwd/ichwd.h>
75
76static struct ichwd_device ichwd_devices[] = {
77	{ DEVICEID_82801AA,  "Intel 82801AA watchdog timer",	1 },
78	{ DEVICEID_82801AB,  "Intel 82801AB watchdog timer",	1 },
79	{ DEVICEID_82801BA,  "Intel 82801BA watchdog timer",	2 },
80	{ DEVICEID_82801BAM, "Intel 82801BAM watchdog timer",	2 },
81	{ DEVICEID_82801CA,  "Intel 82801CA watchdog timer",	3 },
82	{ DEVICEID_82801CAM, "Intel 82801CAM watchdog timer",	3 },
83	{ DEVICEID_82801DB,  "Intel 82801DB watchdog timer",	4 },
84	{ DEVICEID_82801DBM, "Intel 82801DBM watchdog timer",	4 },
85	{ DEVICEID_82801E,   "Intel 82801E watchdog timer",	5 },
86	{ DEVICEID_82801EB,  "Intel 82801EB watchdog timer",	5 },
87	{ DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer",	5 },
88	{ DEVICEID_6300ESB,  "Intel 6300ESB watchdog timer",	5 },
89	{ DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer",	6 },
90	{ DEVICEID_ICH6M,    "Intel ICH6M watchdog timer",	6 },
91	{ DEVICEID_ICH6W,    "Intel ICH6W watchdog timer",	6 },
92	{ DEVICEID_ICH7,     "Intel ICH7 watchdog timer",	7 },
93	{ DEVICEID_ICH7DH,   "Intel ICH7DH watchdog timer",	7 },
94	{ DEVICEID_ICH7M,    "Intel ICH7M watchdog timer",	7 },
95	{ DEVICEID_ICH7MDH,  "Intel ICH7MDH watchdog timer",	7 },
96	{ DEVICEID_NM10,     "Intel NM10 watchdog timer",	7 },
97	{ DEVICEID_ICH8,     "Intel ICH8 watchdog timer",	8 },
98	{ DEVICEID_ICH8DH,   "Intel ICH8DH watchdog timer",	8 },
99	{ DEVICEID_ICH8DO,   "Intel ICH8DO watchdog timer",	8 },
100	{ DEVICEID_ICH8M,    "Intel ICH8M watchdog timer",	8 },
101	{ DEVICEID_ICH8ME,   "Intel ICH8M-E watchdog timer",	8 },
102	{ DEVICEID_63XXESB,  "Intel 63XXESB watchdog timer",	8 },
103	{ DEVICEID_ICH9,     "Intel ICH9 watchdog timer",	9 },
104	{ DEVICEID_ICH9DH,   "Intel ICH9DH watchdog timer",	9 },
105	{ DEVICEID_ICH9DO,   "Intel ICH9DO watchdog timer",	9 },
106	{ DEVICEID_ICH9M,    "Intel ICH9M watchdog timer",	9 },
107	{ DEVICEID_ICH9ME,   "Intel ICH9M-E watchdog timer",	9 },
108	{ DEVICEID_ICH9R,    "Intel ICH9R watchdog timer",	9 },
109	{ DEVICEID_ICH10,    "Intel ICH10 watchdog timer",	10 },
110	{ DEVICEID_ICH10D,   "Intel ICH10D watchdog timer",	10 },
111	{ DEVICEID_ICH10DO,  "Intel ICH10DO watchdog timer",	10 },
112	{ DEVICEID_ICH10R,   "Intel ICH10R watchdog timer",	10 },
113	{ DEVICEID_PCH,      "Intel PCH watchdog timer",	10 },
114	{ DEVICEID_PCHM,     "Intel PCH watchdog timer",	10 },
115	{ DEVICEID_P55,      "Intel P55 watchdog timer",	10 },
116	{ DEVICEID_PM55,     "Intel PM55 watchdog timer",	10 },
117	{ DEVICEID_H55,      "Intel H55 watchdog timer",	10 },
118	{ DEVICEID_QM57,     "Intel QM57 watchdog timer",       10 },
119	{ DEVICEID_H57,      "Intel H57 watchdog timer",        10 },
120	{ DEVICEID_HM55,     "Intel HM55 watchdog timer",       10 },
121	{ DEVICEID_Q57,      "Intel Q57 watchdog timer",        10 },
122	{ DEVICEID_HM57,     "Intel HM57 watchdog timer",       10 },
123	{ DEVICEID_PCHMSFF,  "Intel PCHMSFF watchdog timer",    10 },
124	{ DEVICEID_QS57,     "Intel QS57 watchdog timer",       10 },
125	{ DEVICEID_3400,     "Intel 3400 watchdog timer",       10 },
126	{ DEVICEID_3420,     "Intel 3420 watchdog timer",       10 },
127	{ DEVICEID_3450,     "Intel 3450 watchdog timer",       10 },
128	{ DEVICEID_CPT0,     "Intel Cougar Point watchdog timer",	10 },
129	{ DEVICEID_CPT1,     "Intel Cougar Point watchdog timer",	10 },
130	{ DEVICEID_CPT2,     "Intel Cougar Point watchdog timer",	10 },
131	{ DEVICEID_CPT3,     "Intel Cougar Point watchdog timer",	10 },
132	{ DEVICEID_CPT4,     "Intel Cougar Point watchdog timer",	10 },
133	{ DEVICEID_CPT5,     "Intel Cougar Point watchdog timer",	10 },
134	{ DEVICEID_CPT6,     "Intel Cougar Point watchdog timer",	10 },
135	{ DEVICEID_CPT7,     "Intel Cougar Point watchdog timer",	10 },
136	{ DEVICEID_CPT8,     "Intel Cougar Point watchdog timer",	10 },
137	{ DEVICEID_CPT9,     "Intel Cougar Point watchdog timer",	10 },
138	{ DEVICEID_CPT10,    "Intel Cougar Point watchdog timer",	10 },
139	{ DEVICEID_CPT11,    "Intel Cougar Point watchdog timer",	10 },
140	{ DEVICEID_CPT12,    "Intel Cougar Point watchdog timer",	10 },
141	{ DEVICEID_CPT13,    "Intel Cougar Point watchdog timer",	10 },
142	{ DEVICEID_CPT14,    "Intel Cougar Point watchdog timer",	10 },
143	{ DEVICEID_CPT15,    "Intel Cougar Point watchdog timer",	10 },
144	{ DEVICEID_CPT16,    "Intel Cougar Point watchdog timer",	10 },
145	{ DEVICEID_CPT17,    "Intel Cougar Point watchdog timer",	10 },
146	{ DEVICEID_CPT18,    "Intel Cougar Point watchdog timer",	10 },
147	{ DEVICEID_CPT19,    "Intel Cougar Point watchdog timer",	10 },
148	{ DEVICEID_CPT20,    "Intel Cougar Point watchdog timer",	10 },
149	{ DEVICEID_CPT21,    "Intel Cougar Point watchdog timer",	10 },
150	{ DEVICEID_CPT22,    "Intel Cougar Point watchdog timer",	10 },
151	{ DEVICEID_CPT23,    "Intel Cougar Point watchdog timer",	10 },
152	{ DEVICEID_CPT23,    "Intel Cougar Point watchdog timer",	10 },
153	{ DEVICEID_CPT25,    "Intel Cougar Point watchdog timer",	10 },
154	{ DEVICEID_CPT26,    "Intel Cougar Point watchdog timer",	10 },
155	{ DEVICEID_CPT27,    "Intel Cougar Point watchdog timer",	10 },
156	{ DEVICEID_CPT28,    "Intel Cougar Point watchdog timer",	10 },
157	{ DEVICEID_CPT29,    "Intel Cougar Point watchdog timer",	10 },
158	{ DEVICEID_CPT30,    "Intel Cougar Point watchdog timer",	10 },
159	{ DEVICEID_CPT31,    "Intel Cougar Point watchdog timer",	10 },
160	{ DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer",	10 },
161	{ DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer",	10 },
162	{ DEVICEID_PPT0,     "Intel Panther Point watchdog timer",	10 },
163	{ DEVICEID_PPT1,     "Intel Panther Point watchdog timer",	10 },
164	{ DEVICEID_PPT2,     "Intel Panther Point watchdog timer",	10 },
165	{ DEVICEID_PPT3,     "Intel Panther Point watchdog timer",	10 },
166	{ DEVICEID_PPT4,     "Intel Panther Point watchdog timer",	10 },
167	{ DEVICEID_PPT5,     "Intel Panther Point watchdog timer",	10 },
168	{ DEVICEID_PPT6,     "Intel Panther Point watchdog timer",	10 },
169	{ DEVICEID_PPT7,     "Intel Panther Point watchdog timer",	10 },
170	{ DEVICEID_PPT8,     "Intel Panther Point watchdog timer",	10 },
171	{ DEVICEID_PPT9,     "Intel Panther Point watchdog timer",	10 },
172	{ DEVICEID_PPT10,    "Intel Panther Point watchdog timer",	10 },
173	{ DEVICEID_PPT11,    "Intel Panther Point watchdog timer",	10 },
174	{ DEVICEID_PPT12,    "Intel Panther Point watchdog timer",	10 },
175	{ DEVICEID_PPT13,    "Intel Panther Point watchdog timer",	10 },
176	{ DEVICEID_PPT14,    "Intel Panther Point watchdog timer",	10 },
177	{ DEVICEID_PPT15,    "Intel Panther Point watchdog timer",	10 },
178	{ DEVICEID_PPT16,    "Intel Panther Point watchdog timer",	10 },
179	{ DEVICEID_PPT17,    "Intel Panther Point watchdog timer",	10 },
180	{ DEVICEID_PPT18,    "Intel Panther Point watchdog timer",	10 },
181	{ DEVICEID_PPT19,    "Intel Panther Point watchdog timer",	10 },
182	{ DEVICEID_PPT20,    "Intel Panther Point watchdog timer",	10 },
183	{ DEVICEID_PPT21,    "Intel Panther Point watchdog timer",	10 },
184	{ DEVICEID_PPT22,    "Intel Panther Point watchdog timer",	10 },
185	{ DEVICEID_PPT23,    "Intel Panther Point watchdog timer",	10 },
186	{ DEVICEID_PPT24,    "Intel Panther Point watchdog timer",	10 },
187	{ DEVICEID_PPT25,    "Intel Panther Point watchdog timer",	10 },
188	{ DEVICEID_PPT26,    "Intel Panther Point watchdog timer",	10 },
189	{ DEVICEID_PPT27,    "Intel Panther Point watchdog timer",	10 },
190	{ DEVICEID_PPT28,    "Intel Panther Point watchdog timer",	10 },
191	{ DEVICEID_PPT29,    "Intel Panther Point watchdog timer",	10 },
192	{ DEVICEID_PPT30,    "Intel Panther Point watchdog timer",	10 },
193	{ DEVICEID_PPT31,    "Intel Panther Point watchdog timer",	10 },
194	{ DEVICEID_LPT0,     "Intel Lynx Point watchdog timer",		10 },
195	{ DEVICEID_LPT1,     "Intel Lynx Point watchdog timer",		10 },
196	{ DEVICEID_LPT2,     "Intel Lynx Point watchdog timer",		10 },
197	{ DEVICEID_WCPT2,    "Intel Wildcat Point watchdog timer",	10 },
198	{ DEVICEID_WCPT4,    "Intel Wildcat Point watchdog timer",	10 },
199	{ DEVICEID_WCPT6,    "Intel Wildcat Point watchdog timer",	10 },
200	{ DEVICEID_DH89XXCC_LPC,  "Intel DH89xxCC watchdog timer",	10 },
201	{ DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer",  10 },
202	{ 0, NULL, 0 },
203};
204
205static devclass_t ichwd_devclass;
206
207#define ichwd_read_tco_1(sc, off) \
208	bus_read_1((sc)->tco_res, (off))
209#define ichwd_read_tco_2(sc, off) \
210	bus_read_2((sc)->tco_res, (off))
211#define ichwd_read_tco_4(sc, off) \
212	bus_read_4((sc)->tco_res, (off))
213#define ichwd_read_smi_4(sc, off) \
214	bus_read_4((sc)->smi_res, (off))
215#define ichwd_read_gcs_4(sc, off) \
216	bus_read_4((sc)->gcs_res, (off))
217
218#define ichwd_write_tco_1(sc, off, val) \
219	bus_write_1((sc)->tco_res, (off), (val))
220#define ichwd_write_tco_2(sc, off, val) \
221	bus_write_2((sc)->tco_res, (off), (val))
222#define ichwd_write_tco_4(sc, off, val) \
223	bus_write_4((sc)->tco_res, (off), (val))
224#define ichwd_write_smi_4(sc, off, val) \
225	bus_write_4((sc)->smi_res, (off), (val))
226#define ichwd_write_gcs_4(sc, off, val) \
227	bus_write_4((sc)->gcs_res, (off), (val))
228
229#define ichwd_verbose_printf(dev, ...) \
230	do {						\
231		if (bootverbose)			\
232			device_printf(dev, __VA_ARGS__);\
233	} while (0)
234
235/*
236 * Disable the watchdog timeout SMI handler.
237 *
238 * Apparently, some BIOSes install handlers that reset or disable the
239 * watchdog timer instead of resetting the system, so we disable the SMI
240 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this
241 * from happening.
242 */
243static __inline void
244ichwd_smi_disable(struct ichwd_softc *sc)
245{
246	ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN);
247}
248
249/*
250 * Enable the watchdog timeout SMI handler.  See above for details.
251 */
252static __inline void
253ichwd_smi_enable(struct ichwd_softc *sc)
254{
255	ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN);
256}
257
258/*
259 * Check if the watchdog SMI triggering is enabled.
260 */
261static __inline int
262ichwd_smi_is_enabled(struct ichwd_softc *sc)
263{
264	return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0);
265}
266
267/*
268 * Reset the watchdog status bits.
269 */
270static __inline void
271ichwd_sts_reset(struct ichwd_softc *sc)
272{
273	/*
274	 * The watchdog status bits are set to 1 by the hardware to
275	 * indicate various conditions.  They can be cleared by software
276	 * by writing a 1, not a 0.
277	 */
278	ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT);
279	/*
280	 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must
281	 * be done in two separate operations.
282	 */
283	ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS);
284	ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS);
285}
286
287/*
288 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the
289 * TCO1_CNT register.  This is complicated by the need to preserve bit 9
290 * of that same register, and the requirement that all other bits must be
291 * written back as zero.
292 */
293static __inline void
294ichwd_tmr_enable(struct ichwd_softc *sc)
295{
296	uint16_t cnt;
297
298	cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
299	ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT);
300	sc->active = 1;
301	ichwd_verbose_printf(sc->device, "timer enabled\n");
302}
303
304/*
305 * Disable the watchdog timer.  See above for details.
306 */
307static __inline void
308ichwd_tmr_disable(struct ichwd_softc *sc)
309{
310	uint16_t cnt;
311
312	cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
313	ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT);
314	sc->active = 0;
315	ichwd_verbose_printf(sc->device, "timer disabled\n");
316}
317
318/*
319 * Reload the watchdog timer: writing anything to any of the lower five
320 * bits of the TCO_RLD register reloads the timer from the last value
321 * written to TCO_TMR.
322 */
323static __inline void
324ichwd_tmr_reload(struct ichwd_softc *sc)
325{
326	if (sc->ich_version <= 5)
327		ichwd_write_tco_1(sc, TCO_RLD, 1);
328	else
329		ichwd_write_tco_2(sc, TCO_RLD, 1);
330}
331
332/*
333 * Set the initial timeout value.  Note that this must always be followed
334 * by a reload.
335 */
336static __inline void
337ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
338{
339
340	if (timeout < TCO_RLD_TMR_MIN)
341		timeout = TCO_RLD_TMR_MIN;
342
343	if (sc->ich_version <= 5) {
344		uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
345
346		tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
347		if (timeout > TCO_RLD1_TMR_MAX)
348			timeout = TCO_RLD1_TMR_MAX;
349		tmr_val8 |= timeout;
350		ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
351	} else {
352		uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
353
354		tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff);
355		if (timeout > TCO_RLD2_TMR_MAX)
356			timeout = TCO_RLD2_TMR_MAX;
357		tmr_val16 |= timeout;
358		ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
359	}
360
361	sc->timeout = timeout;
362
363	ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout);
364}
365
366static __inline int
367ichwd_clear_noreboot(struct ichwd_softc *sc)
368{
369	uint32_t status;
370	int rc = 0;
371
372	/* try to clear the NO_REBOOT bit */
373	if (sc->ich_version <= 5) {
374		status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
375		status &= ~ICH_GEN_STA_NO_REBOOT;
376		pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
377		status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
378		if (status & ICH_GEN_STA_NO_REBOOT)
379			rc = EIO;
380	} else {
381		status = ichwd_read_gcs_4(sc, 0);
382		status &= ~ICH_GCS_NO_REBOOT;
383		ichwd_write_gcs_4(sc, 0, status);
384		status = ichwd_read_gcs_4(sc, 0);
385		if (status & ICH_GCS_NO_REBOOT)
386			rc = EIO;
387	}
388
389	if (rc)
390		device_printf(sc->device,
391		    "ICH WDT present but disabled in BIOS or hardware\n");
392
393	return (rc);
394}
395
396/*
397 * Watchdog event handler - called by the framework to enable or disable
398 * the watchdog or change the initial timeout value.
399 */
400static void
401ichwd_event(void *arg, unsigned int cmd, int *error)
402{
403	struct ichwd_softc *sc = arg;
404	unsigned int timeout;
405
406	/* convert from power-of-two-ns to WDT ticks */
407	cmd &= WD_INTERVAL;
408	timeout = ((uint64_t)1 << cmd) / ICHWD_TICK;
409	if (cmd) {
410		if (!sc->active)
411			ichwd_tmr_enable(sc);
412		if (timeout != sc->timeout)
413			ichwd_tmr_set(sc, timeout);
414		ichwd_tmr_reload(sc);
415		*error = 0;
416	} else {
417		if (sc->active)
418			ichwd_tmr_disable(sc);
419	}
420}
421
422static device_t
423ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p)
424{
425	struct ichwd_device *id;
426	device_t ich = NULL;
427
428	/* look for an ICH LPC interface bridge */
429	for (id = ichwd_devices; id->desc != NULL; ++id)
430		if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL)
431			break;
432
433	if (ich == NULL)
434		return (NULL);
435
436	ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n",
437	    id->version, id->desc);
438
439	if (id_p)
440		*id_p = id;
441
442	return (ich);
443}
444
445/*
446 * Look for an ICH LPC interface bridge.  If one is found, register an
447 * ichwd device.  There can be only one.
448 */
449static void
450ichwd_identify(driver_t *driver, device_t parent)
451{
452	struct ichwd_device *id_p;
453	device_t ich = NULL;
454	device_t dev;
455	uint32_t rcba;
456	int rc;
457
458	ich = ichwd_find_ich_lpc_bridge(&id_p);
459	if (ich == NULL)
460		return;
461
462	/* good, add child to bus */
463	if ((dev = device_find_child(parent, driver->name, 0)) == NULL)
464		dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
465
466	if (dev == NULL)
467		return;
468
469	device_set_desc_copy(dev, id_p->desc);
470
471	if (id_p->version >= 6) {
472		/* get RCBA (root complex base address) */
473		rcba = pci_read_config(ich, ICH_RCBA, 4);
474		rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
475		    (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE);
476		if (rc)
477			ichwd_verbose_printf(dev,
478			    "Can not set memory resource for RCBA\n");
479	}
480}
481
482static int
483ichwd_probe(device_t dev)
484{
485
486	/* Do not claim some ISA PnP device by accident. */
487	if (isa_get_logicalid(dev) != 0)
488		return (ENXIO);
489	return (0);
490}
491
492static int
493ichwd_attach(device_t dev)
494{
495	struct ichwd_softc *sc;
496	struct ichwd_device *id_p;
497	device_t ich;
498	unsigned int pmbase = 0;
499
500	sc = device_get_softc(dev);
501	sc->device = dev;
502
503	ich = ichwd_find_ich_lpc_bridge(&id_p);
504	if (ich == NULL) {
505		device_printf(sc->device, "Can not find ICH device.\n");
506		goto fail;
507	}
508	sc->ich = ich;
509	sc->ich_version = id_p->version;
510
511	/* get ACPI base address */
512	pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
513	if (pmbase == 0) {
514		device_printf(dev, "ICH PMBASE register is empty\n");
515		goto fail;
516	}
517
518	/* allocate I/O register space */
519	sc->smi_rid = 0;
520	sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
521	    pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN,
522	    RF_ACTIVE | RF_SHAREABLE);
523	if (sc->smi_res == NULL) {
524		device_printf(dev, "unable to reserve SMI registers\n");
525		goto fail;
526	}
527
528	sc->tco_rid = 1;
529	sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid,
530	    pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN,
531	    RF_ACTIVE | RF_SHAREABLE);
532	if (sc->tco_res == NULL) {
533		device_printf(dev, "unable to reserve TCO registers\n");
534		goto fail;
535	}
536
537	sc->gcs_rid = 0;
538	if (sc->ich_version >= 6) {
539		sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
540		    &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
541		if (sc->gcs_res == NULL) {
542			device_printf(dev, "unable to reserve GCS registers\n");
543			goto fail;
544		}
545	}
546
547	if (ichwd_clear_noreboot(sc) != 0)
548		goto fail;
549
550	ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n",
551	    device_get_desc(dev), sc->ich_version);
552
553	/*
554	 * Determine if we are coming up after a watchdog-induced reset.  Some
555	 * BIOSes may clear this bit at bootup, preventing us from reporting
556	 * this case on such systems.  We clear this bit in ichwd_sts_reset().
557	 */
558	if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0)
559		device_printf(dev,
560		    "resuming after hardware watchdog timeout\n");
561
562	/* reset the watchdog status registers */
563	ichwd_sts_reset(sc);
564
565	/* make sure the WDT starts out inactive */
566	ichwd_tmr_disable(sc);
567
568	/* register the watchdog event handler */
569	sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0);
570
571	/* disable the SMI handler */
572	sc->smi_enabled = ichwd_smi_is_enabled(sc);
573	ichwd_smi_disable(sc);
574
575	return (0);
576 fail:
577	sc = device_get_softc(dev);
578	if (sc->tco_res != NULL)
579		bus_release_resource(dev, SYS_RES_IOPORT,
580		    sc->tco_rid, sc->tco_res);
581	if (sc->smi_res != NULL)
582		bus_release_resource(dev, SYS_RES_IOPORT,
583		    sc->smi_rid, sc->smi_res);
584	if (sc->gcs_res != NULL)
585		bus_release_resource(ich, SYS_RES_MEMORY,
586		    sc->gcs_rid, sc->gcs_res);
587
588	return (ENXIO);
589}
590
591static int
592ichwd_detach(device_t dev)
593{
594	struct ichwd_softc *sc;
595	device_t ich = NULL;
596
597	sc = device_get_softc(dev);
598
599	/* halt the watchdog timer */
600	if (sc->active)
601		ichwd_tmr_disable(sc);
602
603	/* enable the SMI handler */
604	if (sc->smi_enabled != 0)
605		ichwd_smi_enable(sc);
606
607	/* deregister event handler */
608	if (sc->ev_tag != NULL)
609		EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
610	sc->ev_tag = NULL;
611
612	/* reset the watchdog status registers */
613	ichwd_sts_reset(sc);
614
615	/* deallocate I/O register space */
616	bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res);
617	bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res);
618
619	/* deallocate memory resource */
620	ich = ichwd_find_ich_lpc_bridge(NULL);
621	if (sc->gcs_res && ich)
622		bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res);
623
624	return (0);
625}
626
627static device_method_t ichwd_methods[] = {
628	DEVMETHOD(device_identify, ichwd_identify),
629	DEVMETHOD(device_probe,	ichwd_probe),
630	DEVMETHOD(device_attach, ichwd_attach),
631	DEVMETHOD(device_detach, ichwd_detach),
632	DEVMETHOD(device_shutdown, ichwd_detach),
633	{0,0}
634};
635
636static driver_t ichwd_driver = {
637	"ichwd",
638	ichwd_methods,
639	sizeof(struct ichwd_softc),
640};
641
642DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL);
643