ichwd.c revision 221789
13062Sjlahoda/*- 23062Sjlahoda * Copyright (c) 2004 Texas A&M University 33062Sjlahoda * All rights reserved. 43062Sjlahoda * 53062Sjlahoda * Developer: Wm. Daryl Hawkins 63062Sjlahoda * 73062Sjlahoda * Redistribution and use in source and binary forms, with or without 83062Sjlahoda * modification, are permitted provided that the following conditions 93062Sjlahoda * are met: 103062Sjlahoda * 1. Redistributions of source code must retain the above copyright 113062Sjlahoda * notice, this list of conditions and the following disclaimer. 123062Sjlahoda * 2. Redistributions in binary form must reproduce the above copyright 133062Sjlahoda * notice, this list of conditions and the following disclaimer in the 143062Sjlahoda * documentation and/or other materials provided with the distribution. 153062Sjlahoda * 163062Sjlahoda * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 173062Sjlahoda * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 183062Sjlahoda * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 193062Sjlahoda * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 203062Sjlahoda * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 213062Sjlahoda * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 223062Sjlahoda * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 233062Sjlahoda * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 243062Sjlahoda * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 253062Sjlahoda * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 263062Sjlahoda * SUCH DAMAGE. 273062Sjlahoda */ 283062Sjlahoda 293062Sjlahoda/* 303062Sjlahoda * Intel ICH Watchdog Timer (WDT) driver 313062Sjlahoda * 323062Sjlahoda * Originally developed by Wm. Daryl Hawkins of Texas A&M 333062Sjlahoda * Heavily modified by <des@FreeBSD.org> 343062Sjlahoda * 353062Sjlahoda * This is a tricky one. The ICH WDT can't be treated as a regular PCI 363062Sjlahoda * device as it's actually an integrated function of the ICH LPC interface 373062Sjlahoda * bridge. Detection is also awkward, because we can only infer the 383062Sjlahoda * presence of the watchdog timer from the fact that the machine has an 393062Sjlahoda * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 403062Sjlahoda * ACPI table (although this driver does not support the ACPI detection 413062Sjlahoda * method). 423062Sjlahoda * 433062Sjlahoda * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 443062Sjlahoda * way of knowing if the WDT is permanently disabled (either by the BIOS 453062Sjlahoda * or in hardware). 463062Sjlahoda * 473062Sjlahoda * The WDT is programmed through I/O registers in the ACPI I/O space. 483062Sjlahoda * Intel swears it's always at offset 0x60, so we use that. 493062Sjlahoda * 503062Sjlahoda * For details about the ICH WDT, see Intel Application Note AP-725 513062Sjlahoda * (document no. 292273-001). The WDT is also described in the individual 523062Sjlahoda * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 533062Sjlahoda * (document no. 252516-001) sections 9.10 and 9.11. 543062Sjlahoda * 553062Sjlahoda * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 563062Sjlahoda */ 573062Sjlahoda 583062Sjlahoda#include <sys/cdefs.h> 593062Sjlahoda__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 221789 2011-05-11 20:31:27Z jfv $"); 603062Sjlahoda 613062Sjlahoda#include <sys/param.h> 623062Sjlahoda#include <sys/kernel.h> 633062Sjlahoda#include <sys/module.h> 643062Sjlahoda#include <sys/systm.h> 653062Sjlahoda#include <sys/bus.h> 663062Sjlahoda#include <machine/bus.h> 673062Sjlahoda#include <sys/rman.h> 683062Sjlahoda#include <machine/resource.h> 693062Sjlahoda#include <sys/watchdog.h> 703062Sjlahoda 713062Sjlahoda#include <isa/isavar.h> 723062Sjlahoda#include <dev/pci/pcivar.h> 733062Sjlahoda 743062Sjlahoda#include <dev/ichwd/ichwd.h> 753062Sjlahoda 763062Sjlahodastatic struct ichwd_device ichwd_devices[] = { 773062Sjlahoda { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 783062Sjlahoda { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 793062Sjlahoda { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 803062Sjlahoda { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 813062Sjlahoda { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 823062Sjlahoda { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 833062Sjlahoda { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 843062Sjlahoda { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 853062Sjlahoda { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 863062Sjlahoda { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 873062Sjlahoda { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 883062Sjlahoda { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 893062Sjlahoda { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 903062Sjlahoda { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 913062Sjlahoda { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 923062Sjlahoda { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 933062Sjlahoda { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 943062Sjlahoda { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 953062Sjlahoda { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 963062Sjlahoda { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 973062Sjlahoda { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 983062Sjlahoda { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 993062Sjlahoda { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 1003062Sjlahoda { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 1013062Sjlahoda { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 1023062Sjlahoda { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 1033062Sjlahoda { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 1043062Sjlahoda { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 1053062Sjlahoda { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 1063062Sjlahoda { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 1073062Sjlahoda { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 1083062Sjlahoda { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 1093062Sjlahoda { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 1103062Sjlahoda { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 1113062Sjlahoda { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 1123062Sjlahoda { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 1133062Sjlahoda { DEVICEID_PCH, "Intel PCH watchdog timer", 10 }, 1143062Sjlahoda { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 }, 1153062Sjlahoda { DEVICEID_P55, "Intel P55 watchdog timer", 10 }, 1163062Sjlahoda { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 }, 1173062Sjlahoda { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 1183062Sjlahoda { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 }, 1193062Sjlahoda { DEVICEID_H57, "Intel H57 watchdog timer", 10 }, 1203062Sjlahoda { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 }, 1213062Sjlahoda { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 }, 1223062Sjlahoda { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 }, 1233062Sjlahoda { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 }, 1243062Sjlahoda { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 }, 1253062Sjlahoda { DEVICEID_3400, "Intel 3400 watchdog timer", 10 }, 1263062Sjlahoda { DEVICEID_3420, "Intel 3420 watchdog timer", 10 }, 1273062Sjlahoda { DEVICEID_3450, "Intel 3450 watchdog timer", 10 }, 1283062Sjlahoda { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 }, 1293062Sjlahoda { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 }, 1303062Sjlahoda { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 }, 1313062Sjlahoda { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 }, 1323062Sjlahoda { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 }, 1333062Sjlahoda { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 }, 1343062Sjlahoda { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 }, 1353062Sjlahoda { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 }, 1363062Sjlahoda { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 }, 1373062Sjlahoda { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 }, 1383062Sjlahoda { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 }, 1393062Sjlahoda { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 }, 1403062Sjlahoda { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 }, 1413062Sjlahoda { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 }, 1423062Sjlahoda { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 }, 1433062Sjlahoda { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 }, 1443062Sjlahoda { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 }, 1453062Sjlahoda { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 }, 1463062Sjlahoda { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 }, 1473062Sjlahoda { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 }, 1483062Sjlahoda { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 }, 1493062Sjlahoda { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 }, 1503062Sjlahoda { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 }, 1513062Sjlahoda { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 1523062Sjlahoda { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 1533062Sjlahoda { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 }, 1543062Sjlahoda { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 }, 1553062Sjlahoda { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 }, 1563062Sjlahoda { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 }, 1573062Sjlahoda { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 }, 1583062Sjlahoda { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 }, 1593062Sjlahoda { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 }, 1603062Sjlahoda { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 }, 1613062Sjlahoda { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 }, 1623062Sjlahoda { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10 }, 1633062Sjlahoda { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10 }, 1643062Sjlahoda { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10 }, 1653062Sjlahoda { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10 }, 1663062Sjlahoda { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10 }, 1673062Sjlahoda { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10 }, 1683062Sjlahoda { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10 }, 1693062Sjlahoda { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10 }, 1703062Sjlahoda { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10 }, 1713062Sjlahoda { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10 }, 1723062Sjlahoda { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10 }, 1733062Sjlahoda { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10 }, 1743062Sjlahoda { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10 }, 1753062Sjlahoda { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10 }, 1763062Sjlahoda { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10 }, 1773062Sjlahoda { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10 }, 1783062Sjlahoda { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10 }, 1793062Sjlahoda { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10 }, 1803062Sjlahoda { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10 }, 1813062Sjlahoda { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10 }, 1823062Sjlahoda { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10 }, 1833062Sjlahoda { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10 }, 1843062Sjlahoda { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10 }, 1853062Sjlahoda { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10 }, 1863062Sjlahoda { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10 }, 1873062Sjlahoda { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10 }, 1883062Sjlahoda { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10 }, 1893062Sjlahoda { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10 }, 1903062Sjlahoda { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10 }, 1913062Sjlahoda { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10 }, 1923062Sjlahoda { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10 }, 1933062Sjlahoda { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10 }, 1943062Sjlahoda { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 }, 1953062Sjlahoda { 0, NULL, 0 }, 1963062Sjlahoda}; 1973062Sjlahoda 1983062Sjlahodastatic devclass_t ichwd_devclass; 1993062Sjlahoda 2003062Sjlahoda#define ichwd_read_tco_1(sc, off) \ 2013062Sjlahoda bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 2023062Sjlahoda#define ichwd_read_tco_2(sc, off) \ 2033062Sjlahoda bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 2043062Sjlahoda#define ichwd_read_tco_4(sc, off) \ 2053062Sjlahoda bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 2063062Sjlahoda#define ichwd_read_smi_4(sc, off) \ 2073062Sjlahoda bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 2083062Sjlahoda#define ichwd_read_gcs_4(sc, off) \ 2093062Sjlahoda bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 2103062Sjlahoda 2113062Sjlahoda#define ichwd_write_tco_1(sc, off, val) \ 2123062Sjlahoda bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 2133062Sjlahoda#define ichwd_write_tco_2(sc, off, val) \ 2143062Sjlahoda bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 2153062Sjlahoda#define ichwd_write_tco_4(sc, off, val) \ 2163062Sjlahoda bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 2173062Sjlahoda#define ichwd_write_smi_4(sc, off, val) \ 2183062Sjlahoda bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 2193062Sjlahoda#define ichwd_write_gcs_4(sc, off, val) \ 2203062Sjlahoda bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 2213062Sjlahoda 2223062Sjlahoda#define ichwd_verbose_printf(dev, ...) \ 2233062Sjlahoda do { \ 2243062Sjlahoda if (bootverbose) \ 2253062Sjlahoda device_printf(dev, __VA_ARGS__);\ 2263062Sjlahoda } while (0) 2273062Sjlahoda 2283062Sjlahoda/* 2293062Sjlahoda * Disable the watchdog timeout SMI handler. 2303062Sjlahoda * 2313062Sjlahoda * Apparently, some BIOSes install handlers that reset or disable the 2323062Sjlahoda * watchdog timer instead of resetting the system, so we disable the SMI 2333062Sjlahoda * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 2343062Sjlahoda * from happening. 2353062Sjlahoda */ 2363062Sjlahodastatic __inline void 2373062Sjlahodaichwd_smi_disable(struct ichwd_softc *sc) 2383062Sjlahoda{ 2393062Sjlahoda ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 2403062Sjlahoda} 2413062Sjlahoda 2423062Sjlahoda/* 2433062Sjlahoda * Enable the watchdog timeout SMI handler. See above for details. 2443062Sjlahoda */ 2453062Sjlahodastatic __inline void 2463062Sjlahodaichwd_smi_enable(struct ichwd_softc *sc) 2473062Sjlahoda{ 2483062Sjlahoda ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 2493062Sjlahoda} 2503062Sjlahoda 2513464Srfield/* 2523464Srfield * Check if the watchdog SMI triggering is enabled. 2533062Sjlahoda */ 2543062Sjlahodastatic __inline int 2553062Sjlahodaichwd_smi_is_enabled(struct ichwd_softc *sc) 2563062Sjlahoda{ 2573585Srfield return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 2583062Sjlahoda} 2593062Sjlahoda 2603062Sjlahoda/* 2613062Sjlahoda * Reset the watchdog status bits. 2623062Sjlahoda */ 2633062Sjlahodastatic __inline void 264ichwd_sts_reset(struct ichwd_softc *sc) 265{ 266 /* 267 * The watchdog status bits are set to 1 by the hardware to 268 * indicate various conditions. They can be cleared by software 269 * by writing a 1, not a 0. 270 */ 271 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 272 /* 273 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 274 * be done in two separate operations. 275 */ 276 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 277 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 278} 279 280/* 281 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 282 * TCO1_CNT register. This is complicated by the need to preserve bit 9 283 * of that same register, and the requirement that all other bits must be 284 * written back as zero. 285 */ 286static __inline void 287ichwd_tmr_enable(struct ichwd_softc *sc) 288{ 289 uint16_t cnt; 290 291 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 292 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 293 sc->active = 1; 294 ichwd_verbose_printf(sc->device, "timer enabled\n"); 295} 296 297/* 298 * Disable the watchdog timer. See above for details. 299 */ 300static __inline void 301ichwd_tmr_disable(struct ichwd_softc *sc) 302{ 303 uint16_t cnt; 304 305 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 306 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 307 sc->active = 0; 308 ichwd_verbose_printf(sc->device, "timer disabled\n"); 309} 310 311/* 312 * Reload the watchdog timer: writing anything to any of the lower five 313 * bits of the TCO_RLD register reloads the timer from the last value 314 * written to TCO_TMR. 315 */ 316static __inline void 317ichwd_tmr_reload(struct ichwd_softc *sc) 318{ 319 if (sc->ich_version <= 5) 320 ichwd_write_tco_1(sc, TCO_RLD, 1); 321 else 322 ichwd_write_tco_2(sc, TCO_RLD, 1); 323 324 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 325} 326 327/* 328 * Set the initial timeout value. Note that this must always be followed 329 * by a reload. 330 */ 331static __inline void 332ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 333{ 334 335 if (timeout < TCO_RLD_TMR_MIN) 336 timeout = TCO_RLD_TMR_MIN; 337 338 if (sc->ich_version <= 5) { 339 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 340 341 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 342 if (timeout > TCO_RLD1_TMR_MAX) 343 timeout = TCO_RLD1_TMR_MAX; 344 tmr_val8 |= timeout; 345 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 346 } else { 347 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 348 349 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 350 if (timeout > TCO_RLD2_TMR_MAX) 351 timeout = TCO_RLD2_TMR_MAX; 352 tmr_val16 |= timeout; 353 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 354 } 355 356 sc->timeout = timeout; 357 358 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 359} 360 361static __inline int 362ichwd_clear_noreboot(struct ichwd_softc *sc) 363{ 364 uint32_t status; 365 int rc = 0; 366 367 /* try to clear the NO_REBOOT bit */ 368 if (sc->ich_version <= 5) { 369 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 370 status &= ~ICH_GEN_STA_NO_REBOOT; 371 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 372 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 373 if (status & ICH_GEN_STA_NO_REBOOT) 374 rc = EIO; 375 } else { 376 status = ichwd_read_gcs_4(sc, 0); 377 status &= ~ICH_GCS_NO_REBOOT; 378 ichwd_write_gcs_4(sc, 0, status); 379 status = ichwd_read_gcs_4(sc, 0); 380 if (status & ICH_GCS_NO_REBOOT) 381 rc = EIO; 382 } 383 384 if (rc) 385 device_printf(sc->device, 386 "ICH WDT present but disabled in BIOS or hardware\n"); 387 388 return (rc); 389} 390 391/* 392 * Watchdog event handler - called by the framework to enable or disable 393 * the watchdog or change the initial timeout value. 394 */ 395static void 396ichwd_event(void *arg, unsigned int cmd, int *error) 397{ 398 struct ichwd_softc *sc = arg; 399 unsigned int timeout; 400 401 /* convert from power-of-two-ns to WDT ticks */ 402 cmd &= WD_INTERVAL; 403 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 404 if (cmd) { 405 if (timeout != sc->timeout) { 406 if (!sc->active) 407 ichwd_tmr_enable(sc); 408 ichwd_tmr_set(sc, timeout); 409 } 410 ichwd_tmr_reload(sc); 411 *error = 0; 412 } else { 413 if (sc->active) 414 ichwd_tmr_disable(sc); 415 } 416} 417 418static device_t 419ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 420{ 421 struct ichwd_device *id; 422 device_t ich = NULL; 423 424 /* look for an ICH LPC interface bridge */ 425 for (id = ichwd_devices; id->desc != NULL; ++id) 426 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 427 break; 428 429 if (ich == NULL) 430 return (NULL); 431 432 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 433 id->version, id->desc); 434 435 if (id_p) 436 *id_p = id; 437 438 return (ich); 439} 440 441/* 442 * Look for an ICH LPC interface bridge. If one is found, register an 443 * ichwd device. There can be only one. 444 */ 445static void 446ichwd_identify(driver_t *driver, device_t parent) 447{ 448 struct ichwd_device *id_p; 449 device_t ich = NULL; 450 device_t dev; 451 uint32_t rcba; 452 int rc; 453 454 ich = ichwd_find_ich_lpc_bridge(&id_p); 455 if (ich == NULL) 456 return; 457 458 /* good, add child to bus */ 459 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 460 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 461 462 if (dev == NULL) 463 return; 464 465 device_set_desc_copy(dev, id_p->desc); 466 467 if (id_p->version >= 6) { 468 /* get RCBA (root complex base address) */ 469 rcba = pci_read_config(ich, ICH_RCBA, 4); 470 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 471 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 472 if (rc) 473 ichwd_verbose_printf(dev, 474 "Can not set memory resource for RCBA\n"); 475 } 476} 477 478static int 479ichwd_probe(device_t dev) 480{ 481 482 /* Do not claim some ISA PnP device by accident. */ 483 if (isa_get_logicalid(dev) != 0) 484 return (ENXIO); 485 return (0); 486} 487 488static int 489ichwd_attach(device_t dev) 490{ 491 struct ichwd_softc *sc; 492 struct ichwd_device *id_p; 493 device_t ich; 494 unsigned int pmbase = 0; 495 496 sc = device_get_softc(dev); 497 sc->device = dev; 498 499 ich = ichwd_find_ich_lpc_bridge(&id_p); 500 if (ich == NULL) { 501 device_printf(sc->device, "Can not find ICH device.\n"); 502 goto fail; 503 } 504 sc->ich = ich; 505 sc->ich_version = id_p->version; 506 507 /* get ACPI base address */ 508 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 509 if (pmbase == 0) { 510 device_printf(dev, "ICH PMBASE register is empty\n"); 511 goto fail; 512 } 513 514 /* allocate I/O register space */ 515 sc->smi_rid = 0; 516 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 517 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 518 RF_ACTIVE | RF_SHAREABLE); 519 if (sc->smi_res == NULL) { 520 device_printf(dev, "unable to reserve SMI registers\n"); 521 goto fail; 522 } 523 sc->smi_bst = rman_get_bustag(sc->smi_res); 524 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 525 526 sc->tco_rid = 1; 527 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 528 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 529 RF_ACTIVE | RF_SHAREABLE); 530 if (sc->tco_res == NULL) { 531 device_printf(dev, "unable to reserve TCO registers\n"); 532 goto fail; 533 } 534 sc->tco_bst = rman_get_bustag(sc->tco_res); 535 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 536 537 sc->gcs_rid = 0; 538 if (sc->ich_version >= 6) { 539 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 540 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 541 if (sc->gcs_res == NULL) { 542 device_printf(dev, "unable to reserve GCS registers\n"); 543 goto fail; 544 } 545 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 546 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 547 } else { 548 sc->gcs_res = 0; 549 sc->gcs_bst = 0; 550 sc->gcs_bsh = 0; 551 } 552 553 if (ichwd_clear_noreboot(sc) != 0) 554 goto fail; 555 556 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 557 device_get_desc(dev), sc->ich_version); 558 559 /* 560 * Determine if we are coming up after a watchdog-induced reset. Some 561 * BIOSes may clear this bit at bootup, preventing us from reporting 562 * this case on such systems. We clear this bit in ichwd_sts_reset(). 563 */ 564 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 565 device_printf(dev, 566 "resuming after hardware watchdog timeout\n"); 567 568 /* reset the watchdog status registers */ 569 ichwd_sts_reset(sc); 570 571 /* make sure the WDT starts out inactive */ 572 ichwd_tmr_disable(sc); 573 574 /* register the watchdog event handler */ 575 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 576 577 /* disable the SMI handler */ 578 sc->smi_enabled = ichwd_smi_is_enabled(sc); 579 ichwd_smi_disable(sc); 580 581 return (0); 582 fail: 583 sc = device_get_softc(dev); 584 if (sc->tco_res != NULL) 585 bus_release_resource(dev, SYS_RES_IOPORT, 586 sc->tco_rid, sc->tco_res); 587 if (sc->smi_res != NULL) 588 bus_release_resource(dev, SYS_RES_IOPORT, 589 sc->smi_rid, sc->smi_res); 590 if (sc->gcs_res != NULL) 591 bus_release_resource(ich, SYS_RES_MEMORY, 592 sc->gcs_rid, sc->gcs_res); 593 594 return (ENXIO); 595} 596 597static int 598ichwd_detach(device_t dev) 599{ 600 struct ichwd_softc *sc; 601 device_t ich = NULL; 602 603 sc = device_get_softc(dev); 604 605 /* halt the watchdog timer */ 606 if (sc->active) 607 ichwd_tmr_disable(sc); 608 609 /* enable the SMI handler */ 610 if (sc->smi_enabled != 0) 611 ichwd_smi_enable(sc); 612 613 /* deregister event handler */ 614 if (sc->ev_tag != NULL) 615 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 616 sc->ev_tag = NULL; 617 618 /* reset the watchdog status registers */ 619 ichwd_sts_reset(sc); 620 621 /* deallocate I/O register space */ 622 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 623 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 624 625 /* deallocate memory resource */ 626 ich = ichwd_find_ich_lpc_bridge(NULL); 627 if (sc->gcs_res && ich) 628 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 629 630 return (0); 631} 632 633static device_method_t ichwd_methods[] = { 634 DEVMETHOD(device_identify, ichwd_identify), 635 DEVMETHOD(device_probe, ichwd_probe), 636 DEVMETHOD(device_attach, ichwd_attach), 637 DEVMETHOD(device_detach, ichwd_detach), 638 DEVMETHOD(device_shutdown, ichwd_detach), 639 {0,0} 640}; 641 642static driver_t ichwd_driver = { 643 "ichwd", 644 ichwd_methods, 645 sizeof(struct ichwd_softc), 646}; 647 648DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 649