ichwd.c revision 218140
1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 218140 2011-01-31 18:41:52Z jfv $"); 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/module.h> 64#include <sys/systm.h> 65#include <sys/bus.h> 66#include <machine/bus.h> 67#include <sys/rman.h> 68#include <machine/resource.h> 69#include <sys/watchdog.h> 70 71#include <isa/isavar.h> 72#include <dev/pci/pcivar.h> 73 74#include <dev/ichwd/ichwd.h> 75 76static struct ichwd_device ichwd_devices[] = { 77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 }, 114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 }, 115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 }, 116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 }, 117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 }, 119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 }, 120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 }, 121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 }, 122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 }, 123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 }, 124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 }, 125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 }, 126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 }, 127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 }, 128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 }, 129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 }, 130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 }, 131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 }, 132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 }, 133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 }, 134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 }, 135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 }, 136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 }, 137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 }, 138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 }, 139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 }, 140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 }, 141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 }, 142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 }, 143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 }, 144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 }, 145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 }, 146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 }, 147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 }, 148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 }, 149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 }, 150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 }, 151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 }, 154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 }, 155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 }, 156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 }, 157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 }, 158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 }, 159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 }, 160 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 }, 161 { 0, NULL, 0 }, 162}; 163 164static devclass_t ichwd_devclass; 165 166#define ichwd_read_tco_1(sc, off) \ 167 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 168#define ichwd_read_tco_2(sc, off) \ 169 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 170#define ichwd_read_tco_4(sc, off) \ 171 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 172#define ichwd_read_smi_4(sc, off) \ 173 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 174#define ichwd_read_gcs_4(sc, off) \ 175 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 176 177#define ichwd_write_tco_1(sc, off, val) \ 178 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 179#define ichwd_write_tco_2(sc, off, val) \ 180 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 181#define ichwd_write_tco_4(sc, off, val) \ 182 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 183#define ichwd_write_smi_4(sc, off, val) \ 184 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 185#define ichwd_write_gcs_4(sc, off, val) \ 186 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 187 188#define ichwd_verbose_printf(dev, ...) \ 189 do { \ 190 if (bootverbose) \ 191 device_printf(dev, __VA_ARGS__);\ 192 } while (0) 193 194/* 195 * Disable the watchdog timeout SMI handler. 196 * 197 * Apparently, some BIOSes install handlers that reset or disable the 198 * watchdog timer instead of resetting the system, so we disable the SMI 199 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 200 * from happening. 201 */ 202static __inline void 203ichwd_smi_disable(struct ichwd_softc *sc) 204{ 205 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 206} 207 208/* 209 * Enable the watchdog timeout SMI handler. See above for details. 210 */ 211static __inline void 212ichwd_smi_enable(struct ichwd_softc *sc) 213{ 214 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 215} 216 217/* 218 * Reset the watchdog status bits. 219 */ 220static __inline void 221ichwd_sts_reset(struct ichwd_softc *sc) 222{ 223 /* 224 * The watchdog status bits are set to 1 by the hardware to 225 * indicate various conditions. They can be cleared by software 226 * by writing a 1, not a 0. 227 */ 228 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 229 /* 230 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 231 * be done in two separate operations. 232 */ 233 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 234 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 235} 236 237/* 238 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 239 * TCO1_CNT register. This is complicated by the need to preserve bit 9 240 * of that same register, and the requirement that all other bits must be 241 * written back as zero. 242 */ 243static __inline void 244ichwd_tmr_enable(struct ichwd_softc *sc) 245{ 246 uint16_t cnt; 247 248 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 249 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 250 sc->active = 1; 251 ichwd_verbose_printf(sc->device, "timer enabled\n"); 252} 253 254/* 255 * Disable the watchdog timer. See above for details. 256 */ 257static __inline void 258ichwd_tmr_disable(struct ichwd_softc *sc) 259{ 260 uint16_t cnt; 261 262 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 263 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 264 sc->active = 0; 265 ichwd_verbose_printf(sc->device, "timer disabled\n"); 266} 267 268/* 269 * Reload the watchdog timer: writing anything to any of the lower five 270 * bits of the TCO_RLD register reloads the timer from the last value 271 * written to TCO_TMR. 272 */ 273static __inline void 274ichwd_tmr_reload(struct ichwd_softc *sc) 275{ 276 if (sc->ich_version <= 5) 277 ichwd_write_tco_1(sc, TCO_RLD, 1); 278 else 279 ichwd_write_tco_2(sc, TCO_RLD, 1); 280 281 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 282} 283 284/* 285 * Set the initial timeout value. Note that this must always be followed 286 * by a reload. 287 */ 288static __inline void 289ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 290{ 291 292 if (timeout < TCO_RLD_TMR_MIN) 293 timeout = TCO_RLD_TMR_MIN; 294 295 if (sc->ich_version <= 5) { 296 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 297 298 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 299 if (timeout > TCO_RLD1_TMR_MAX) 300 timeout = TCO_RLD1_TMR_MAX; 301 tmr_val8 |= timeout; 302 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 303 } else { 304 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 305 306 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 307 if (timeout > TCO_RLD2_TMR_MAX) 308 timeout = TCO_RLD2_TMR_MAX; 309 tmr_val16 |= timeout; 310 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 311 } 312 313 sc->timeout = timeout; 314 315 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 316} 317 318static __inline int 319ichwd_clear_noreboot(struct ichwd_softc *sc) 320{ 321 uint32_t status; 322 int rc = 0; 323 324 /* try to clear the NO_REBOOT bit */ 325 if (sc->ich_version <= 5) { 326 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 327 status &= ~ICH_GEN_STA_NO_REBOOT; 328 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 329 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 330 if (status & ICH_GEN_STA_NO_REBOOT) 331 rc = EIO; 332 } else { 333 status = ichwd_read_gcs_4(sc, 0); 334 status &= ~ICH_GCS_NO_REBOOT; 335 ichwd_write_gcs_4(sc, 0, status); 336 status = ichwd_read_gcs_4(sc, 0); 337 if (status & ICH_GCS_NO_REBOOT) 338 rc = EIO; 339 } 340 341 if (rc) 342 device_printf(sc->device, 343 "ICH WDT present but disabled in BIOS or hardware\n"); 344 345 return (rc); 346} 347 348/* 349 * Watchdog event handler - called by the framework to enable or disable 350 * the watchdog or change the initial timeout value. 351 */ 352static void 353ichwd_event(void *arg, unsigned int cmd, int *error) 354{ 355 struct ichwd_softc *sc = arg; 356 unsigned int timeout; 357 358 /* convert from power-of-two-ns to WDT ticks */ 359 cmd &= WD_INTERVAL; 360 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 361 if (cmd) { 362 if (timeout != sc->timeout) { 363 if (!sc->active) 364 ichwd_tmr_enable(sc); 365 ichwd_tmr_set(sc, timeout); 366 } 367 ichwd_tmr_reload(sc); 368 *error = 0; 369 } else { 370 if (sc->active) 371 ichwd_tmr_disable(sc); 372 } 373} 374 375static device_t 376ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 377{ 378 struct ichwd_device *id; 379 device_t ich = NULL; 380 381 /* look for an ICH LPC interface bridge */ 382 for (id = ichwd_devices; id->desc != NULL; ++id) 383 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 384 break; 385 386 if (ich == NULL) 387 return (NULL); 388 389 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 390 id->version, id->desc); 391 392 if (id_p) 393 *id_p = id; 394 395 return (ich); 396} 397 398/* 399 * Look for an ICH LPC interface bridge. If one is found, register an 400 * ichwd device. There can be only one. 401 */ 402static void 403ichwd_identify(driver_t *driver, device_t parent) 404{ 405 struct ichwd_device *id_p; 406 device_t ich = NULL; 407 device_t dev; 408 uint32_t rcba; 409 int rc; 410 411 ich = ichwd_find_ich_lpc_bridge(&id_p); 412 if (ich == NULL) 413 return; 414 415 /* good, add child to bus */ 416 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 417 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 418 419 if (dev == NULL) 420 return; 421 422 device_set_desc_copy(dev, id_p->desc); 423 424 if (id_p->version >= 6) { 425 /* get RCBA (root complex base address) */ 426 rcba = pci_read_config(ich, ICH_RCBA, 4); 427 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 428 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 429 if (rc) 430 ichwd_verbose_printf(dev, 431 "Can not set memory resource for RCBA\n"); 432 } 433} 434 435static int 436ichwd_probe(device_t dev) 437{ 438 439 /* Do not claim some ISA PnP device by accident. */ 440 if (isa_get_logicalid(dev) != 0) 441 return (ENXIO); 442 return (0); 443} 444 445static int 446ichwd_attach(device_t dev) 447{ 448 struct ichwd_softc *sc; 449 struct ichwd_device *id_p; 450 device_t ich; 451 unsigned int pmbase = 0; 452 453 sc = device_get_softc(dev); 454 sc->device = dev; 455 456 ich = ichwd_find_ich_lpc_bridge(&id_p); 457 if (ich == NULL) { 458 device_printf(sc->device, "Can not find ICH device.\n"); 459 goto fail; 460 } 461 sc->ich = ich; 462 sc->ich_version = id_p->version; 463 464 /* get ACPI base address */ 465 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 466 if (pmbase == 0) { 467 device_printf(dev, "ICH PMBASE register is empty\n"); 468 goto fail; 469 } 470 471 /* allocate I/O register space */ 472 sc->smi_rid = 0; 473 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 474 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 475 RF_ACTIVE | RF_SHAREABLE); 476 if (sc->smi_res == NULL) { 477 device_printf(dev, "unable to reserve SMI registers\n"); 478 goto fail; 479 } 480 sc->smi_bst = rman_get_bustag(sc->smi_res); 481 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 482 483 sc->tco_rid = 1; 484 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 485 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 486 RF_ACTIVE | RF_SHAREABLE); 487 if (sc->tco_res == NULL) { 488 device_printf(dev, "unable to reserve TCO registers\n"); 489 goto fail; 490 } 491 sc->tco_bst = rman_get_bustag(sc->tco_res); 492 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 493 494 sc->gcs_rid = 0; 495 if (sc->ich_version >= 6) { 496 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 497 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 498 if (sc->gcs_res == NULL) { 499 device_printf(dev, "unable to reserve GCS registers\n"); 500 goto fail; 501 } 502 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 503 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 504 } else { 505 sc->gcs_res = 0; 506 sc->gcs_bst = 0; 507 sc->gcs_bsh = 0; 508 } 509 510 if (ichwd_clear_noreboot(sc) != 0) 511 goto fail; 512 513 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 514 device_get_desc(dev), sc->ich_version); 515 516 /* 517 * Determine if we are coming up after a watchdog-induced reset. Some 518 * BIOSes may clear this bit at bootup, preventing us from reporting 519 * this case on such systems. We clear this bit in ichwd_sts_reset(). 520 */ 521 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 522 device_printf(dev, 523 "resuming after hardware watchdog timeout\n"); 524 525 /* reset the watchdog status registers */ 526 ichwd_sts_reset(sc); 527 528 /* make sure the WDT starts out inactive */ 529 ichwd_tmr_disable(sc); 530 531 /* register the watchdog event handler */ 532 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 533 534 /* disable the SMI handler */ 535 ichwd_smi_disable(sc); 536 537 return (0); 538 fail: 539 sc = device_get_softc(dev); 540 if (sc->tco_res != NULL) 541 bus_release_resource(dev, SYS_RES_IOPORT, 542 sc->tco_rid, sc->tco_res); 543 if (sc->smi_res != NULL) 544 bus_release_resource(dev, SYS_RES_IOPORT, 545 sc->smi_rid, sc->smi_res); 546 if (sc->gcs_res != NULL) 547 bus_release_resource(ich, SYS_RES_MEMORY, 548 sc->gcs_rid, sc->gcs_res); 549 550 return (ENXIO); 551} 552 553static int 554ichwd_detach(device_t dev) 555{ 556 struct ichwd_softc *sc; 557 device_t ich = NULL; 558 559 sc = device_get_softc(dev); 560 561 /* halt the watchdog timer */ 562 if (sc->active) 563 ichwd_tmr_disable(sc); 564 565 /* enable the SMI handler */ 566 ichwd_smi_enable(sc); 567 568 /* deregister event handler */ 569 if (sc->ev_tag != NULL) 570 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 571 sc->ev_tag = NULL; 572 573 /* reset the watchdog status registers */ 574 ichwd_sts_reset(sc); 575 576 /* deallocate I/O register space */ 577 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 578 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 579 580 /* deallocate memory resource */ 581 ich = ichwd_find_ich_lpc_bridge(NULL); 582 if (sc->gcs_res && ich) 583 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 584 585 return (0); 586} 587 588static device_method_t ichwd_methods[] = { 589 DEVMETHOD(device_identify, ichwd_identify), 590 DEVMETHOD(device_probe, ichwd_probe), 591 DEVMETHOD(device_attach, ichwd_attach), 592 DEVMETHOD(device_detach, ichwd_detach), 593 DEVMETHOD(device_shutdown, ichwd_detach), 594 {0,0} 595}; 596 597static driver_t ichwd_driver = { 598 "ichwd", 599 ichwd_methods, 600 sizeof(struct ichwd_softc), 601}; 602 603DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 604