ichwd.c revision 202917
1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 202917 2010-01-24 10:50:20Z remko $"); 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/module.h> 64#include <sys/systm.h> 65#include <sys/bus.h> 66#include <machine/bus.h> 67#include <sys/rman.h> 68#include <machine/resource.h> 69#include <sys/watchdog.h> 70 71#include <isa/isavar.h> 72#include <dev/pci/pcivar.h> 73 74#include <dev/ichwd/ichwd.h> 75 76static struct ichwd_device ichwd_devices[] = { 77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 113 { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 114 { 0, NULL, 0 }, 115}; 116 117static devclass_t ichwd_devclass; 118 119#define ichwd_read_tco_1(sc, off) \ 120 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 121#define ichwd_read_tco_2(sc, off) \ 122 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 123#define ichwd_read_tco_4(sc, off) \ 124 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 125#define ichwd_read_smi_4(sc, off) \ 126 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 127#define ichwd_read_gcs_4(sc, off) \ 128 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 129 130#define ichwd_write_tco_1(sc, off, val) \ 131 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 132#define ichwd_write_tco_2(sc, off, val) \ 133 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 134#define ichwd_write_tco_4(sc, off, val) \ 135 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 136#define ichwd_write_smi_4(sc, off, val) \ 137 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 138#define ichwd_write_gcs_4(sc, off, val) \ 139 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 140 141#define ichwd_verbose_printf(dev, ...) \ 142 do { \ 143 if (bootverbose) \ 144 device_printf(dev, __VA_ARGS__);\ 145 } while (0) 146 147/* 148 * Disable the watchdog timeout SMI handler. 149 * 150 * Apparently, some BIOSes install handlers that reset or disable the 151 * watchdog timer instead of resetting the system, so we disable the SMI 152 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 153 * from happening. 154 */ 155static __inline void 156ichwd_smi_disable(struct ichwd_softc *sc) 157{ 158 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 159} 160 161/* 162 * Enable the watchdog timeout SMI handler. See above for details. 163 */ 164static __inline void 165ichwd_smi_enable(struct ichwd_softc *sc) 166{ 167 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 168} 169 170/* 171 * Reset the watchdog status bits. 172 */ 173static __inline void 174ichwd_sts_reset(struct ichwd_softc *sc) 175{ 176 /* 177 * The watchdog status bits are set to 1 by the hardware to 178 * indicate various conditions. They can be cleared by software 179 * by writing a 1, not a 0. 180 */ 181 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 182 /* 183 * XXX The datasheet says that TCO_SECOND_TO_STS must be cleared 184 * before TCO_BOOT_STS, not the other way around. 185 */ 186 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 187 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 188} 189 190/* 191 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 192 * TCO1_CNT register. This is complicated by the need to preserve bit 9 193 * of that same register, and the requirement that all other bits must be 194 * written back as zero. 195 */ 196static __inline void 197ichwd_tmr_enable(struct ichwd_softc *sc) 198{ 199 uint16_t cnt; 200 201 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 202 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 203 sc->active = 1; 204 ichwd_verbose_printf(sc->device, "timer enabled\n"); 205} 206 207/* 208 * Disable the watchdog timer. See above for details. 209 */ 210static __inline void 211ichwd_tmr_disable(struct ichwd_softc *sc) 212{ 213 uint16_t cnt; 214 215 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 216 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 217 sc->active = 0; 218 ichwd_verbose_printf(sc->device, "timer disabled\n"); 219} 220 221/* 222 * Reload the watchdog timer: writing anything to any of the lower five 223 * bits of the TCO_RLD register reloads the timer from the last value 224 * written to TCO_TMR. 225 */ 226static __inline void 227ichwd_tmr_reload(struct ichwd_softc *sc) 228{ 229 if (sc->ich_version <= 5) 230 ichwd_write_tco_1(sc, TCO_RLD, 1); 231 else 232 ichwd_write_tco_2(sc, TCO_RLD, 1); 233 234 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 235} 236 237/* 238 * Set the initial timeout value. Note that this must always be followed 239 * by a reload. 240 */ 241static __inline void 242ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 243{ 244 245 /* 246 * If the datasheets are to be believed, the minimum value 247 * actually varies from chipset to chipset - 4 for ICH5 and 2 for 248 * all other chipsets. I suspect this is a bug in the ICH5 249 * datasheet and that the minimum is uniformly 2, but I'd rather 250 * err on the side of caution. 251 */ 252 if (timeout < 4) 253 timeout = 4; 254 255 if (sc->ich_version <= 5) { 256 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 257 258 tmr_val8 &= 0xc0; 259 if (timeout > 0xbf) 260 timeout = 0xbf; 261 tmr_val8 |= timeout; 262 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 263 } else { 264 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 265 266 tmr_val16 &= 0xfc00; 267 if (timeout > 0x03ff) 268 timeout = 0x03ff; 269 tmr_val16 |= timeout; 270 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 271 } 272 273 sc->timeout = timeout; 274 275 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 276} 277 278static __inline int 279ichwd_clear_noreboot(struct ichwd_softc *sc) 280{ 281 uint32_t status; 282 int rc = 0; 283 284 /* try to clear the NO_REBOOT bit */ 285 if (sc->ich_version <= 5) { 286 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 287 status &= ~ICH_GEN_STA_NO_REBOOT; 288 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 289 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 290 if (status & ICH_GEN_STA_NO_REBOOT) 291 rc = EIO; 292 } else { 293 status = ichwd_read_gcs_4(sc, 0); 294 status &= ~ICH_GCS_NO_REBOOT; 295 ichwd_write_gcs_4(sc, 0, status); 296 status = ichwd_read_gcs_4(sc, 0); 297 if (status & ICH_GCS_NO_REBOOT) 298 rc = EIO; 299 } 300 301 if (rc) 302 device_printf(sc->device, 303 "ICH WDT present but disabled in BIOS or hardware\n"); 304 305 return (rc); 306} 307 308/* 309 * Watchdog event handler - called by the framework to enable or disable 310 * the watchdog or change the initial timeout value. 311 */ 312static void 313ichwd_event(void *arg, unsigned int cmd, int *error) 314{ 315 struct ichwd_softc *sc = arg; 316 unsigned int timeout; 317 318 /* convert from power-of-two-ns to WDT ticks */ 319 cmd &= WD_INTERVAL; 320 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 321 if (cmd) { 322 if (timeout != sc->timeout) { 323 if (!sc->active) 324 ichwd_tmr_enable(sc); 325 ichwd_tmr_set(sc, timeout); 326 } 327 ichwd_tmr_reload(sc); 328 *error = 0; 329 } else { 330 if (sc->active) 331 ichwd_tmr_disable(sc); 332 } 333} 334 335static device_t 336ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 337{ 338 struct ichwd_device *id; 339 device_t ich = NULL; 340 341 /* look for an ICH LPC interface bridge */ 342 for (id = ichwd_devices; id->desc != NULL; ++id) 343 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 344 break; 345 346 if (ich == NULL) 347 return (NULL); 348 349 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 350 id->version, id->desc); 351 352 if (id_p) 353 *id_p = id; 354 355 return (ich); 356} 357 358/* 359 * Look for an ICH LPC interface bridge. If one is found, register an 360 * ichwd device. There can be only one. 361 */ 362static void 363ichwd_identify(driver_t *driver, device_t parent) 364{ 365 struct ichwd_device *id_p; 366 device_t ich = NULL; 367 device_t dev; 368 uint32_t rcba; 369 int rc; 370 371 ich = ichwd_find_ich_lpc_bridge(&id_p); 372 if (ich == NULL) 373 return; 374 375 /* good, add child to bus */ 376 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 377 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 378 379 if (dev == NULL) 380 return; 381 382 device_set_desc_copy(dev, id_p->desc); 383 384 if (id_p->version >= 6) { 385 /* get RCBA (root complex base address) */ 386 rcba = pci_read_config(ich, ICH_RCBA, 4); 387 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 388 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 389 if (rc) 390 ichwd_verbose_printf(dev, 391 "Can not set memory resource for RCBA\n"); 392 } 393} 394 395static int 396ichwd_probe(device_t dev) 397{ 398 399 /* Do not claim some ISA PnP device by accident. */ 400 if (isa_get_logicalid(dev) != 0) 401 return (ENXIO); 402 return (0); 403} 404 405static int 406ichwd_attach(device_t dev) 407{ 408 struct ichwd_softc *sc; 409 struct ichwd_device *id_p; 410 device_t ich; 411 unsigned int pmbase = 0; 412 413 sc = device_get_softc(dev); 414 sc->device = dev; 415 416 ich = ichwd_find_ich_lpc_bridge(&id_p); 417 if (ich == NULL) { 418 device_printf(sc->device, "Can not find ICH device.\n"); 419 goto fail; 420 } 421 sc->ich = ich; 422 sc->ich_version = id_p->version; 423 424 /* get ACPI base address */ 425 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 426 if (pmbase == 0) { 427 device_printf(dev, "ICH PMBASE register is empty\n"); 428 goto fail; 429 } 430 431 /* allocate I/O register space */ 432 sc->smi_rid = 0; 433 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 434 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 435 RF_ACTIVE | RF_SHAREABLE); 436 if (sc->smi_res == NULL) { 437 device_printf(dev, "unable to reserve SMI registers\n"); 438 goto fail; 439 } 440 sc->smi_bst = rman_get_bustag(sc->smi_res); 441 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 442 443 sc->tco_rid = 1; 444 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 445 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 446 RF_ACTIVE | RF_SHAREABLE); 447 if (sc->tco_res == NULL) { 448 device_printf(dev, "unable to reserve TCO registers\n"); 449 goto fail; 450 } 451 sc->tco_bst = rman_get_bustag(sc->tco_res); 452 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 453 454 sc->gcs_rid = 0; 455 if (sc->ich_version >= 6) { 456 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 457 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 458 if (sc->gcs_res == NULL) { 459 device_printf(dev, "unable to reserve GCS registers\n"); 460 goto fail; 461 } 462 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 463 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 464 } else { 465 sc->gcs_res = 0; 466 sc->gcs_bst = 0; 467 sc->gcs_bsh = 0; 468 } 469 470 if (ichwd_clear_noreboot(sc) != 0) 471 goto fail; 472 473 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 474 device_get_desc(dev), sc->ich_version); 475 476 /* 477 * XXX we should check the status registers (specifically, the 478 * TCO_SECOND_TO_STS bit in the TCO2_STS register) to see if we 479 * just came back from a watchdog-induced reset, and let the user 480 * know. 481 */ 482 483 /* reset the watchdog status registers */ 484 ichwd_sts_reset(sc); 485 486 /* make sure the WDT starts out inactive */ 487 ichwd_tmr_disable(sc); 488 489 /* register the watchdog event handler */ 490 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 491 492 /* disable the SMI handler */ 493 ichwd_smi_disable(sc); 494 495 return (0); 496 fail: 497 sc = device_get_softc(dev); 498 if (sc->tco_res != NULL) 499 bus_release_resource(dev, SYS_RES_IOPORT, 500 sc->tco_rid, sc->tco_res); 501 if (sc->smi_res != NULL) 502 bus_release_resource(dev, SYS_RES_IOPORT, 503 sc->smi_rid, sc->smi_res); 504 if (sc->gcs_res != NULL) 505 bus_release_resource(ich, SYS_RES_MEMORY, 506 sc->gcs_rid, sc->gcs_res); 507 508 return (ENXIO); 509} 510 511static int 512ichwd_detach(device_t dev) 513{ 514 struct ichwd_softc *sc; 515 device_t ich = NULL; 516 517 sc = device_get_softc(dev); 518 519 /* halt the watchdog timer */ 520 if (sc->active) 521 ichwd_tmr_disable(sc); 522 523 /* enable the SMI handler */ 524 ichwd_smi_enable(sc); 525 526 /* deregister event handler */ 527 if (sc->ev_tag != NULL) 528 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 529 sc->ev_tag = NULL; 530 531 /* reset the watchdog status registers */ 532 ichwd_sts_reset(sc); 533 534 /* deallocate I/O register space */ 535 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 536 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 537 538 /* deallocate memory resource */ 539 ich = ichwd_find_ich_lpc_bridge(NULL); 540 if (sc->gcs_res && ich) 541 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 542 543 return (0); 544} 545 546static device_method_t ichwd_methods[] = { 547 DEVMETHOD(device_identify, ichwd_identify), 548 DEVMETHOD(device_probe, ichwd_probe), 549 DEVMETHOD(device_attach, ichwd_attach), 550 DEVMETHOD(device_detach, ichwd_detach), 551 DEVMETHOD(device_shutdown, ichwd_detach), 552 {0,0} 553}; 554 555static driver_t ichwd_driver = { 556 "ichwd", 557 ichwd_methods, 558 sizeof(struct ichwd_softc), 559}; 560 561DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 562