ichwd.c revision 197072
1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 197072 2009-09-10 18:33:08Z n_hibma $"); 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/module.h> 64#include <sys/systm.h> 65#include <sys/bus.h> 66#include <machine/bus.h> 67#include <sys/rman.h> 68#include <machine/resource.h> 69#include <sys/watchdog.h> 70 71#include <dev/pci/pcivar.h> 72 73#include <dev/ichwd/ichwd.h> 74 75static struct ichwd_device ichwd_devices[] = { 76 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 77 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 78 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 79 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 80 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 81 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 82 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 83 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 84 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 85 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 86 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 87 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 88 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 89 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 90 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 91 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 92 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 93 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 94 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 95 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 96 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 97 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 98 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 99 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 100 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 101 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 102 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 103 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 104 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 105 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 106 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 107 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 108 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 109 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 110 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 111 { 0, NULL, 0 }, 112}; 113 114static devclass_t ichwd_devclass; 115 116#define ichwd_read_tco_1(sc, off) \ 117 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 118#define ichwd_read_tco_2(sc, off) \ 119 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 120#define ichwd_read_tco_4(sc, off) \ 121 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 122#define ichwd_read_smi_4(sc, off) \ 123 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 124#define ichwd_read_gcs_4(sc, off) \ 125 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 126 127#define ichwd_write_tco_1(sc, off, val) \ 128 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 129#define ichwd_write_tco_2(sc, off, val) \ 130 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 131#define ichwd_write_tco_4(sc, off, val) \ 132 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 133#define ichwd_write_smi_4(sc, off, val) \ 134 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 135#define ichwd_write_gcs_4(sc, off, val) \ 136 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 137 138#define ichwd_verbose_printf(dev, ...) \ 139 do { \ 140 if (bootverbose) \ 141 device_printf(dev, __VA_ARGS__);\ 142 } while (0) 143 144/* 145 * Disable the watchdog timeout SMI handler. 146 * 147 * Apparently, some BIOSes install handlers that reset or disable the 148 * watchdog timer instead of resetting the system, so we disable the SMI 149 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 150 * from happening. 151 */ 152static __inline void 153ichwd_smi_disable(struct ichwd_softc *sc) 154{ 155 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 156} 157 158/* 159 * Enable the watchdog timeout SMI handler. See above for details. 160 */ 161static __inline void 162ichwd_smi_enable(struct ichwd_softc *sc) 163{ 164 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 165} 166 167/* 168 * Reset the watchdog status bits. 169 */ 170static __inline void 171ichwd_sts_reset(struct ichwd_softc *sc) 172{ 173 /* 174 * The watchdog status bits are set to 1 by the hardware to 175 * indicate various conditions. They can be cleared by software 176 * by writing a 1, not a 0. 177 */ 178 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 179 /* 180 * XXX The datasheet says that TCO_SECOND_TO_STS must be cleared 181 * before TCO_BOOT_STS, not the other way around. 182 */ 183 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 184 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 185} 186 187/* 188 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 189 * TCO1_CNT register. This is complicated by the need to preserve bit 9 190 * of that same register, and the requirement that all other bits must be 191 * written back as zero. 192 */ 193static __inline void 194ichwd_tmr_enable(struct ichwd_softc *sc) 195{ 196 uint16_t cnt; 197 198 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 199 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 200 sc->active = 1; 201 ichwd_verbose_printf(sc->device, "timer enabled\n"); 202} 203 204/* 205 * Disable the watchdog timer. See above for details. 206 */ 207static __inline void 208ichwd_tmr_disable(struct ichwd_softc *sc) 209{ 210 uint16_t cnt; 211 212 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 213 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 214 sc->active = 0; 215 ichwd_verbose_printf(sc->device, "timer disabled\n"); 216} 217 218/* 219 * Reload the watchdog timer: writing anything to any of the lower five 220 * bits of the TCO_RLD register reloads the timer from the last value 221 * written to TCO_TMR. 222 */ 223static __inline void 224ichwd_tmr_reload(struct ichwd_softc *sc) 225{ 226 if (sc->ich_version <= 5) 227 ichwd_write_tco_1(sc, TCO_RLD, 1); 228 else 229 ichwd_write_tco_2(sc, TCO_RLD, 1); 230 231 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 232} 233 234/* 235 * Set the initial timeout value. Note that this must always be followed 236 * by a reload. 237 */ 238static __inline void 239ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 240{ 241 242 /* 243 * If the datasheets are to be believed, the minimum value 244 * actually varies from chipset to chipset - 4 for ICH5 and 2 for 245 * all other chipsets. I suspect this is a bug in the ICH5 246 * datasheet and that the minimum is uniformly 2, but I'd rather 247 * err on the side of caution. 248 */ 249 if (timeout < 4) 250 timeout = 4; 251 252 if (sc->ich_version <= 5) { 253 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 254 255 tmr_val8 &= 0xc0; 256 if (timeout > 0xbf) 257 timeout = 0xbf; 258 tmr_val8 |= timeout; 259 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 260 } else { 261 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 262 263 tmr_val16 &= 0xfc00; 264 if (timeout > 0x03ff) 265 timeout = 0x03ff; 266 tmr_val16 |= timeout; 267 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 268 } 269 270 sc->timeout = timeout; 271 272 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 273} 274 275static __inline int 276ichwd_clear_noreboot(struct ichwd_softc *sc) 277{ 278 uint32_t status; 279 int rc = 0; 280 281 /* try to clear the NO_REBOOT bit */ 282 if (sc->ich_version <= 5) { 283 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 284 status &= ~ICH_GEN_STA_NO_REBOOT; 285 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 286 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 287 if (status & ICH_GEN_STA_NO_REBOOT) 288 rc = EIO; 289 } else { 290 status = ichwd_read_gcs_4(sc, 0); 291 status &= ~ICH_GCS_NO_REBOOT; 292 ichwd_write_gcs_4(sc, 0, status); 293 status = ichwd_read_gcs_4(sc, 0); 294 if (status & ICH_GCS_NO_REBOOT) 295 rc = EIO; 296 } 297 298 if (rc) 299 device_printf(sc->device, 300 "ICH WDT present but disabled in BIOS or hardware\n"); 301 302 return (rc); 303} 304 305/* 306 * Watchdog event handler - called by the framework to enable or disable 307 * the watchdog or change the initial timeout value. 308 */ 309static void 310ichwd_event(void *arg, unsigned int cmd, int *error) 311{ 312 struct ichwd_softc *sc = arg; 313 unsigned int timeout; 314 315 /* convert from power-of-two-ns to WDT ticks */ 316 cmd &= WD_INTERVAL; 317 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 318 if (cmd) { 319 if (timeout != sc->timeout) { 320 if (!sc->active) 321 ichwd_tmr_enable(sc); 322 ichwd_tmr_set(sc, timeout); 323 } 324 ichwd_tmr_reload(sc); 325 *error = 0; 326 } else { 327 if (sc->active) 328 ichwd_tmr_disable(sc); 329 } 330} 331 332static device_t 333ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 334{ 335 struct ichwd_device *id; 336 device_t ich = NULL; 337 338 /* look for an ICH LPC interface bridge */ 339 for (id = ichwd_devices; id->desc != NULL; ++id) 340 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 341 break; 342 343 if (ich == NULL) 344 return (NULL); 345 346 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 347 id->version, id->desc); 348 349 if (id_p) 350 *id_p = id; 351 352 return (ich); 353} 354 355/* 356 * Look for an ICH LPC interface bridge. If one is found, register an 357 * ichwd device. There can be only one. 358 */ 359static void 360ichwd_identify(driver_t *driver, device_t parent) 361{ 362 struct ichwd_device *id_p; 363 device_t ich = NULL; 364 device_t dev; 365 uint32_t rcba; 366 int rc; 367 368 ich = ichwd_find_ich_lpc_bridge(&id_p); 369 if (ich == NULL) 370 return; 371 372 /* good, add child to bus */ 373 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 374 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 375 376 if (dev == NULL) 377 return; 378 379 device_set_desc_copy(dev, id_p->desc); 380 381 if (id_p->version >= 6) { 382 /* get RCBA (root complex base address) */ 383 rcba = pci_read_config(ich, ICH_RCBA, 4); 384 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 385 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 386 if (rc) 387 ichwd_verbose_printf(dev, 388 "Can not set memory resource for RCBA\n"); 389 } 390} 391 392static int 393ichwd_probe(device_t dev) 394{ 395 396 (void)dev; 397 return (0); 398} 399 400static int 401ichwd_attach(device_t dev) 402{ 403 struct ichwd_softc *sc; 404 struct ichwd_device *id_p; 405 device_t ich; 406 unsigned int pmbase = 0; 407 408 sc = device_get_softc(dev); 409 sc->device = dev; 410 411 ich = ichwd_find_ich_lpc_bridge(&id_p); 412 if (ich == NULL) { 413 device_printf(sc->device, "Can not find ICH device.\n"); 414 goto fail; 415 } 416 sc->ich = ich; 417 sc->ich_version = id_p->version; 418 419 /* get ACPI base address */ 420 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 421 if (pmbase == 0) { 422 device_printf(dev, "ICH PMBASE register is empty\n"); 423 goto fail; 424 } 425 426 /* allocate I/O register space */ 427 sc->smi_rid = 0; 428 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 429 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 430 RF_ACTIVE | RF_SHAREABLE); 431 if (sc->smi_res == NULL) { 432 device_printf(dev, "unable to reserve SMI registers\n"); 433 goto fail; 434 } 435 sc->smi_bst = rman_get_bustag(sc->smi_res); 436 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 437 438 sc->tco_rid = 1; 439 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 440 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 441 RF_ACTIVE | RF_SHAREABLE); 442 if (sc->tco_res == NULL) { 443 device_printf(dev, "unable to reserve TCO registers\n"); 444 goto fail; 445 } 446 sc->tco_bst = rman_get_bustag(sc->tco_res); 447 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 448 449 sc->gcs_rid = 0; 450 if (sc->ich_version >= 6) { 451 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 452 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 453 if (sc->gcs_res == NULL) { 454 device_printf(dev, "unable to reserve GCS registers\n"); 455 goto fail; 456 } 457 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 458 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 459 } else { 460 sc->gcs_res = 0; 461 sc->gcs_bst = 0; 462 sc->gcs_bsh = 0; 463 } 464 465 if (ichwd_clear_noreboot(sc) != 0) 466 goto fail; 467 468 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 469 device_get_desc(dev), sc->ich_version); 470 471 /* 472 * XXX we should check the status registers (specifically, the 473 * TCO_SECOND_TO_STS bit in the TCO2_STS register) to see if we 474 * just came back from a watchdog-induced reset, and let the user 475 * know. 476 */ 477 478 /* reset the watchdog status registers */ 479 ichwd_sts_reset(sc); 480 481 /* make sure the WDT starts out inactive */ 482 ichwd_tmr_disable(sc); 483 484 /* register the watchdog event handler */ 485 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 486 487 /* disable the SMI handler */ 488 ichwd_smi_disable(sc); 489 490 return (0); 491 fail: 492 sc = device_get_softc(dev); 493 if (sc->tco_res != NULL) 494 bus_release_resource(dev, SYS_RES_IOPORT, 495 sc->tco_rid, sc->tco_res); 496 if (sc->smi_res != NULL) 497 bus_release_resource(dev, SYS_RES_IOPORT, 498 sc->smi_rid, sc->smi_res); 499 if (sc->gcs_res != NULL) 500 bus_release_resource(ich, SYS_RES_MEMORY, 501 sc->gcs_rid, sc->gcs_res); 502 503 return (ENXIO); 504} 505 506static int 507ichwd_detach(device_t dev) 508{ 509 struct ichwd_softc *sc; 510 device_t ich = NULL; 511 512 sc = device_get_softc(dev); 513 514 /* halt the watchdog timer */ 515 if (sc->active) 516 ichwd_tmr_disable(sc); 517 518 /* enable the SMI handler */ 519 ichwd_smi_enable(sc); 520 521 /* deregister event handler */ 522 if (sc->ev_tag != NULL) 523 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 524 sc->ev_tag = NULL; 525 526 /* reset the watchdog status registers */ 527 ichwd_sts_reset(sc); 528 529 /* deallocate I/O register space */ 530 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 531 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 532 533 /* deallocate memory resource */ 534 ich = ichwd_find_ich_lpc_bridge(NULL); 535 if (sc->gcs_res && ich) 536 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 537 538 return (0); 539} 540 541static device_method_t ichwd_methods[] = { 542 DEVMETHOD(device_identify, ichwd_identify), 543 DEVMETHOD(device_probe, ichwd_probe), 544 DEVMETHOD(device_attach, ichwd_attach), 545 DEVMETHOD(device_detach, ichwd_detach), 546 DEVMETHOD(device_shutdown, ichwd_detach), 547 {0,0} 548}; 549 550static driver_t ichwd_driver = { 551 "ichwd", 552 ichwd_methods, 553 sizeof(struct ichwd_softc), 554}; 555 556DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 557