ichwd.c revision 175128
1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 175128 2008-01-07 09:46:39Z des $"); 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/module.h> 64#include <sys/systm.h> 65#include <sys/bus.h> 66#include <machine/bus.h> 67#include <sys/rman.h> 68#include <machine/resource.h> 69#include <sys/watchdog.h> 70 71#include <dev/pci/pcivar.h> 72 73#include <dev/ichwd/ichwd.h> 74 75static struct ichwd_device ichwd_devices[] = { 76 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 77 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 78 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 79 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 80 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 81 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 82 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 83 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 84 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 85 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 86 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 87 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 88 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 89 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 90 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 91 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 92 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 93 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 94 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 95 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 96 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 97 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 98 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 99 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 100 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 101 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 102 { 0, NULL, 0 }, 103}; 104 105static devclass_t ichwd_devclass; 106 107#define ichwd_read_tco_1(sc, off) \ 108 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 109#define ichwd_read_tco_2(sc, off) \ 110 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 111#define ichwd_read_tco_4(sc, off) \ 112 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 113#define ichwd_read_smi_4(sc, off) \ 114 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 115#define ichwd_read_gcs_4(sc, off) \ 116 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 117 118#define ichwd_write_tco_1(sc, off, val) \ 119 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 120#define ichwd_write_tco_2(sc, off, val) \ 121 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 122#define ichwd_write_tco_4(sc, off, val) \ 123 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 124#define ichwd_write_smi_4(sc, off, val) \ 125 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 126#define ichwd_write_gcs_4(sc, off, val) \ 127 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 128 129#define ichwd_verbose_printf(dev, ...) \ 130 do { \ 131 if (bootverbose) \ 132 device_printf(dev, __VA_ARGS__);\ 133 } while (0) 134 135static __inline void 136ichwd_intr_enable(struct ichwd_softc *sc) 137{ 138 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 139} 140 141static __inline void 142ichwd_intr_disable(struct ichwd_softc *sc) 143{ 144 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 145} 146 147static __inline void 148ichwd_sts_reset(struct ichwd_softc *sc) 149{ 150 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 151 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 152 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 153} 154 155static __inline void 156ichwd_tmr_enable(struct ichwd_softc *sc) 157{ 158 uint16_t cnt; 159 160 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 161 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 162 sc->active = 1; 163 ichwd_verbose_printf(sc->device, "timer enabled\n"); 164} 165 166static __inline void 167ichwd_tmr_disable(struct ichwd_softc *sc) 168{ 169 uint16_t cnt; 170 171 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 172 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 173 sc->active = 0; 174 ichwd_verbose_printf(sc->device, "timer disabled\n"); 175} 176 177static __inline void 178ichwd_tmr_reload(struct ichwd_softc *sc) 179{ 180 if (sc->ich_version <= 5) 181 ichwd_write_tco_1(sc, TCO_RLD, 1); 182 else 183 ichwd_write_tco_2(sc, TCO_RLD, 1); 184 185 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 186} 187 188static __inline void 189ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 190{ 191 192 /* 193 * If the datasheets are to be believed, the minimum value 194 * actually varies from chipset to chipset - 4 for ICH5 and 2 for 195 * all other chipsets. I suspect this is a bug in the ICH5 196 * datasheet and that the minimum is uniformly 2, but I'd rather 197 * err on the side of caution. 198 */ 199 if (timeout < 4) 200 timeout = 4; 201 202 if (sc->ich_version <= 5) { 203 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 204 205 tmr_val8 &= 0xc0; 206 if (timeout > 0xbf) 207 timeout = 0xbf; 208 tmr_val8 |= timeout; 209 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 210 } else { 211 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 212 213 tmr_val16 &= 0xfc00; 214 if (timeout > 0x0bff) 215 timeout = 0x0bff; 216 tmr_val16 |= timeout; 217 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 218 } 219 220 sc->timeout = timeout; 221 222 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 223} 224 225static __inline int 226ichwd_clear_noreboot(struct ichwd_softc *sc) 227{ 228 uint32_t status; 229 int rc = 0; 230 231 /* try to clear the NO_REBOOT bit */ 232 if (sc->ich_version <= 5) { 233 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 234 status &= ~ICH_GEN_STA_NO_REBOOT; 235 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 236 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 237 if (status & ICH_GEN_STA_NO_REBOOT) 238 rc = EIO; 239 } else { 240 status = ichwd_read_gcs_4(sc, 0); 241 status &= ~ICH_GCS_NO_REBOOT; 242 ichwd_write_gcs_4(sc, 0, status); 243 status = ichwd_read_gcs_4(sc, 0); 244 if (status & ICH_GCS_NO_REBOOT) 245 rc = EIO; 246 } 247 248 if (rc) 249 device_printf(sc->device, 250 "ICH WDT present but disabled in BIOS or hardware\n"); 251 252 return (rc); 253} 254 255/* 256 * Watchdog event handler. 257 */ 258static void 259ichwd_event(void *arg, unsigned int cmd, int *error) 260{ 261 struct ichwd_softc *sc = arg; 262 unsigned int timeout; 263 264 /* convert from power-of-two-ns to WDT ticks */ 265 cmd &= WD_INTERVAL; 266 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 267 if (cmd) { 268 if (timeout != sc->timeout) { 269 if (!sc->active) 270 ichwd_tmr_enable(sc); 271 ichwd_tmr_set(sc, timeout); 272 } 273 ichwd_tmr_reload(sc); 274 *error = 0; 275 } else { 276 if (sc->active) 277 ichwd_tmr_disable(sc); 278 } 279} 280 281static device_t 282ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 283{ 284 struct ichwd_device *id; 285 device_t ich = NULL; 286 287 /* look for an ICH LPC interface bridge */ 288 for (id = ichwd_devices; id->desc != NULL; ++id) 289 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 290 break; 291 292 if (ich == NULL) 293 return (NULL); 294 295 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 296 id->version, id->desc); 297 298 if (id_p) 299 *id_p = id; 300 301 return (ich); 302} 303 304/* 305 * Look for an ICH LPC interface bridge. If one is found, register an 306 * ichwd device. There can be only one. 307 */ 308static void 309ichwd_identify(driver_t *driver, device_t parent) 310{ 311 struct ichwd_device *id_p; 312 device_t ich = NULL; 313 device_t dev; 314 uint32_t rcba; 315 int rc; 316 317 ich = ichwd_find_ich_lpc_bridge(&id_p); 318 if (ich == NULL) 319 return; 320 321 /* good, add child to bus */ 322 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 323 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 324 325 if (dev == NULL) 326 return; 327 328 device_set_desc_copy(dev, id_p->desc); 329 330 if (id_p->version >= 6) { 331 /* get RCBA (root complex base address) */ 332 rcba = pci_read_config(ich, ICH_RCBA, 4); 333 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 334 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 335 if (rc) 336 ichwd_verbose_printf(dev, 337 "Can not set memory resource for RCBA\n"); 338 } 339} 340 341static int 342ichwd_probe(device_t dev) 343{ 344 345 (void)dev; 346 return (0); 347} 348 349static int 350ichwd_attach(device_t dev) 351{ 352 struct ichwd_softc *sc; 353 struct ichwd_device *id_p; 354 device_t ich; 355 unsigned int pmbase = 0; 356 357 sc = device_get_softc(dev); 358 sc->device = dev; 359 360 ich = ichwd_find_ich_lpc_bridge(&id_p); 361 if (ich == NULL) { 362 device_printf(sc->device, "Can not find ICH device.\n"); 363 goto fail; 364 } 365 sc->ich = ich; 366 sc->ich_version = id_p->version; 367 368 /* get ACPI base address */ 369 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 370 if (pmbase == 0) { 371 device_printf(dev, "ICH PMBASE register is empty\n"); 372 goto fail; 373 } 374 375 /* allocate I/O register space */ 376 sc->smi_rid = 0; 377 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 378 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 379 RF_ACTIVE | RF_SHAREABLE); 380 if (sc->smi_res == NULL) { 381 device_printf(dev, "unable to reserve SMI registers\n"); 382 goto fail; 383 } 384 sc->smi_bst = rman_get_bustag(sc->smi_res); 385 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 386 387 sc->tco_rid = 1; 388 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 389 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 390 RF_ACTIVE | RF_SHAREABLE); 391 if (sc->tco_res == NULL) { 392 device_printf(dev, "unable to reserve TCO registers\n"); 393 goto fail; 394 } 395 sc->tco_bst = rman_get_bustag(sc->tco_res); 396 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 397 398 sc->gcs_rid = 0; 399 if (sc->ich_version >= 6) { 400 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 401 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 402 if (sc->gcs_res == NULL) { 403 device_printf(dev, "unable to reserve GCS registers\n"); 404 goto fail; 405 } 406 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 407 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 408 } else { 409 sc->gcs_res = 0; 410 sc->gcs_bst = 0; 411 sc->gcs_bsh = 0; 412 } 413 414 if (ichwd_clear_noreboot(sc) != 0) 415 goto fail; 416 417 device_printf(dev, "%s (ICH%d or equivalent)\n", 418 device_get_desc(dev), sc->ich_version); 419 420 /* reset the watchdog status registers */ 421 ichwd_sts_reset(sc); 422 423 /* make sure the WDT starts out inactive */ 424 ichwd_tmr_disable(sc); 425 426 /* register the watchdog event handler */ 427 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 428 429 /* enable watchdog timeout interrupts */ 430 ichwd_intr_enable(sc); 431 432 return (0); 433 fail: 434 sc = device_get_softc(dev); 435 if (sc->tco_res != NULL) 436 bus_release_resource(dev, SYS_RES_IOPORT, 437 sc->tco_rid, sc->tco_res); 438 if (sc->smi_res != NULL) 439 bus_release_resource(dev, SYS_RES_IOPORT, 440 sc->smi_rid, sc->smi_res); 441 if (sc->gcs_res != NULL) 442 bus_release_resource(ich, SYS_RES_MEMORY, 443 sc->gcs_rid, sc->gcs_res); 444 445 return (ENXIO); 446} 447 448static int 449ichwd_detach(device_t dev) 450{ 451 struct ichwd_softc *sc; 452 device_t ich = NULL; 453 454 sc = device_get_softc(dev); 455 456 /* halt the watchdog timer */ 457 if (sc->active) 458 ichwd_tmr_disable(sc); 459 460 /* disable watchdog timeout interrupts */ 461 ichwd_intr_disable(sc); 462 463 /* deregister event handler */ 464 if (sc->ev_tag != NULL) 465 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 466 sc->ev_tag = NULL; 467 468 /* reset the watchdog status registers */ 469 ichwd_sts_reset(sc); 470 471 /* deallocate I/O register space */ 472 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 473 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 474 475 /* deallocate memory resource */ 476 ich = ichwd_find_ich_lpc_bridge(NULL); 477 if (sc->gcs_res && ich) 478 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 479 480 return (0); 481} 482 483static device_method_t ichwd_methods[] = { 484 DEVMETHOD(device_identify, ichwd_identify), 485 DEVMETHOD(device_probe, ichwd_probe), 486 DEVMETHOD(device_attach, ichwd_attach), 487 DEVMETHOD(device_detach, ichwd_detach), 488 DEVMETHOD(device_shutdown, ichwd_detach), 489 {0,0} 490}; 491 492static driver_t ichwd_driver = { 493 "ichwd", 494 ichwd_methods, 495 sizeof(struct ichwd_softc), 496}; 497 498static int 499ichwd_modevent(module_t mode, int type, void *data) 500{ 501 int error = 0; 502 503 switch (type) { 504 case MOD_LOAD: 505 printf("ichwd module loaded\n"); 506 break; 507 case MOD_UNLOAD: 508 printf("ichwd module unloaded\n"); 509 break; 510 case MOD_SHUTDOWN: 511 printf("ichwd module shutting down\n"); 512 break; 513 } 514 return (error); 515} 516 517DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL); 518