ichwd.c revision 175013
1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 175013 2007-12-31 11:44:01Z des $"); 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/module.h> 64#include <sys/systm.h> 65#include <sys/bus.h> 66#include <machine/bus.h> 67#include <sys/rman.h> 68#include <machine/resource.h> 69#include <sys/watchdog.h> 70 71#include <dev/pci/pcivar.h> 72 73#include <dev/ichwd/ichwd.h> 74 75static struct ichwd_device ichwd_devices[] = { 76 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 77 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 78 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 79 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 80 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 81 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 82 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 83 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 84 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 85 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 86 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 87 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 88 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 89 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 90 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 91 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 92 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 93 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 94 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 95 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 96 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 97 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 98 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 99 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 100 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 101 { 0, NULL, 0 }, 102}; 103 104static devclass_t ichwd_devclass; 105 106#define ichwd_read_tco_1(sc, off) \ 107 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 108#define ichwd_read_tco_2(sc, off) \ 109 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 110#define ichwd_read_tco_4(sc, off) \ 111 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 112#define ichwd_read_smi_4(sc, off) \ 113 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 114#define ichwd_read_gcs_4(sc, off) \ 115 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 116 117#define ichwd_write_tco_1(sc, off, val) \ 118 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 119#define ichwd_write_tco_2(sc, off, val) \ 120 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 121#define ichwd_write_tco_4(sc, off, val) \ 122 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 123#define ichwd_write_smi_4(sc, off, val) \ 124 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 125#define ichwd_write_gcs_4(sc, off, val) \ 126 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 127 128#define ichwd_verbose_printf(dev, ...) \ 129 do { \ 130 if (bootverbose) \ 131 device_printf(dev, __VA_ARGS__);\ 132 } while (0) 133 134static __inline void 135ichwd_intr_enable(struct ichwd_softc *sc) 136{ 137 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 138} 139 140static __inline void 141ichwd_intr_disable(struct ichwd_softc *sc) 142{ 143 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 144} 145 146static __inline void 147ichwd_sts_reset(struct ichwd_softc *sc) 148{ 149 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 150 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 151 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 152} 153 154static __inline void 155ichwd_tmr_enable(struct ichwd_softc *sc) 156{ 157 uint16_t cnt; 158 159 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 160 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 161 sc->active = 1; 162 ichwd_verbose_printf(sc->device, "timer enabled\n"); 163} 164 165static __inline void 166ichwd_tmr_disable(struct ichwd_softc *sc) 167{ 168 uint16_t cnt; 169 170 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 171 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 172 sc->active = 0; 173 ichwd_verbose_printf(sc->device, "timer disabled\n"); 174} 175 176static __inline void 177ichwd_tmr_reload(struct ichwd_softc *sc) 178{ 179 if (sc->ich_version <= 5) 180 ichwd_write_tco_1(sc, TCO_RLD, 1); 181 else 182 ichwd_write_tco_2(sc, TCO_RLD, 1); 183 184 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 185} 186 187static __inline void 188ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 189{ 190 191 /* 192 * If the datasheets are to be believed, the minimum value 193 * actually varies from chipset to chipset - 4 for ICH5 and 2 for 194 * all other chipsets. I suspect this is a bug in the ICH5 195 * datasheet and that the minimum is uniformly 2, but I'd rather 196 * err on the side of caution. 197 */ 198 if (timeout < 4) 199 timeout = 4; 200 201 if (sc->ich_version <= 5) { 202 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 203 204 tmr_val8 &= 0xc0; 205 if (timeout > 0xbf) 206 timeout = 0xbf; 207 tmr_val8 |= timeout; 208 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 209 } else { 210 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 211 212 tmr_val16 &= 0xfc00; 213 if (timeout > 0x0bff) 214 timeout = 0x0bff; 215 tmr_val16 |= timeout; 216 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 217 } 218 219 sc->timeout = timeout; 220 221 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 222} 223 224static __inline int 225ichwd_clear_noreboot(struct ichwd_softc *sc) 226{ 227 uint32_t status; 228 int rc = 0; 229 230 /* try to clear the NO_REBOOT bit */ 231 if (sc->ich_version <= 5) { 232 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 233 status &= ~ICH_GEN_STA_NO_REBOOT; 234 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 235 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 236 if (status & ICH_GEN_STA_NO_REBOOT) 237 rc = EIO; 238 } else { 239 status = ichwd_read_gcs_4(sc, 0); 240 status &= ~ICH_GCS_NO_REBOOT; 241 ichwd_write_gcs_4(sc, 0, status); 242 status = ichwd_read_gcs_4(sc, 0); 243 if (status & ICH_GCS_NO_REBOOT) 244 rc = EIO; 245 } 246 247 if (rc) 248 device_printf(sc->device, 249 "ICH WDT present but disabled in BIOS or hardware\n"); 250 251 return (rc); 252} 253 254/* 255 * Watchdog event handler. 256 */ 257static void 258ichwd_event(void *arg, unsigned int cmd, int *error) 259{ 260 struct ichwd_softc *sc = arg; 261 unsigned int timeout; 262 263 /* convert from power-of-two-ns to WDT ticks */ 264 cmd &= WD_INTERVAL; 265 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 266 if (cmd) { 267 if (timeout != sc->timeout) { 268 if (!sc->active) 269 ichwd_tmr_enable(sc); 270 ichwd_tmr_set(sc, timeout); 271 } 272 ichwd_tmr_reload(sc); 273 *error = 0; 274 } else { 275 if (sc->active) 276 ichwd_tmr_disable(sc); 277 } 278} 279 280static device_t 281ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 282{ 283 struct ichwd_device *id; 284 device_t ich = NULL; 285 286 /* look for an ICH LPC interface bridge */ 287 for (id = ichwd_devices; id->desc != NULL; ++id) 288 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 289 break; 290 291 if (ich == NULL) 292 return (NULL); 293 294 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 295 id->version, id->desc); 296 297 if (id_p) 298 *id_p = id; 299 300 return (ich); 301} 302 303/* 304 * Look for an ICH LPC interface bridge. If one is found, register an 305 * ichwd device. There can be only one. 306 */ 307static void 308ichwd_identify(driver_t *driver, device_t parent) 309{ 310 struct ichwd_device *id_p; 311 device_t ich = NULL; 312 device_t dev; 313 uint32_t rcba; 314 int rc; 315 316 ich = ichwd_find_ich_lpc_bridge(&id_p); 317 if (ich == NULL) 318 return; 319 320 /* good, add child to bus */ 321 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 322 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 323 324 if (dev == NULL) 325 return; 326 327 device_set_desc_copy(dev, id_p->desc); 328 329 if (id_p->version >= 6) { 330 /* get RCBA (root complex base address) */ 331 rcba = pci_read_config(ich, ICH_RCBA, 4); 332 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 333 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 334 if (rc) 335 ichwd_verbose_printf(dev, 336 "Can not set memory resource for RCBA\n"); 337 } 338} 339 340static int 341ichwd_probe(device_t dev) 342{ 343 344 (void)dev; 345 return (0); 346} 347 348static int 349ichwd_attach(device_t dev) 350{ 351 struct ichwd_softc *sc; 352 struct ichwd_device *id_p; 353 device_t ich; 354 unsigned int pmbase = 0; 355 356 sc = device_get_softc(dev); 357 sc->device = dev; 358 359 ich = ichwd_find_ich_lpc_bridge(&id_p); 360 if (ich == NULL) { 361 device_printf(sc->device, "Can not find ICH device.\n"); 362 goto fail; 363 } 364 sc->ich = ich; 365 sc->ich_version = id_p->version; 366 367 /* get ACPI base address */ 368 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 369 if (pmbase == 0) { 370 device_printf(dev, "ICH PMBASE register is empty\n"); 371 goto fail; 372 } 373 374 /* allocate I/O register space */ 375 sc->smi_rid = 0; 376 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 377 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 378 RF_ACTIVE | RF_SHAREABLE); 379 if (sc->smi_res == NULL) { 380 device_printf(dev, "unable to reserve SMI registers\n"); 381 goto fail; 382 } 383 sc->smi_bst = rman_get_bustag(sc->smi_res); 384 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 385 386 sc->tco_rid = 1; 387 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 388 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 389 RF_ACTIVE | RF_SHAREABLE); 390 if (sc->tco_res == NULL) { 391 device_printf(dev, "unable to reserve TCO registers\n"); 392 goto fail; 393 } 394 sc->tco_bst = rman_get_bustag(sc->tco_res); 395 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 396 397 sc->gcs_rid = 0; 398 if (sc->ich_version >= 6) { 399 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 400 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 401 if (sc->gcs_res == NULL) { 402 device_printf(dev, "unable to reserve GCS registers\n"); 403 goto fail; 404 } 405 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 406 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 407 } else { 408 sc->gcs_res = 0; 409 sc->gcs_bst = 0; 410 sc->gcs_bsh = 0; 411 } 412 413 if (ichwd_clear_noreboot(sc) != 0) 414 goto fail; 415 416 device_printf(dev, "%s (ICH%d or equivalent)\n", 417 device_get_desc(dev), sc->ich_version); 418 419 /* reset the watchdog status registers */ 420 ichwd_sts_reset(sc); 421 422 /* make sure the WDT starts out inactive */ 423 ichwd_tmr_disable(sc); 424 425 /* register the watchdog event handler */ 426 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 427 428 /* enable watchdog timeout interrupts */ 429 ichwd_intr_enable(sc); 430 431 return (0); 432 fail: 433 sc = device_get_softc(dev); 434 if (sc->tco_res != NULL) 435 bus_release_resource(dev, SYS_RES_IOPORT, 436 sc->tco_rid, sc->tco_res); 437 if (sc->smi_res != NULL) 438 bus_release_resource(dev, SYS_RES_IOPORT, 439 sc->smi_rid, sc->smi_res); 440 if (sc->gcs_res != NULL) 441 bus_release_resource(ich, SYS_RES_MEMORY, 442 sc->gcs_rid, sc->gcs_res); 443 444 return (ENXIO); 445} 446 447static int 448ichwd_detach(device_t dev) 449{ 450 struct ichwd_softc *sc; 451 device_t ich = NULL; 452 453 sc = device_get_softc(dev); 454 455 /* halt the watchdog timer */ 456 if (sc->active) 457 ichwd_tmr_disable(sc); 458 459 /* disable watchdog timeout interrupts */ 460 ichwd_intr_disable(sc); 461 462 /* deregister event handler */ 463 if (sc->ev_tag != NULL) 464 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 465 sc->ev_tag = NULL; 466 467 /* reset the watchdog status registers */ 468 ichwd_sts_reset(sc); 469 470 /* deallocate I/O register space */ 471 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 472 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 473 474 /* deallocate memory resource */ 475 ich = ichwd_find_ich_lpc_bridge(NULL); 476 if (sc->gcs_res && ich) 477 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 478 479 return (0); 480} 481 482static device_method_t ichwd_methods[] = { 483 DEVMETHOD(device_identify, ichwd_identify), 484 DEVMETHOD(device_probe, ichwd_probe), 485 DEVMETHOD(device_attach, ichwd_attach), 486 DEVMETHOD(device_detach, ichwd_detach), 487 DEVMETHOD(device_shutdown, ichwd_detach), 488 {0,0} 489}; 490 491static driver_t ichwd_driver = { 492 "ichwd", 493 ichwd_methods, 494 sizeof(struct ichwd_softc), 495}; 496 497static int 498ichwd_modevent(module_t mode, int type, void *data) 499{ 500 int error = 0; 501 502 switch (type) { 503 case MOD_LOAD: 504 printf("ichwd module loaded\n"); 505 break; 506 case MOD_UNLOAD: 507 printf("ichwd module unloaded\n"); 508 break; 509 case MOD_SHUTDOWN: 510 printf("ichwd module shutting down\n"); 511 break; 512 } 513 return (error); 514} 515 516DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL); 517