ichwd.c revision 173661
1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 173661 2007-11-15 23:59:36Z jfv $"); 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/module.h> 64#include <sys/systm.h> 65#include <sys/bus.h> 66#include <machine/bus.h> 67#include <sys/rman.h> 68#include <machine/resource.h> 69#include <sys/watchdog.h> 70 71#include <dev/pci/pcivar.h> 72 73#include <dev/ichwd/ichwd.h> 74 75static struct ichwd_device ichwd_devices[] = { 76 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 77 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 78 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 79 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 80 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 81 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 82 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 83 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 84 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 85 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 86 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 87 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 88 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 89 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 90 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 91 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 92 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 93 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 94 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 95 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 96 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 97 { 0, NULL, 0 }, 98}; 99 100static devclass_t ichwd_devclass; 101 102#define ichwd_read_tco_1(sc, off) \ 103 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 104#define ichwd_read_tco_2(sc, off) \ 105 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 106#define ichwd_read_tco_4(sc, off) \ 107 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 108#define ichwd_read_smi_4(sc, off) \ 109 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 110#define ichwd_read_gcs_4(sc, off) \ 111 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 112 113#define ichwd_write_tco_1(sc, off, val) \ 114 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 115#define ichwd_write_tco_2(sc, off, val) \ 116 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 117#define ichwd_write_tco_4(sc, off, val) \ 118 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 119#define ichwd_write_smi_4(sc, off, val) \ 120 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 121#define ichwd_write_gcs_4(sc, off, val) \ 122 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 123 124#define ichwd_verbose_printf(dev, ...) \ 125 do { \ 126 if (bootverbose) \ 127 device_printf(dev, __VA_ARGS__);\ 128 } while (0) 129 130static __inline void 131ichwd_intr_enable(struct ichwd_softc *sc) 132{ 133 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 134} 135 136static __inline void 137ichwd_intr_disable(struct ichwd_softc *sc) 138{ 139 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 140} 141 142static __inline void 143ichwd_sts_reset(struct ichwd_softc *sc) 144{ 145 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 146 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 147 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 148} 149 150static __inline void 151ichwd_tmr_enable(struct ichwd_softc *sc) 152{ 153 uint16_t cnt; 154 155 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 156 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 157 sc->active = 1; 158 ichwd_verbose_printf(sc->device, "timer enabled\n"); 159} 160 161static __inline void 162ichwd_tmr_disable(struct ichwd_softc *sc) 163{ 164 uint16_t cnt; 165 166 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 167 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 168 sc->active = 0; 169 ichwd_verbose_printf(sc->device, "timer disabled\n"); 170} 171 172static __inline void 173ichwd_tmr_reload(struct ichwd_softc *sc) 174{ 175 if (sc->ich_version <= 5) 176 ichwd_write_tco_1(sc, TCO_RLD, 1); 177 else 178 ichwd_write_tco_2(sc, TCO_RLD, 1); 179 180 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 181} 182 183static __inline void 184ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 185{ 186 187 /* 188 * If the datasheets are to be believed, the minimum value 189 * actually varies from chipset to chipset - 4 for ICH5 and 2 for 190 * all other chipsets. I suspect this is a bug in the ICH5 191 * datasheet and that the minimum is uniformly 2, but I'd rather 192 * err on the side of caution. 193 */ 194 if (timeout < 4) 195 timeout = 4; 196 197 if (sc->ich_version <= 5) { 198 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 199 200 tmr_val8 &= 0xc0; 201 if (timeout > 0xbf) 202 timeout = 0xbf; 203 tmr_val8 |= timeout; 204 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 205 } else { 206 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 207 208 tmr_val16 &= 0xfc00; 209 if (timeout > 0x0bff) 210 timeout = 0x0bff; 211 tmr_val16 |= timeout; 212 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 213 } 214 215 sc->timeout = timeout; 216 217 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 218} 219 220static __inline int 221ichwd_clear_noreboot(struct ichwd_softc *sc) 222{ 223 uint32_t status; 224 int rc = 0; 225 226 /* try to clear the NO_REBOOT bit */ 227 if (sc->ich_version <= 5) { 228 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 229 status &= ~ICH_GEN_STA_NO_REBOOT; 230 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 231 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 232 if (status & ICH_GEN_STA_NO_REBOOT) 233 rc = EIO; 234 } else { 235 status = ichwd_read_gcs_4(sc, 0); 236 status &= ~ICH_GCS_NO_REBOOT; 237 ichwd_write_gcs_4(sc, 0, status); 238 status = ichwd_read_gcs_4(sc, 0); 239 if (status & ICH_GCS_NO_REBOOT) 240 rc = EIO; 241 } 242 243 if (rc) 244 device_printf(sc->device, 245 "ICH WDT present but disabled in BIOS or hardware\n"); 246 247 return (rc); 248} 249 250/* 251 * Watchdog event handler. 252 */ 253static void 254ichwd_event(void *arg, unsigned int cmd, int *error) 255{ 256 struct ichwd_softc *sc = arg; 257 unsigned int timeout; 258 259 /* convert from power-of-two-ns to WDT ticks */ 260 cmd &= WD_INTERVAL; 261 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 262 if (cmd) { 263 if (timeout != sc->timeout) { 264 if (!sc->active) 265 ichwd_tmr_enable(sc); 266 ichwd_tmr_set(sc, timeout); 267 } 268 ichwd_tmr_reload(sc); 269 *error = 0; 270 } else { 271 if (sc->active) 272 ichwd_tmr_disable(sc); 273 } 274} 275 276static device_t 277ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 278{ 279 struct ichwd_device *id; 280 device_t ich = NULL; 281 282 /* look for an ICH LPC interface bridge */ 283 for (id = ichwd_devices; id->desc != NULL; ++id) 284 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 285 break; 286 287 if (ich == NULL) 288 return (NULL); 289 290 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 291 id->version, id->desc); 292 293 if (id_p) 294 *id_p = id; 295 296 return (ich); 297} 298 299/* 300 * Look for an ICH LPC interface bridge. If one is found, register an 301 * ichwd device. There can be only one. 302 */ 303static void 304ichwd_identify(driver_t *driver, device_t parent) 305{ 306 struct ichwd_device *id_p; 307 device_t ich = NULL; 308 device_t dev; 309 uint32_t rcba; 310 int rc; 311 312 ich = ichwd_find_ich_lpc_bridge(&id_p); 313 if (ich == NULL) 314 return; 315 316 /* good, add child to bus */ 317 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 318 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 319 320 if (dev == NULL) 321 return; 322 323 device_set_desc_copy(dev, id_p->desc); 324 325 if (id_p->version >= 6) { 326 /* get RCBA (root complex base address) */ 327 rcba = pci_read_config(ich, ICH_RCBA, 4); 328 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 329 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 330 if (rc) 331 ichwd_verbose_printf(dev, 332 "Can not set memory resource for RCBA\n"); 333 } 334} 335 336static int 337ichwd_probe(device_t dev) 338{ 339 340 (void)dev; 341 return (0); 342} 343 344static int 345ichwd_attach(device_t dev) 346{ 347 struct ichwd_softc *sc; 348 struct ichwd_device *id_p; 349 device_t ich; 350 unsigned int pmbase = 0; 351 352 sc = device_get_softc(dev); 353 sc->device = dev; 354 355 ich = ichwd_find_ich_lpc_bridge(&id_p); 356 if (ich == NULL) { 357 device_printf(sc->device, "Can not find ICH device.\n"); 358 goto fail; 359 } 360 sc->ich = ich; 361 sc->ich_version = id_p->version; 362 363 /* get ACPI base address */ 364 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 365 if (pmbase == 0) { 366 device_printf(dev, "ICH PMBASE register is empty\n"); 367 goto fail; 368 } 369 370 /* allocate I/O register space */ 371 sc->smi_rid = 0; 372 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 373 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 374 RF_ACTIVE | RF_SHAREABLE); 375 if (sc->smi_res == NULL) { 376 device_printf(dev, "unable to reserve SMI registers\n"); 377 goto fail; 378 } 379 sc->smi_bst = rman_get_bustag(sc->smi_res); 380 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 381 382 sc->tco_rid = 1; 383 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 384 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 385 RF_ACTIVE | RF_SHAREABLE); 386 if (sc->tco_res == NULL) { 387 device_printf(dev, "unable to reserve TCO registers\n"); 388 goto fail; 389 } 390 sc->tco_bst = rman_get_bustag(sc->tco_res); 391 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 392 393 sc->gcs_rid = 0; 394 if (sc->ich_version >= 6) { 395 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 396 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 397 if (sc->gcs_res == NULL) { 398 device_printf(dev, "unable to reserve GCS registers\n"); 399 goto fail; 400 } 401 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 402 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 403 } else { 404 sc->gcs_res = 0; 405 sc->gcs_bst = 0; 406 sc->gcs_bsh = 0; 407 } 408 409 if (ichwd_clear_noreboot(sc) != 0) 410 goto fail; 411 412 device_printf(dev, "%s (ICH%d or equivalent)\n", 413 device_get_desc(dev), sc->ich_version); 414 415 /* reset the watchdog status registers */ 416 ichwd_sts_reset(sc); 417 418 /* make sure the WDT starts out inactive */ 419 ichwd_tmr_disable(sc); 420 421 /* register the watchdog event handler */ 422 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 423 424 /* enable watchdog timeout interrupts */ 425 ichwd_intr_enable(sc); 426 427 return (0); 428 fail: 429 sc = device_get_softc(dev); 430 if (sc->tco_res != NULL) 431 bus_release_resource(dev, SYS_RES_IOPORT, 432 sc->tco_rid, sc->tco_res); 433 if (sc->smi_res != NULL) 434 bus_release_resource(dev, SYS_RES_IOPORT, 435 sc->smi_rid, sc->smi_res); 436 if (sc->gcs_res != NULL) 437 bus_release_resource(ich, SYS_RES_MEMORY, 438 sc->gcs_rid, sc->gcs_res); 439 440 return (ENXIO); 441} 442 443static int 444ichwd_detach(device_t dev) 445{ 446 struct ichwd_softc *sc; 447 device_t ich = NULL; 448 449 sc = device_get_softc(dev); 450 451 /* halt the watchdog timer */ 452 if (sc->active) 453 ichwd_tmr_disable(sc); 454 455 /* disable watchdog timeout interrupts */ 456 ichwd_intr_disable(sc); 457 458 /* deregister event handler */ 459 if (sc->ev_tag != NULL) 460 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 461 sc->ev_tag = NULL; 462 463 /* reset the watchdog status registers */ 464 ichwd_sts_reset(sc); 465 466 /* deallocate I/O register space */ 467 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 468 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 469 470 /* deallocate memory resource */ 471 ich = ichwd_find_ich_lpc_bridge(NULL); 472 if (sc->gcs_res && ich) 473 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 474 475 return (0); 476} 477 478static device_method_t ichwd_methods[] = { 479 DEVMETHOD(device_identify, ichwd_identify), 480 DEVMETHOD(device_probe, ichwd_probe), 481 DEVMETHOD(device_attach, ichwd_attach), 482 DEVMETHOD(device_detach, ichwd_detach), 483 DEVMETHOD(device_shutdown, ichwd_detach), 484 {0,0} 485}; 486 487static driver_t ichwd_driver = { 488 "ichwd", 489 ichwd_methods, 490 sizeof(struct ichwd_softc), 491}; 492 493static int 494ichwd_modevent(module_t mode, int type, void *data) 495{ 496 int error = 0; 497 498 switch (type) { 499 case MOD_LOAD: 500 printf("ichwd module loaded\n"); 501 break; 502 case MOD_UNLOAD: 503 printf("ichwd module unloaded\n"); 504 break; 505 case MOD_SHUTDOWN: 506 printf("ichwd module shutting down\n"); 507 break; 508 } 509 return (error); 510} 511 512DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL); 513