ichwd.c revision 171820
1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/dev/ichwd/ichwd.c 171820 2007-08-13 18:52:37Z des $"); 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/module.h> 64#include <sys/systm.h> 65#include <sys/bus.h> 66#include <machine/bus.h> 67#include <sys/rman.h> 68#include <machine/resource.h> 69#include <sys/watchdog.h> 70 71#include <dev/pci/pcivar.h> 72 73#include <dev/ichwd/ichwd.h> 74 75static struct ichwd_device ichwd_devices[] = { 76 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 77 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 78 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 79 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 80 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 81 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 82 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 83 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 84 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 85 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 86 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 87 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 88 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 89 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 90 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 91 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 92 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 93 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 94 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 95 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 96 { 0, NULL, 0 }, 97}; 98 99static devclass_t ichwd_devclass; 100 101#define ichwd_read_tco_1(sc, off) \ 102 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 103#define ichwd_read_tco_2(sc, off) \ 104 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 105#define ichwd_read_tco_4(sc, off) \ 106 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 107#define ichwd_read_smi_4(sc, off) \ 108 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 109#define ichwd_read_gcs_4(sc, off) \ 110 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 111 112#define ichwd_write_tco_1(sc, off, val) \ 113 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 114#define ichwd_write_tco_2(sc, off, val) \ 115 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 116#define ichwd_write_tco_4(sc, off, val) \ 117 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 118#define ichwd_write_smi_4(sc, off, val) \ 119 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 120#define ichwd_write_gcs_4(sc, off, val) \ 121 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 122 123#define ichwd_verbose_printf(dev, ...) \ 124 do { \ 125 if (bootverbose) \ 126 device_printf(dev, __VA_ARGS__);\ 127 } while (0) 128 129static __inline void 130ichwd_intr_enable(struct ichwd_softc *sc) 131{ 132 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 133} 134 135static __inline void 136ichwd_intr_disable(struct ichwd_softc *sc) 137{ 138 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 139} 140 141static __inline void 142ichwd_sts_reset(struct ichwd_softc *sc) 143{ 144 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 145 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 146 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 147} 148 149static __inline void 150ichwd_tmr_enable(struct ichwd_softc *sc) 151{ 152 uint16_t cnt; 153 154 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 155 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 156 sc->active = 1; 157 ichwd_verbose_printf(sc->device, "timer enabled\n"); 158} 159 160static __inline void 161ichwd_tmr_disable(struct ichwd_softc *sc) 162{ 163 uint16_t cnt; 164 165 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 166 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 167 sc->active = 0; 168 ichwd_verbose_printf(sc->device, "timer disabled\n"); 169} 170 171static __inline void 172ichwd_tmr_reload(struct ichwd_softc *sc) 173{ 174 if (sc->ich_version <= 5) 175 ichwd_write_tco_1(sc, TCO_RLD, 1); 176 else 177 ichwd_write_tco_2(sc, TCO_RLD, 1); 178 179 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 180} 181 182static __inline void 183ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 184{ 185 186 /* 187 * If the datasheets are to be believed, the minimum value 188 * actually varies from chipset to chipset - 4 for ICH5 and 2 for 189 * all other chipsets. I suspect this is a bug in the ICH5 190 * datasheet and that the minimum is uniformly 2, but I'd rather 191 * err on the side of caution. 192 */ 193 if (timeout < 4) 194 timeout = 4; 195 196 if (sc->ich_version <= 5) { 197 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 198 199 tmr_val8 &= 0xc0; 200 if (timeout > 0xbf) 201 timeout = 0xbf; 202 tmr_val8 |= timeout; 203 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 204 } else { 205 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 206 207 tmr_val16 &= 0xfc00; 208 if (timeout > 0x0bff) 209 timeout = 0x0bff; 210 tmr_val16 |= timeout; 211 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 212 } 213 214 sc->timeout = timeout; 215 216 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 217} 218 219static __inline int 220ichwd_clear_noreboot(struct ichwd_softc *sc) 221{ 222 uint32_t status; 223 int rc = 0; 224 225 /* try to clear the NO_REBOOT bit */ 226 if (sc->ich_version <= 5) { 227 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 228 status &= ~ICH_GEN_STA_NO_REBOOT; 229 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 230 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 231 if (status & ICH_GEN_STA_NO_REBOOT) 232 rc = EIO; 233 } else { 234 status = ichwd_read_gcs_4(sc, 0); 235 status &= ~ICH_GCS_NO_REBOOT; 236 ichwd_write_gcs_4(sc, 0, status); 237 status = ichwd_read_gcs_4(sc, 0); 238 if (status & ICH_GCS_NO_REBOOT) 239 rc = EIO; 240 } 241 242 if (rc) 243 device_printf(sc->device, 244 "ICH WDT present but disabled in BIOS or hardware\n"); 245 246 return (rc); 247} 248 249/* 250 * Watchdog event handler. 251 */ 252static void 253ichwd_event(void *arg, unsigned int cmd, int *error) 254{ 255 struct ichwd_softc *sc = arg; 256 unsigned int timeout; 257 258 /* convert from power-of-two-ns to WDT ticks */ 259 cmd &= WD_INTERVAL; 260 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 261 if (cmd) { 262 if (timeout != sc->timeout) { 263 if (!sc->active) 264 ichwd_tmr_enable(sc); 265 ichwd_tmr_set(sc, timeout); 266 } 267 ichwd_tmr_reload(sc); 268 *error = 0; 269 } else { 270 if (sc->active) 271 ichwd_tmr_disable(sc); 272 } 273} 274 275static device_t 276ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 277{ 278 struct ichwd_device *id; 279 device_t ich = NULL; 280 281 /* look for an ICH LPC interface bridge */ 282 for (id = ichwd_devices; id->desc != NULL; ++id) 283 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 284 break; 285 286 if (ich == NULL) 287 return (NULL); 288 289 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 290 id->version, id->desc); 291 292 if (id_p) 293 *id_p = id; 294 295 return (ich); 296} 297 298/* 299 * Look for an ICH LPC interface bridge. If one is found, register an 300 * ichwd device. There can be only one. 301 */ 302static void 303ichwd_identify(driver_t *driver, device_t parent) 304{ 305 struct ichwd_device *id_p; 306 device_t ich = NULL; 307 device_t dev; 308 uint32_t rcba; 309 int rc; 310 311 ich = ichwd_find_ich_lpc_bridge(&id_p); 312 if (ich == NULL) 313 return; 314 315 /* good, add child to bus */ 316 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 317 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 318 319 if (dev == NULL) 320 return; 321 322 device_set_desc_copy(dev, id_p->desc); 323 324 if (id_p->version >= 6) { 325 /* get RCBA (root complex base address) */ 326 rcba = pci_read_config(ich, ICH_RCBA, 4); 327 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 328 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 329 if (rc) 330 ichwd_verbose_printf(dev, 331 "Can not set memory resource for RCBA\n"); 332 } 333} 334 335static int 336ichwd_probe(device_t dev) 337{ 338 339 (void)dev; 340 return (0); 341} 342 343static int 344ichwd_attach(device_t dev) 345{ 346 struct ichwd_softc *sc; 347 struct ichwd_device *id_p; 348 device_t ich; 349 unsigned int pmbase = 0; 350 351 sc = device_get_softc(dev); 352 sc->device = dev; 353 354 ich = ichwd_find_ich_lpc_bridge(&id_p); 355 if (ich == NULL) { 356 device_printf(sc->device, "Can not find ICH device.\n"); 357 goto fail; 358 } 359 sc->ich = ich; 360 sc->ich_version = id_p->version; 361 362 /* get ACPI base address */ 363 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 364 if (pmbase == 0) { 365 device_printf(dev, "ICH PMBASE register is empty\n"); 366 goto fail; 367 } 368 369 /* allocate I/O register space */ 370 sc->smi_rid = 0; 371 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 372 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 373 RF_ACTIVE | RF_SHAREABLE); 374 if (sc->smi_res == NULL) { 375 device_printf(dev, "unable to reserve SMI registers\n"); 376 goto fail; 377 } 378 sc->smi_bst = rman_get_bustag(sc->smi_res); 379 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 380 381 sc->tco_rid = 1; 382 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 383 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 384 RF_ACTIVE | RF_SHAREABLE); 385 if (sc->tco_res == NULL) { 386 device_printf(dev, "unable to reserve TCO registers\n"); 387 goto fail; 388 } 389 sc->tco_bst = rman_get_bustag(sc->tco_res); 390 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 391 392 sc->gcs_rid = 0; 393 if (sc->ich_version >= 6) { 394 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 395 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 396 if (sc->gcs_res == NULL) { 397 device_printf(dev, "unable to reserve GCS registers\n"); 398 goto fail; 399 } 400 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 401 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 402 } else { 403 sc->gcs_res = 0; 404 sc->gcs_bst = 0; 405 sc->gcs_bsh = 0; 406 } 407 408 if (ichwd_clear_noreboot(sc) != 0) 409 goto fail; 410 411 device_printf(dev, "%s (ICH%d or equivalent)\n", 412 device_get_desc(dev), sc->ich_version); 413 414 /* reset the watchdog status registers */ 415 ichwd_sts_reset(sc); 416 417 /* make sure the WDT starts out inactive */ 418 ichwd_tmr_disable(sc); 419 420 /* register the watchdog event handler */ 421 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 422 423 /* enable watchdog timeout interrupts */ 424 ichwd_intr_enable(sc); 425 426 return (0); 427 fail: 428 sc = device_get_softc(dev); 429 if (sc->tco_res != NULL) 430 bus_release_resource(dev, SYS_RES_IOPORT, 431 sc->tco_rid, sc->tco_res); 432 if (sc->smi_res != NULL) 433 bus_release_resource(dev, SYS_RES_IOPORT, 434 sc->smi_rid, sc->smi_res); 435 if (sc->gcs_res != NULL) 436 bus_release_resource(ich, SYS_RES_MEMORY, 437 sc->gcs_rid, sc->gcs_res); 438 439 return (ENXIO); 440} 441 442static int 443ichwd_detach(device_t dev) 444{ 445 struct ichwd_softc *sc; 446 device_t ich = NULL; 447 448 sc = device_get_softc(dev); 449 450 /* halt the watchdog timer */ 451 if (sc->active) 452 ichwd_tmr_disable(sc); 453 454 /* disable watchdog timeout interrupts */ 455 ichwd_intr_disable(sc); 456 457 /* deregister event handler */ 458 if (sc->ev_tag != NULL) 459 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 460 sc->ev_tag = NULL; 461 462 /* reset the watchdog status registers */ 463 ichwd_sts_reset(sc); 464 465 /* deallocate I/O register space */ 466 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 467 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 468 469 /* deallocate memory resource */ 470 ich = ichwd_find_ich_lpc_bridge(NULL); 471 if (sc->gcs_res && ich) 472 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 473 474 return (0); 475} 476 477static device_method_t ichwd_methods[] = { 478 DEVMETHOD(device_identify, ichwd_identify), 479 DEVMETHOD(device_probe, ichwd_probe), 480 DEVMETHOD(device_attach, ichwd_attach), 481 DEVMETHOD(device_detach, ichwd_detach), 482 DEVMETHOD(device_shutdown, ichwd_detach), 483 {0,0} 484}; 485 486static driver_t ichwd_driver = { 487 "ichwd", 488 ichwd_methods, 489 sizeof(struct ichwd_softc), 490}; 491 492static int 493ichwd_modevent(module_t mode, int type, void *data) 494{ 495 int error = 0; 496 497 switch (type) { 498 case MOD_LOAD: 499 printf("ichwd module loaded\n"); 500 break; 501 case MOD_UNLOAD: 502 printf("ichwd module unloaded\n"); 503 break; 504 case MOD_SHUTDOWN: 505 printf("ichwd module shutting down\n"); 506 break; 507 } 508 return (error); 509} 510 511DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL); 512