1139749Simp/*- 2119815Smarcel * Copyright (c) 2003 Marcel Moolenaar 3119815Smarcel * All rights reserved. 4119815Smarcel * 5119815Smarcel * Redistribution and use in source and binary forms, with or without 6119815Smarcel * modification, are permitted provided that the following conditions 7119815Smarcel * are met: 8119815Smarcel * 9119815Smarcel * 1. Redistributions of source code must retain the above copyright 10119815Smarcel * notice, this list of conditions and the following disclaimer. 11119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12119815Smarcel * notice, this list of conditions and the following disclaimer in the 13119815Smarcel * documentation and/or other materials provided with the distribution. 14119815Smarcel * 15119815Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16119815Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17119815Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18119815Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19119815Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20119815Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21119815Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22119815Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23119815Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24119815Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25119815Smarcel * 26119815Smarcel * $FreeBSD: releng/10.2/sys/dev/ic/z8530.h 155967 2006-02-24 02:03:35Z marcel $ 27119815Smarcel */ 28119815Smarcel 29137955Smarcel#ifndef _DEV_IC_Z8530_H_ 30137955Smarcel#define _DEV_IC_Z8530_H_ 31119815Smarcel 32119815Smarcel/* 33119815Smarcel * Channel B control: 0 34119815Smarcel * Channel B data: 1 35119815Smarcel * Channel A control: 2 36119815Smarcel * Channel A data: 3 37119815Smarcel */ 38155967Smarcel 39155967Smarcel/* The following apply when using a device-scoped bus handle */ 40155967Smarcel#define CHAN_A 2 41155967Smarcel#define CHAN_B 0 42155967Smarcel 43119815Smarcel#define REG_CTRL 0 44119815Smarcel#define REG_DATA 1 45119815Smarcel 46119815Smarcel/* Write registers. */ 47119815Smarcel#define WR_CR 0 /* Command Register. */ 48119815Smarcel#define WR_IDT 1 /* Interrupt and Data Transfer Mode. */ 49119815Smarcel#define WR_IV 2 /* Interrupt Vector (shared). */ 50119815Smarcel#define WR_RPC 3 /* Receive Parameters and Control. */ 51119815Smarcel#define WR_MPM 4 /* Miscellaneous Parameters and Modes. */ 52119815Smarcel#define WR_TPC 5 /* Transmit Parameters and Control. */ 53119815Smarcel#define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */ 54119815Smarcel#define WR_SCF 7 /* Sync Character or (SDCL) Flag. */ 55119815Smarcel#define WR_EFC 7 /* Extended Feature and FIFO Control. */ 56119815Smarcel#define WR_TB 8 /* Transmit Buffer. */ 57119815Smarcel#define WR_MIC 9 /* Master Interrupt Control (shared). */ 58119815Smarcel#define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */ 59119815Smarcel#define WR_CMC 11 /* Clock Mode Control. */ 60119815Smarcel#define WR_TCL 12 /* BRG Time Constant Low. */ 61119815Smarcel#define WR_TCH 13 /* BRG Time Constant High. */ 62119815Smarcel#define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */ 63119815Smarcel#define WR_IC 15 /* Interrupt Control. */ 64119815Smarcel 65119815Smarcel/* Read registers. */ 66119815Smarcel#define RR_BES 0 /* Buffer and External Status. */ 67119815Smarcel#define RR_SRC 1 /* Special Receive Condition. */ 68119815Smarcel#define RR_IV 2 /* Interrupt Vector. */ 69119815Smarcel#define RR_IP 3 /* Interrupt Pending (ch A only). */ 70119815Smarcel#define RR_MPM 4 /* Miscellaneous Parameters and Modes. */ 71119815Smarcel#define RR_TPC 5 /* Transmit Parameters and Control. */ 72119815Smarcel#define RR_BCL 6 /* Byte Count Low. */ 73119815Smarcel#define RR_BCH 7 /* Byte Count High. */ 74119815Smarcel#define RR_RB 8 /* Receive Buffer. */ 75155967Smarcel#define RR_RPC 9 /* Receive Parameters and Control. */ 76119815Smarcel#define RR_MSB 10 /* Miscellaneous Status Bits. */ 77119815Smarcel#define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */ 78119815Smarcel#define RR_TCL 12 /* BRG Time Constant Low. */ 79119815Smarcel#define RR_TCH 13 /* BRG Time Constant High. */ 80119815Smarcel#define RR_EFC 14 /* Extended Feature and FIFO Control. */ 81119815Smarcel#define RR_IC 15 /* Interrupt Control. */ 82119815Smarcel 83119815Smarcel/* Buffer and External Status (RR0). */ 84119815Smarcel#define BES_BRK 0x80 /* Break (Abort). */ 85119815Smarcel#define BES_TXU 0x40 /* Tx Underrun (EOM). */ 86119815Smarcel#define BES_CTS 0x20 /* CTS. */ 87119815Smarcel#define BES_SYNC 0x10 /* Sync. */ 88119815Smarcel#define BES_DCD 0x08 /* DCD. */ 89119815Smarcel#define BES_TXE 0x04 /* Tx Empty. */ 90119815Smarcel#define BES_ZC 0x02 /* Zero Count. */ 91119815Smarcel#define BES_RXA 0x01 /* Rx Available. */ 92119815Smarcel 93119815Smarcel/* Clock Mode Control (WR11). */ 94119815Smarcel#define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */ 95119815Smarcel#define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */ 96119815Smarcel#define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */ 97119815Smarcel#define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */ 98119815Smarcel#define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */ 99119815Smarcel#define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */ 100119815Smarcel#define CMC_TC_BRG 0x10 /* Tx Clock from BRG */ 101119815Smarcel#define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */ 102119815Smarcel#define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */ 103119815Smarcel#define CMC_TRXC_OUT 0x04 /* -TRxC is output. */ 104119815Smarcel#define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */ 105119815Smarcel#define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */ 106119815Smarcel#define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */ 107119815Smarcel#define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */ 108119815Smarcel 109119815Smarcel/* Command Register (WR0). */ 110119815Smarcel#define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */ 111119815Smarcel#define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */ 112119815Smarcel#define CR_RSTRXCRC 0x40 /* Reset Rx. CRC. */ 113119815Smarcel#define CR_RSTIUS 0x38 /* Reset Int. Under Service. */ 114119815Smarcel#define CR_RSTERR 0x30 /* Error Reset. */ 115119815Smarcel#define CR_RSTTXI 0x28 /* Reset Tx. Int. */ 116119815Smarcel#define CR_ENARXI 0x20 /* Enable Rx. Int. */ 117119815Smarcel#define CR_ABORT 0x18 /* Send Abort. */ 118119815Smarcel#define CR_RSTXSI 0x10 /* Reset Ext/Status Int. */ 119119815Smarcel 120119815Smarcel/* Extended Feature and FIFO Control (WR7 prime). */ 121119815Smarcel#define EFC_ERE 0x40 /* Extended Read Enable. */ 122119815Smarcel#define EFC_FE 0x20 /* Transmit FIFO Empty. */ 123119815Smarcel#define EFC_RQT 0x10 /* Request Timing. */ 124119815Smarcel#define EFC_FHF 0x08 /* Receive FIFO Half Full. */ 125119815Smarcel#define EFC_RTS 0x04 /* Auto RTS Deactivation. */ 126119815Smarcel#define EFC_EOM 0x02 /* Auto EOM Reset. */ 127119815Smarcel#define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */ 128119815Smarcel 129119815Smarcel/* Interrupt Control (WR15). */ 130119815Smarcel#define IC_BRK 0x80 /* Break (Abort) IE. */ 131119815Smarcel#define IC_TXU 0x40 /* Tx Underrun IE. */ 132119815Smarcel#define IC_CTS 0x20 /* CTS IE. */ 133119815Smarcel#define IC_SYNC 0x10 /* Sync IE. */ 134119815Smarcel#define IC_DCD 0x08 /* DCD IE. */ 135119815Smarcel#define IC_FIFO 0x04 /* SDLC FIFO Enable. */ 136119815Smarcel#define IC_ZC 0x02 /* Zero Count IE. */ 137119815Smarcel#define IC_EF 0x01 /* Extended Feature Enable. */ 138119815Smarcel 139119815Smarcel/* Interrupt and Data Transfer Mode (WR1). */ 140119815Smarcel#define IDT_WRE 0x80 /* Wait/DMA Request Enable. */ 141119815Smarcel#define IDT_REQ 0x40 /* DMA Request. */ 142119815Smarcel#define IDT_WRR 0x20 /* Wait/DMA Reuest on Receive. */ 143119815Smarcel#define IDT_RISC 0x18 /* Rx Int. on Special Condition Only. */ 144119815Smarcel#define IDT_RIA 0x10 /* Rx Int. on All Characters. */ 145119815Smarcel#define IDT_RIF 0x08 /* Rx Int. on First Character. */ 146119815Smarcel#define IDT_PSC 0x04 /* Parity is Special Condition. */ 147119815Smarcel#define IDT_TIE 0x02 /* Tx Int. Enable. */ 148119815Smarcel#define IDT_XIE 0x01 /* Ext. Int. Enable. */ 149119815Smarcel 150119815Smarcel/* Interrupt Pending (RR3). */ 151119815Smarcel#define IP_RIA 0x20 /* Rx. Int. ch. A. */ 152119815Smarcel#define IP_TIA 0x10 /* Tx. Int. ch. A. */ 153119815Smarcel#define IP_SIA 0x08 /* Ext/Status Int. ch. A. */ 154119815Smarcel#define IP_RIB 0x04 /* Rx. Int. ch. B. */ 155119815Smarcel#define IP_TIB 0x02 /* Tx. Int. ch. B. */ 156119815Smarcel#define IP_SIB 0x01 /* Ext/Status Int. ch. B. */ 157119815Smarcel 158119815Smarcel/* Interrupt Vector Status Low (RR2). */ 159119815Smarcel#define IV_SCA 0x0e /* Special Condition ch. A. */ 160119815Smarcel#define IV_RAA 0x0c /* Receive Available ch. A. */ 161119815Smarcel#define IV_XSA 0x0a /* External/Status Change ch. A. */ 162119815Smarcel#define IV_TEA 0x08 /* Transmitter Empty ch. A. */ 163119815Smarcel#define IV_SCB 0x06 /* Special Condition ch. B. */ 164119815Smarcel#define IV_RAB 0x04 /* Receive Available ch. B. */ 165119815Smarcel#define IV_XSB 0x02 /* External/Status Change ch. B. */ 166119815Smarcel#define IV_TEB 0x00 /* Transmitter Empty ch. B. */ 167119815Smarcel 168119815Smarcel/* Miscellaneous Control Bits part 1 (WR10). */ 169119815Smarcel#define MCB1_CRC1 0x80 /* CRC presets to 1. */ 170119815Smarcel#define MCB1_FM0 0x60 /* FM0 Encoding. */ 171119815Smarcel#define MCB1_FM1 0x40 /* FM1 Encoding. */ 172119815Smarcel#define MCB1_NRZI 0x20 /* NRZI Encoding. */ 173119815Smarcel#define MCB1_NRZ 0x00 /* NRZ Encoding. */ 174119815Smarcel#define MCB1_AOP 0x10 /* Active On Poll. */ 175119815Smarcel#define MCB1_MI 0x08 /* Mark Idle. */ 176119815Smarcel#define MCB1_AOU 0x04 /* Abort On Underrun. */ 177119815Smarcel#define MCB1_LM 0x02 /* Loop Mode. */ 178119815Smarcel#define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */ 179119815Smarcel 180119815Smarcel/* Miscellaneous Control Bits part 2 (WR14). */ 181119815Smarcel#define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */ 182119815Smarcel#define MCB2_FM 0xc0 /* DPLL - FM mode. */ 183119815Smarcel#define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */ 184119815Smarcel#define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */ 185119815Smarcel#define MCB2_OFF 0x60 /* DPLL - Disable. */ 186119815Smarcel#define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */ 187119815Smarcel#define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */ 188119815Smarcel#define MCB2_LL 0x10 /* Local Loopback. */ 189119815Smarcel#define MCB2_AE 0x08 /* Auto Echo. */ 190119815Smarcel#define MCB2_REQ 0x04 /* Request Function. */ 191119815Smarcel#define MCB2_PCLK 0x02 /* BRG source is PCLK. */ 192119815Smarcel#define MCB2_BRGE 0x01 /* BRG enable. */ 193119815Smarcel 194119815Smarcel/* Master Interrupt Control (WR9). */ 195119815Smarcel#define MIC_FHR 0xc0 /* Force Hardware Reset. */ 196119815Smarcel#define MIC_CRA 0x80 /* Channel Reset A. */ 197119815Smarcel#define MIC_CRB 0x40 /* Channel Reset B. */ 198119815Smarcel#define MIC_SIE 0x20 /* Software INTACK Enable. */ 199119815Smarcel#define MIC_SH 0x10 /* Status High. */ 200119815Smarcel#define MIC_MIE 0x08 /* Master Interrupt Enable. */ 201119815Smarcel#define MIC_DLC 0x04 /* Disable Lower Chain. */ 202119815Smarcel#define MIC_NV 0x02 /* No Vector. */ 203119815Smarcel#define MIC_VIS 0x01 /* Vector Includes Status. */ 204119815Smarcel 205119815Smarcel/* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */ 206119815Smarcel#define MPM_CM64 0xc0 /* X64 Clock Mode. */ 207119815Smarcel#define MPM_CM32 0x80 /* X32 Clock Mode. */ 208119815Smarcel#define MPM_CM16 0x40 /* X16 Clock Mode. */ 209119815Smarcel#define MPM_CM1 0x00 /* X1 Clock Mode. */ 210119815Smarcel#define MPM_EXT 0x30 /* External Sync Mode. */ 211119815Smarcel#define MPM_SDLC 0x20 /* SDLC mode. */ 212119815Smarcel#define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */ 213119815Smarcel#define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */ 214119815Smarcel#define MPM_SB2 0x0c /* Async mode: 2 stopbits. */ 215119815Smarcel#define MPM_SB15 0x08 /* Async mode: 1.5 stopbits. */ 216119815Smarcel#define MPM_SB1 0x04 /* Async mode: 1 stopbit. */ 217119815Smarcel#define MPM_SYNC 0x00 /* Sync Mode Enable. */ 218119815Smarcel#define MPM_EVEN 0x02 /* Async mode: even parity. */ 219119815Smarcel#define MPM_PE 0x01 /* Async mode: parity enable. */ 220119815Smarcel 221119815Smarcel/* Receive Parameters and Control (WR3). */ 222119815Smarcel#define RPC_RB8 0xc0 /* 8 databits. */ 223119815Smarcel#define RPC_RB6 0x80 /* 6 databits. */ 224119815Smarcel#define RPC_RB7 0x40 /* 7 databits. */ 225119815Smarcel#define RPC_RB5 0x00 /* 5 databits. */ 226119815Smarcel#define RPC_AE 0x20 /* Auto Enable. */ 227119815Smarcel#define RPC_EHM 0x10 /* Enter Hunt Mode. */ 228119815Smarcel#define RPC_CRC 0x08 /* CRC Enable. */ 229119815Smarcel#define RPC_ASM 0x04 /* Address Search Mode. */ 230119815Smarcel#define RPC_LI 0x02 /* SYNC Character Load Inhibit */ 231119815Smarcel#define RPC_RXE 0x01 /* Receiver Enable */ 232119815Smarcel 233119815Smarcel/* Special Receive Condition (RR1). */ 234119815Smarcel#define SRC_EOF 0x80 /* End Of Frame. */ 235119815Smarcel#define SRC_FE 0x40 /* Framing Error. */ 236119815Smarcel#define SRC_OVR 0x20 /* Rx. Overrun. */ 237119815Smarcel#define SRC_PE 0x10 /* Parity Error. */ 238119815Smarcel#define SRC_RC0 0x08 /* Residue Code 0. */ 239119815Smarcel#define SRC_RC1 0x04 /* Residue Code 1. */ 240119815Smarcel#define SRC_RC2 0x02 /* Residue Code 2. */ 241119815Smarcel#define SRC_AS 0x01 /* All Sent. */ 242119815Smarcel 243119815Smarcel/* Transmit Parameter and Control (WR5). */ 244119815Smarcel#define TPC_DTR 0x80 /* DTR. */ 245119815Smarcel#define TPC_TB8 0x60 /* 8 databits. */ 246119815Smarcel#define TPC_TB6 0x40 /* 6 databits. */ 247119815Smarcel#define TPC_TB7 0x20 /* 7 databits. */ 248119815Smarcel#define TPC_TB5 0x00 /* 5 or fewer databits. */ 249119815Smarcel#define TPC_BRK 0x10 /* Send break. */ 250119815Smarcel#define TPC_TXE 0x08 /* Transmitter Enable. */ 251119815Smarcel#define TPC_CRC16 0x04 /* CRC16. */ 252119815Smarcel#define TPC_RTS 0x02 /* RTS. */ 253119815Smarcel#define TPC_CRC 0x01 /* CRC Enable. */ 254119815Smarcel 255137955Smarcel#endif /* _DEV_IC_Z8530_H_ */ 256