sab82532.h revision 119815
1119815Smarcel/* $OpenBSD: sab82532reg.h,v 1.2 2002/04/08 17:49:42 jason Exp $ */ 2119815Smarcel 3119815Smarcel/* 4119815Smarcel * Copyright (c) 2001 Jason L. Wright (jason@thought.net) 5119815Smarcel * All rights reserved. 6119815Smarcel * 7119815Smarcel * Redistribution and use in source and binary forms, with or without 8119815Smarcel * modification, are permitted provided that the following conditions 9119815Smarcel * are met: 10119815Smarcel * 1. Redistributions of source code must retain the above copyright 11119815Smarcel * notice, this list of conditions and the following disclaimer. 12119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 13119815Smarcel * notice, this list of conditions and the following disclaimer in the 14119815Smarcel * documentation and/or other materials provided with the distribution. 15119815Smarcel * 3. All advertising materials mentioning features or use of this software 16119815Smarcel * must display the following acknowledgement: 17119815Smarcel * This product includes software developed by Jason L. Wright 18119815Smarcel * 4. The name of the author may not be used to endorse or promote products 19119815Smarcel * derived from this software without specific prior written permission. 20119815Smarcel * 21119815Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22119815Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23119815Smarcel * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24119815Smarcel * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25119815Smarcel * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26119815Smarcel * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27119815Smarcel * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28119815Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29119815Smarcel * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30119815Smarcel * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31119815Smarcel * POSSIBILITY OF SUCH DAMAGE. 32119815Smarcel * 33119815Smarcel * Effort sponsored in part by the Defense Advanced Research Projects 34119815Smarcel * Agency (DARPA) and Air Force Research Laboratory, Air Force 35119815Smarcel * Materiel Command, USAF, under agreement number F30602-01-2-0537. 36119815Smarcel * 37119815Smarcel * $FreeBSD: head/sys/dev/ic/sab82532.h 119815 2003-09-06 23:13:47Z marcel $ 38119815Smarcel */ 39119815Smarcel 40119815Smarcel/* 41119815Smarcel * Register definitions for SAB82532 based on "Enhanced Serial Communication 42119815Smarcel * Controller ESCC2 Version 3.2 User's Manual 07.96" from: 43119815Smarcel * http://www.infineon.com 44119815Smarcel */ 45119815Smarcel 46119815Smarcel#define SAB_NCHAN 2 /* number of channels */ 47119815Smarcel#define SAB_CHANLEN 0x40 /* length of channel register set */ 48119815Smarcel 49119815Smarcel#define SAB_CHAN_A 0x00 /* channel A register offset */ 50119815Smarcel#define SAB_CHAN_B 0x40 /* channel B register offset */ 51119815Smarcel 52119815Smarcel#define SAB_RFIFO 0x00 /* r: rx fifo */ 53119815Smarcel#define SAB_XFIFO 0x00 /* w: tx fifo */ 54119815Smarcel#define SAB_STAR 0x20 /* r: status register */ 55119815Smarcel#define SAB_CMDR 0x20 /* w: command register */ 56119815Smarcel#define SAB_MODE 0x22 /* rw: mode register */ 57119815Smarcel#define SAB_TIMR 0x23 /* rw: timer register */ 58119815Smarcel#define SAB_XON 0x24 /* rw: xon character */ 59119815Smarcel#define SAB_XOFF 0x25 /* rw: xoff character */ 60119815Smarcel#define SAB_TCR 0x26 /* rw: termination character */ 61119815Smarcel#define SAB_DAFO 0x27 /* rw: data format */ 62119815Smarcel#define SAB_RFC 0x28 /* rw: rfifo control register */ 63119815Smarcel#define SAB_RBCL 0x2a /* r: rx byte count low */ 64119815Smarcel#define SAB_TBCL 0x2a /* w: tx byte count low */ 65119815Smarcel#define SAB_RBCH 0x2b /* r: rx byte count high */ 66119815Smarcel#define SAB_XBCH 0x2b /* w: tx byte count high */ 67119815Smarcel#define SAB_CCR0 0x2c /* rw: channel configuration register 0 */ 68119815Smarcel#define SAB_CCR1 0x2d /* rw: channel configuration register 1 */ 69119815Smarcel#define SAB_CCR2 0x2e /* rw: channel configuration register 2 */ 70119815Smarcel#define SAB_CCR3 0x2f /* rw: channel configuration register 3 */ 71119815Smarcel#define SAB_TSAX 0x30 /* w: time-slot assignment register tx */ 72119815Smarcel#define SAB_TSAR 0x31 /* w: time-slot assignment register rx */ 73119815Smarcel#define SAB_XCCR 0x32 /* w: tx channel capacity register */ 74119815Smarcel#define SAB_RCCR 0x33 /* w: receive channel capacity register */ 75119815Smarcel#define SAB_VSTR 0x34 /* r: version status */ 76119815Smarcel#define SAB_BGR 0x34 /* w: baud rate generator */ 77119815Smarcel#define SAB_TIC 0x35 /* w: transmit immediate character */ 78119815Smarcel#define SAB_MXN 0x36 /* w: mask xon character */ 79119815Smarcel#define SAB_MXF 0x37 /* w: mask xoff character */ 80119815Smarcel#define SAB_GIS 0x38 /* r: global interrupt status */ 81119815Smarcel#define SAB_IVA 0x38 /* w: interrupt vector address */ 82119815Smarcel#define SAB_IPC 0x39 /* rw: interrupt port configuration */ 83119815Smarcel#define SAB_ISR0 0x3a /* r: interrupt status 0 */ 84119815Smarcel#define SAB_IMR0 0x3a /* w: interrupt mask 0 */ 85119815Smarcel#define SAB_ISR1 0x3b /* r: interrupt status 1 */ 86119815Smarcel#define SAB_IMR1 0x3b /* w: interrupt mask 1 */ 87119815Smarcel#define SAB_PVR 0x3c /* rw: port value register */ 88119815Smarcel#define SAB_PIS 0x3d /* r: port interrupt status */ 89119815Smarcel#define SAB_PIM 0x3d /* w: port interrupt mask */ 90119815Smarcel#define SAB_PCR 0x3e /* w: port configuration register */ 91119815Smarcel#define SAB_CCR4 0x3f /* rw: channel configuration register 4 */ 92119815Smarcel 93119815Smarcel/* SAB_STAR: status register */ 94119815Smarcel#define SAB_STAR_XDOV 0x80 /* transmit data overflow */ 95119815Smarcel#define SAB_STAR_XFW 0x40 /* transmit fifo write enable */ 96119815Smarcel#define SAB_STAR_RFNE 0x20 /* rfifo not empty */ 97119815Smarcel#define SAB_STAR_FCS 0x10 /* flow control status */ 98119815Smarcel#define SAB_STAR_TEC 0x08 /* tx immediate char is executing */ 99119815Smarcel#define SAB_STAR_CEC 0x04 /* command is executing */ 100119815Smarcel#define SAB_STAR_CTS 0x02 /* cts status: 0:inactive/high,1:active/low */ 101119815Smarcel 102119815Smarcel/* SAB_CMDR: command register */ 103119815Smarcel#define SAB_CMDR_RMC 0x80 /* receive message complete */ 104119815Smarcel#define SAB_CMDR_RRES 0x40 /* receiver reset */ 105119815Smarcel#define SAB_CMDR_RFRD 0x20 /* receive fifo read enable */ 106119815Smarcel#define SAB_CMDR_STI 0x10 /* start timer */ 107119815Smarcel#define SAB_CMDR_XF 0x08 /* transmit frame */ 108119815Smarcel#define SAB_CMDR_XRES 0x01 /* transmit reset */ 109119815Smarcel 110119815Smarcel/* SAB_MODE: mode register */ 111119815Smarcel#define SAB_MODE_FRTS 0x40 /* flow control using rts */ 112119815Smarcel#define SAB_MODE_FCTS 0x20 /* flow control using cts */ 113119815Smarcel#define SAB_MODE_FLON 0x10 /* flow control on */ 114119815Smarcel#define SAB_MODE_RAC 0x08 /* receiver active */ 115119815Smarcel#define SAB_MODE_RTS 0x04 /* request to send */ 116119815Smarcel#define SAB_MODE_TRS 0x02 /* timer resolution */ 117119815Smarcel#define SAB_MODE_TLP 0x01 /* test loop */ 118119815Smarcel 119119815Smarcel/* SAB_TIMR: timer register */ 120119815Smarcel#define SAB_TIMR_CNT 0xe0 /* count mask */ 121119815Smarcel#define SAB_TIMR_VAL 0x1f /* value mask */ 122119815Smarcel 123119815Smarcel/* SAB_DAFO: data format */ 124119815Smarcel#define SAB_DAFO_XBRK 0x40 /* transmit break */ 125119815Smarcel#define SAB_DAFO_STOP 0x20 /* stop bit: 0:1 bit, 1:2 bits */ 126119815Smarcel#define SAB_DAFO_PAR1 0x10 /* parity 1, see below */ 127119815Smarcel#define SAB_DAFO_PAR0 0x08 /* parity 0, see below */ 128119815Smarcel#define SAB_DAFO_PARE 0x04 /* parity enable */ 129119815Smarcel#define SAB_DAFO_CHL1 0x02 /* character length 1, see below */ 130119815Smarcel#define SAB_DAFO_CHL0 0x01 /* character length 0, see below */ 131119815Smarcel 132119815Smarcel#define SAB_DAFO_CHL_CSIZE (SAB_DAFO_CHL1|SAB_DAFO_CHL0) 133119815Smarcel#define SAB_DAFO_CHL_CS5 (SAB_DAFO_CHL1|SAB_DAFO_CHL0) 134119815Smarcel#define SAB_DAFO_CHL_CS6 (SAB_DAFO_CHL1) 135119815Smarcel#define SAB_DAFO_CHL_CS7 (SAB_DAFO_CHL0) 136119815Smarcel#define SAB_DAFO_CHL_CS8 (0) 137119815Smarcel 138119815Smarcel#define SAB_DAFO_PARMASK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE) 139119815Smarcel#define SAB_DAFO_PAR_MARK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE) 140119815Smarcel#define SAB_DAFO_PAR_EVEN (SAB_DAFO_PAR1|SAB_DAFO_PARE) 141119815Smarcel#define SAB_DAFO_PAR_ODD (SAB_DAFO_PAR0|SAB_DAFO_PARE) 142119815Smarcel#define SAB_DAFO_PAR_SPACE (SAB_DAFO_PARE) 143119815Smarcel#define SAB_DAFO_PAR_NONE (0) 144119815Smarcel 145119815Smarcel/* SAB_RFC: rfifo control register */ 146119815Smarcel#define SAB_RFC_DPS 0x40 /* disable parity storage */ 147119815Smarcel#define SAB_RFC_DXS 0x20 /* disable storage of xon/xoff characters */ 148119815Smarcel#define SAB_RFC_RFDF 0x10 /* rfifo data format: 0 data,1 data+stat */ 149119815Smarcel#define SAB_RFC_RFTH1 0x08 /* rfifo threshold level 1, see below */ 150119815Smarcel#define SAB_RFC_RFTH0 0x04 /* rfifo threshold level 0, see below */ 151119815Smarcel#define SAB_RFC_TCDE 0x01 /* termination character detection enable */ 152119815Smarcel 153119815Smarcel#define SAB_RFC_RFTH_MASK (SAB_RFC_RFTH1|SAB_RFC_RFTH0) 154119815Smarcel#define SAB_RFC_RFTH_32CHAR (SAB_RFC_RFTH1|SAB_RFC_RFTH0) 155119815Smarcel#define SAB_RFC_RFTH_16CHAR (SAB_RFC_RFTH1) 156119815Smarcel#define SAB_RFC_RFTH_4CHAR (SAB_RFC_RFTH0) 157119815Smarcel#define SAB_RFC_RFTH_1CHAR (0) 158119815Smarcel 159119815Smarcel/* SAB_RBCH: received byte count high */ 160119815Smarcel#define SAB_RBCH_DMA 0x80 /* read back of XBCH DMA bit */ 161119815Smarcel#define SAB_RBCH_CAS 0x20 /* read back of XBCH CAS bit */ 162119815Smarcel#define SAB_RBCH_CNT 0x0f /* ms 4 bits of rx byte count (not used) */ 163119815Smarcel 164119815Smarcel/* SAB_XBCH: transmit byte count high */ 165119815Smarcel#define SAB_XBCH_DMA 0x80 /* dma mode: 1:dma, 0:interrupt */ 166119815Smarcel#define SAB_XBCH_CAS 0x20 /* carrier detect auto-start */ 167119815Smarcel#define SAB_XBCH_XC 0x10 /* transmit continuously */ 168119815Smarcel#define SAB_XBCH_CNT 0x0f /* ms 4 bits of tx byte count */ 169119815Smarcel 170119815Smarcel/* SAB_CCR0: channel configuration register 0 */ 171119815Smarcel#define SAB_CCR0_PU 0x80 /* 0:power-down, 1:power-up */ 172119815Smarcel#define SAB_CCR0_MCE 0x40 /* master clock enable */ 173119815Smarcel#define SAB_CCR0_SC2 0x10 /* serial port config 2, see below */ 174119815Smarcel#define SAB_CCR0_SC1 0x08 /* serial port config 1, see below */ 175119815Smarcel#define SAB_CCR0_SC0 0x04 /* serial port config 0, see below */ 176119815Smarcel#define SAB_CCR0_SM1 0x02 /* serial mode 1, see below */ 177119815Smarcel#define SAB_CCR0_SM0 0x01 /* serial mode 0, see below */ 178119815Smarcel 179119815Smarcel#define SAB_CCR0_SC_MASK (SAB_CCR0_SC2|SAB_CCR0_SC1|SAB_CCR0_SC0) 180119815Smarcel#define SAB_CCR0_SC_NRZ (0) 181119815Smarcel#define SAB_CCR0_SC_NRZI (SAB_CCR0_SC1) 182119815Smarcel#define SAB_CCR0_SC_FM0 (SAB_CCR0_SC2) 183119815Smarcel#define SAB_CCR0_SC_FM1 (SAB_CCR0_SC2|SAB_CCR0_SC0) 184119815Smarcel#define SAB_CCR0_SC_MANCHESTER (SAB_CCR0_SC2|SAB_CCR0_SC1) 185119815Smarcel 186119815Smarcel#define SAB_CCR0_SM_MASK (SAB_CCR0_SM1|SAB_CCR0_SM0) 187119815Smarcel#define SAB_CCR0_SM_DLC (0) 188119815Smarcel#define SAB_CCR0_SM_DLCLOOP (SAB_CCR0_SM0) 189119815Smarcel#define SAB_CCR0_SM_BISYNC (SAB_CCR0_SM1) 190119815Smarcel#define SAB_CCR0_SM_ASYNC (SAB_CCR0_SM1|SAB_CCR0_SM0) 191119815Smarcel 192119815Smarcel/* SAB_CCR1: channel configuration register 1 */ 193119815Smarcel#define SAB_CCR1_ODS 0x10 /* Output driver select:1:pushpull,0:odrain */ 194119815Smarcel#define SAB_CCR1_BCR 0x08 /* bit clock rate: 1:async, 0:isochronous */ 195119815Smarcel#define SAB_CCR1_CM2 0x04 /* clock mode 2, see below */ 196119815Smarcel#define SAB_CCR1_CM1 0x02 /* clock mode 1, see below */ 197119815Smarcel#define SAB_CCR1_CM0 0x01 /* clock mode 0, see below */ 198119815Smarcel 199119815Smarcel#define SAB_CCR1_CM_MASK (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0) 200119815Smarcel#define SAB_CCR1_CM_7 (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0) 201119815Smarcel 202119815Smarcel/* SAB_CCR2: channel configuration register 2, depends on clock mode above */ 203119815Smarcel/* clock mode 0a, 1, 4, 5 */ 204119815Smarcel#define SAB_CCR2_SOC1 0x80 /* special output 1, below */ 205119815Smarcel#define SAB_CCR2_SOC0 0x40 /* special output 0, below */ 206119815Smarcel#define SAB_CCR2_SOC_MASK (SAB_CCR2_SOC1|SAB_CCR2_SOC0) 207119815Smarcel#define SAB_CCR2_SOC_RTSHIGH (SAB_CCR2_SOC1) 208119815Smarcel#define SAB_CCR2_SOC_RTSNORM (0) 209119815Smarcel#define SAB_CCR2_SOC_RTSRX (SAB_CCR2_SOC1|SAB_CCR2_SOC0) 210119815Smarcel/* clock mode 0b, 2, 3, 6, 7 */ 211119815Smarcel#define SAB_CCR2_BR9 0x80 /* baud rate bit 9 */ 212119815Smarcel#define SAB_CCR2_BR8 0x40 /* baud rate bit 8 */ 213119815Smarcel#define SAB_CCR2_BDF 0x20 /* baud rate division factor: 0:1: 1:BRG */ 214119815Smarcel#define SAB_CCR2_SSEL 0x10 /* clock source select */ 215119815Smarcel/* clock mode 5 */ 216119815Smarcel#define SAB_CCR2_XCS0 0x20 /* tx clock shift, bit 0 */ 217119815Smarcel#define SAB_CCR2_RCS0 0x10 /* rx clock shift, bit 0 */ 218119815Smarcel/* clock mode 0b, 2, 3, 4, 5, 6, 7 */ 219119815Smarcel#define SAB_CCR2_TOE 0x08 /* tx clock output enable */ 220119815Smarcel/* clock mode 0a, 0b, 1, 2, 3, 4, 5, 6, 7 */ 221119815Smarcel#define SAB_CCR2_RWX 0x04 /* read/write exchange (dma mode only) */ 222119815Smarcel#define SAB_CCR2_DIV 0x01 /* data inversion (nrz) */ 223119815Smarcel 224119815Smarcel/* SAB_CCR3: channel configuration register 3 (v2 or greater) */ 225119815Smarcel#define SAB_CCR3_PSD 0x01 /* dpll phase shift disable (nrz/nrzi) */ 226119815Smarcel 227119815Smarcel/* SAB_TSAX: time-slot assignment register transmit (clock mode 5 only) */ 228119815Smarcel#define SAB_TSAX_TSNX 0xfc /* time-slot number transmit */ 229119815Smarcel#define SAB_TSAX_XCS2 0x02 /* transmit clock shift bit 2 */ 230119815Smarcel#define SAB_TSAX_XCS1 0x01 /* transmit clock shift bit 1 */ 231119815Smarcel 232119815Smarcel/* SAB_TSAR: time-slot assignment register receive (clock mode 5 only) */ 233119815Smarcel#define SAB_TSAR_TSNR 0xfc /* time-slot number receive */ 234119815Smarcel#define SAB_TSAR_RCS2 0x02 /* receive clock shift bit 2 */ 235119815Smarcel#define SAB_TSAR_RCS1 0x01 /* receive clock shift bit 1 */ 236119815Smarcel 237119815Smarcel/* SAB_VSTR: version status register */ 238119815Smarcel#define SAB_VSTR_CD 0x80 /* carrier detect status */ 239119815Smarcel#define SAB_VSTR_DPLA 0x40 /* dpll asynchronous */ 240119815Smarcel#define SAB_VSTR_VMASK 0x0f /* chip version mask: */ 241119815Smarcel#define SAB_VSTR_V_1 0x00 /* version 1 */ 242119815Smarcel#define SAB_VSTR_V_2 0x01 /* version 2 */ 243119815Smarcel#define SAB_VSTR_V_32 0x02 /* version 3.2 */ 244119815Smarcel 245119815Smarcel/* SAB_GIS: global interrupt status register */ 246119815Smarcel#define SAB_GIS_PI 0x80 /* universal port interrupt */ 247119815Smarcel#define SAB_GIS_ISA1 0x08 /* interrupt status a1 */ 248119815Smarcel#define SAB_GIS_ISA0 0x04 /* interrupt status a0 */ 249119815Smarcel#define SAB_GIS_ISB1 0x02 /* interrupt status b1 */ 250119815Smarcel#define SAB_GIS_ISB0 0x01 /* interrupt status b0 */ 251119815Smarcel 252119815Smarcel/* SAB_IVA: interrupt vector address */ 253119815Smarcel#define SAB_IVA_MASK 0xf8 /* interrupt vector address mask */ 254119815Smarcel 255119815Smarcel/* SAB_IPC: interrupt port configuration */ 256119815Smarcel#define SAB_IPC_VIS 0x80 /* masked interrupt bits visible */ 257119815Smarcel#define SAB_IPC_SLAMASK 0x18 /* slave address mask */ 258119815Smarcel#define SAB_IPC_CASM 0x04 /* cascading mode */ 259119815Smarcel#define SAB_IPC_ICMASK 0x03 /* port config mask: */ 260119815Smarcel#define SAB_IPC_ICOD 0x00 /* open drain output */ 261119815Smarcel#define SAB_IPC_ICPL 0x01 /* push/pull active low output */ 262119815Smarcel#define SAB_IPC_ICPH 0x03 /* push/pull active high output */ 263119815Smarcel 264119815Smarcel/* SAB_ISR0: interrupt status 0 */ 265119815Smarcel#define SAB_ISR0_TCD 0x80 /* termination character detected */ 266119815Smarcel#define SAB_ISR0_TIME 0x40 /* time-out limit exceeded */ 267119815Smarcel#define SAB_ISR0_PERR 0x20 /* parity error */ 268119815Smarcel#define SAB_ISR0_FERR 0x10 /* framing error */ 269119815Smarcel#define SAB_ISR0_PLLA 0x08 /* dpll asynchronous */ 270119815Smarcel#define SAB_ISR0_CDSC 0x04 /* carrier detect status change */ 271119815Smarcel#define SAB_ISR0_RFO 0x02 /* rfifo overflow */ 272119815Smarcel#define SAB_ISR0_RPF 0x01 /* receive pool full */ 273119815Smarcel 274119815Smarcel/* SAB_ISR1: interrupt status 1 */ 275119815Smarcel#define SAB_ISR1_BRK 0x80 /* break detected */ 276119815Smarcel#define SAB_ISR1_BRKT 0x40 /* break terminated */ 277119815Smarcel#define SAB_ISR1_ALLS 0x20 /* all sent */ 278119815Smarcel#define SAB_ISR1_XOFF 0x10 /* xoff detected */ 279119815Smarcel#define SAB_ISR1_TIN 0x08 /* timer interrupt */ 280119815Smarcel#define SAB_ISR1_CSC 0x04 /* clear to send status change */ 281119815Smarcel#define SAB_ISR1_XON 0x02 /* xon detected */ 282119815Smarcel#define SAB_ISR1_XPR 0x01 /* transmit pool ready */ 283119815Smarcel 284119815Smarcel/* SAB_IMR0: interrupt mask 0 */ 285119815Smarcel#define SAB_IMR0_TCD 0x80 /* termination character detected */ 286119815Smarcel#define SAB_IMR0_TIME 0x40 /* time-out limit exceeded */ 287119815Smarcel#define SAB_IMR0_PERR 0x20 /* parity error */ 288119815Smarcel#define SAB_IMR0_FERR 0x10 /* framing error */ 289119815Smarcel#define SAB_IMR0_PLLA 0x08 /* dpll asynchronous */ 290119815Smarcel#define SAB_IMR0_CDSC 0x04 /* carrier detect status change */ 291119815Smarcel#define SAB_IMR0_RFO 0x02 /* rfifo overflow */ 292119815Smarcel#define SAB_IMR0_RPF 0x01 /* receive pool full */ 293119815Smarcel 294119815Smarcel/* SAB_ISR1: interrupt mask 1 */ 295119815Smarcel#define SAB_IMR1_BRK 0x80 /* break detected */ 296119815Smarcel#define SAB_IMR1_BRKT 0x40 /* break terminated */ 297119815Smarcel#define SAB_IMR1_ALLS 0x20 /* all sent */ 298119815Smarcel#define SAB_IMR1_XDU 0x10 /* xoff detected */ 299119815Smarcel#define SAB_IMR1_TIN 0x08 /* timer interrupt */ 300119815Smarcel#define SAB_IMR1_CSC 0x04 /* clear to send status change */ 301119815Smarcel#define SAB_IMR1_XMR 0x02 /* xon detected */ 302119815Smarcel#define SAB_IMR1_XPR 0x01 /* transmit pool ready */ 303119815Smarcel 304119815Smarcel/* SAB_PVR: port value register */ 305119815Smarcel#define SAB_PVR_DSR_A 0x01 /* port A DSR */ 306119815Smarcel#define SAB_PVR_DTR_A 0x02 /* port A DTR */ 307119815Smarcel#define SAB_PVR_DTR_B 0x04 /* port B DTR */ 308119815Smarcel#define SAB_PVR_DSR_B 0x08 /* port B DSR */ 309119815Smarcel#define SAB_PVR_MAGIC 0x10 /* dunno... */ 310119815Smarcel 311119815Smarcel/* SAB_CCR4: channel configuration register 4 */ 312119815Smarcel#define SAB_CCR4_MCK4 0x80 /* master clock divide by 4 */ 313119815Smarcel#define SAB_CCR4_EBRG 0x40 /* enhanced baud rate generator mode */ 314119815Smarcel#define SAB_CCR4_TST1 0x20 /* test pin */ 315119815Smarcel#define SAB_CCR4_ICD 0x10 /* invert polarity of carrier detect */ 316119815Smarcel 317119815Smarcel/* Receive status byte */ 318119815Smarcel#define SAB_RSTAT_PE 0x80 /* parity error */ 319119815Smarcel#define SAB_RSTAT_FE 0x40 /* framing error */ 320119815Smarcel#define SAB_RSTAT_PAR 0x01 /* parity bit */ 321