ns16550.h revision 194600
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: head/sys/dev/ic/ns16550.h 194600 2009-06-21 19:17:22Z sam $ 31 */ 32 33/* 34 * NS8250... UART registers. 35 */ 36 37/* 8250 registers #[0-6]. */ 38 39#define com_data 0 /* data register (R/W) */ 40#define REG_DATA com_data 41 42#define com_ier 1 /* interrupt enable register (W) */ 43#define REG_IER com_ier 44#define IER_ERXRDY 0x1 45#define IER_ETXRDY 0x2 46#define IER_ERLS 0x4 47#define IER_EMSC 0x8 48 49#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" 50 51#define com_iir 2 /* interrupt identification register (R) */ 52#define REG_IIR com_iir 53#define IIR_IMASK 0xf 54#define IIR_RXTOUT 0xc 55#define IIR_RLS 0x6 56#define IIR_RXRDY 0x4 57#define IIR_TXRDY 0x2 58#define IIR_NOPEND 0x1 59#define IIR_MLSC 0x0 60#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 61 62#define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" 63 64#define com_lcr 3 /* line control register (R/W) */ 65#define com_cfcr com_lcr /* character format control register (R/W) */ 66#define REG_LCR com_lcr 67#define LCR_DLAB 0x80 68#define CFCR_DLAB LCR_DLAB 69#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 70#define CFCR_EFR_ENABLE LCR_EFR_ENABLE 71#define LCR_SBREAK 0x40 72#define CFCR_SBREAK LCR_SBREAK 73#define LCR_PZERO 0x30 74#define CFCR_PZERO LCR_PZERO 75#define LCR_PONE 0x20 76#define CFCR_PONE LCR_PONE 77#define LCR_PEVEN 0x10 78#define CFCR_PEVEN LCR_PEVEN 79#define LCR_PODD 0x00 80#define CFCR_PODD LCR_PODD 81#define LCR_PENAB 0x08 82#define CFCR_PENAB LCR_PENAB 83#define LCR_STOPB 0x04 84#define CFCR_STOPB LCR_STOPB 85#define LCR_8BITS 0x03 86#define CFCR_8BITS LCR_8BITS 87#define LCR_7BITS 0x02 88#define CFCR_7BITS LCR_7BITS 89#define LCR_6BITS 0x01 90#define CFCR_6BITS LCR_6BITS 91#define LCR_5BITS 0x00 92#define CFCR_5BITS LCR_5BITS 93 94#define com_mcr 4 /* modem control register (R/W) */ 95#define REG_MCR com_mcr 96#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 97#define MCR_LOOPBACK 0x10 98#define MCR_IE 0x08 99#define MCR_IENABLE MCR_IE 100#define MCR_DRS 0x04 101#define MCR_RTS 0x02 102#define MCR_DTR 0x01 103 104#define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE" 105 106#define com_lsr 5 /* line status register (R/W) */ 107#define REG_LSR com_lsr 108#define LSR_RCV_FIFO 0x80 109#define LSR_TEMT 0x40 110#define LSR_TSRE LSR_TEMT 111#define LSR_THRE 0x20 112#define LSR_TXRDY LSR_THRE 113#define LSR_BI 0x10 114#define LSR_FE 0x08 115#define LSR_PE 0x04 116#define LSR_OE 0x02 117#define LSR_RXRDY 0x01 118#define LSR_RCV_MASK 0x1f 119 120#define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO" 121 122#define com_msr 6 /* modem status register (R/W) */ 123#define REG_MSR com_msr 124#define MSR_DCD 0x80 125#define MSR_RI 0x40 126#define MSR_DSR 0x20 127#define MSR_CTS 0x10 128#define MSR_DDCD 0x08 129#define MSR_TERI 0x04 130#define MSR_DDSR 0x02 131#define MSR_DCTS 0x01 132 133#define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD" 134 135/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 136#define com_dll 0 /* divisor latch low (R/W) */ 137#define com_dlbl com_dll 138#define com_dlm 1 /* divisor latch high (R/W) */ 139#define com_dlbh com_dlm 140#define REG_DLL com_dll 141#define REG_DLH com_dlm 142 143/* 16450 register #7. Not multiplexed. */ 144#define com_scr 7 /* scratch register (R/W) */ 145 146/* 16550 register #2. Not multiplexed. */ 147#define com_fcr 2 /* FIFO control register (W) */ 148#define com_fifo com_fcr 149#define REG_FCR com_fcr 150#define FCR_ENABLE 0x01 151#define FIFO_ENABLE FCR_ENABLE 152#define FCR_RCV_RST 0x02 153#define FIFO_RCV_RST FCR_RCV_RST 154#define FCR_XMT_RST 0x04 155#define FIFO_XMT_RST FCR_XMT_RST 156#define FCR_DMA 0x08 157#define FIFO_DMA_MODE FCR_DMA 158#define FCR_RX_LOW 0x00 159#define FIFO_RX_LOW FCR_RX_LOW 160#define FCR_RX_MEDL 0x40 161#define FIFO_RX_MEDL FCR_RX_MEDL 162#define FCR_RX_MEDH 0x80 163#define FIFO_RX_MEDH FCR_RX_MEDH 164#define FCR_RX_HIGH 0xc0 165#define FIFO_RX_HIGH FCR_RX_HIGH 166 167#define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA" 168 169/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 170 171#define com_efr 2 /* enhanced features register (R/W) */ 172#define REG_EFR com_efr 173#define EFR_CTS 0x80 174#define EFR_AUTOCTS EFR_CTS 175#define EFR_RTS 0x40 176#define EFR_AUTORTS EFR_RTS 177#define EFR_EFE 0x10 /* enhanced functions enable */ 178 179#define com_xon1 4 /* XON 1 character (R/W) */ 180#define com_xon2 5 /* XON 2 character (R/W) */ 181#define com_xoff1 6 /* XOFF 1 character (R/W) */ 182#define com_xoff2 7 /* XOFF 2 character (R/W) */ 183 184/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 185#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 186 187/* 16950 register #3. R/W access enabled by ACR[7]. */ 188#define com_rfl 3 /* receiver fifo level (R) */ 189 190/* 191 * 16950 register #4. Access enabled by ACR[7]. Also requires 192 * !LCR_EFR_ENABLE. 193 */ 194#define com_tfl 4 /* transmitter fifo level (R) */ 195 196/* 197 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 198 * requires ACR[6]. 199 */ 200#define com_icr 5 /* index control register (R/W) */ 201 202/* 203 * 16950 register #7. It is the same as com_scr except it has a different 204 * abbreviation in the manufacturer's data sheet and it also serves as an 205 * index into the Indexed Control register set. 206 */ 207#define com_spr com_scr /* scratch pad (and index) register (R/W) */ 208#define REG_SPR com_scr 209 210/* 211 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 212 * data in ICR (if ICR is accessible). 213 */ 214 215#define com_acr 0 /* additional control register (R/W) */ 216#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 217#define ACR_ICRE 0x40 /* ICR enable */ 218#define ACR_TLE 0x20 /* TTL/RTL enable */ 219 220#define com_cpr 1 /* clock prescaler register (R/W) */ 221#define com_tcr 2 /* times clock register (R/W) */ 222#define com_ttl 4 /* transmitter trigger level (R/W) */ 223#define com_rtl 5 /* receiver trigger level (R/W) */ 224/* ... */ 225 226/* Hardware extension mode register for RSB-2000/3000. */ 227#define com_emr com_msr 228#define EMR_EXBUFF 0x04 229#define EMR_CTSFLW 0x08 230#define EMR_DSRFLW 0x10 231#define EMR_RTSFLW 0x20 232#define EMR_DTRFLW 0x40 233#define EMR_EFMODE 0x80 234