ns16550.h revision 266046
14Srgrimes/*- 24Srgrimes * Copyright (c) 1991 The Regents of the University of California. 34Srgrimes * All rights reserved. 44Srgrimes * 54Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 114Srgrimes * notice, this list of conditions and the following disclaimer in the 124Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 4. Neither the name of the University nor the names of its contributors 144Srgrimes * may be used to endorse or promote products derived from this software 154Srgrimes * without specific prior written permission. 164Srgrimes * 174Srgrimes * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 184Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 194Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 204Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 214Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 224Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 234Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 244Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 254Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 264Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 274Srgrimes * SUCH DAMAGE. 284Srgrimes * 29619Srgrimes * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 3050477Speter * $FreeBSD: stable/10/sys/dev/ic/ns16550.h 266046 2014-05-14 16:32:27Z ian $ 314Srgrimes */ 324Srgrimes 334Srgrimes/* 34120119Sbde * NS8250... UART registers. 354Srgrimes */ 36120119Sbde 37120119Sbde/* 8250 registers #[0-6]. */ 38120119Sbde 394Srgrimes#define com_data 0 /* data register (R/W) */ 40137948Smarcel#define REG_DATA com_data 41120116Sbde 42120119Sbde#define com_ier 1 /* interrupt enable register (W) */ 43137948Smarcel#define REG_IER com_ier 44120116Sbde#define IER_ERXRDY 0x1 45120116Sbde#define IER_ETXRDY 0x2 46120116Sbde#define IER_ERLS 0x4 47120116Sbde#define IER_EMSC 0x8 48120116Sbde 49194600Ssam#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" 50194600Ssam 51120119Sbde#define com_iir 2 /* interrupt identification register (R) */ 52137948Smarcel#define REG_IIR com_iir 53120116Sbde#define IIR_IMASK 0xf 54120116Sbde#define IIR_RXTOUT 0xc 55202062Simp#define IIR_BUSY 0x7 56120116Sbde#define IIR_RLS 0x6 57120116Sbde#define IIR_RXRDY 0x4 58120116Sbde#define IIR_TXRDY 0x2 59120116Sbde#define IIR_NOPEND 0x1 60120116Sbde#define IIR_MLSC 0x0 61120116Sbde#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 62120116Sbde 63194600Ssam#define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" 64194600Ssam 65120122Sbde#define com_lcr 3 /* line control register (R/W) */ 66120122Sbde#define com_cfcr com_lcr /* character format control register (R/W) */ 67137948Smarcel#define REG_LCR com_lcr 68120122Sbde#define LCR_DLAB 0x80 69120122Sbde#define CFCR_DLAB LCR_DLAB 70120122Sbde#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 71120122Sbde#define CFCR_EFR_ENABLE LCR_EFR_ENABLE 72137948Smarcel#define LCR_SBREAK 0x40 73137948Smarcel#define CFCR_SBREAK LCR_SBREAK 74137948Smarcel#define LCR_PZERO 0x30 75137948Smarcel#define CFCR_PZERO LCR_PZERO 76137948Smarcel#define LCR_PONE 0x20 77137948Smarcel#define CFCR_PONE LCR_PONE 78137948Smarcel#define LCR_PEVEN 0x10 79137948Smarcel#define CFCR_PEVEN LCR_PEVEN 80137948Smarcel#define LCR_PODD 0x00 81137948Smarcel#define CFCR_PODD LCR_PODD 82137948Smarcel#define LCR_PENAB 0x08 83137948Smarcel#define CFCR_PENAB LCR_PENAB 84137948Smarcel#define LCR_STOPB 0x04 85137948Smarcel#define CFCR_STOPB LCR_STOPB 86137948Smarcel#define LCR_8BITS 0x03 87137948Smarcel#define CFCR_8BITS LCR_8BITS 88137948Smarcel#define LCR_7BITS 0x02 89137948Smarcel#define CFCR_7BITS LCR_7BITS 90137948Smarcel#define LCR_6BITS 0x01 91137948Smarcel#define CFCR_6BITS LCR_6BITS 92137948Smarcel#define LCR_5BITS 0x00 93137948Smarcel#define CFCR_5BITS LCR_5BITS 94120116Sbde 95120119Sbde#define com_mcr 4 /* modem control register (R/W) */ 96137948Smarcel#define REG_MCR com_mcr 97120119Sbde#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 98120116Sbde#define MCR_LOOPBACK 0x10 99137948Smarcel#define MCR_IE 0x08 100137948Smarcel#define MCR_IENABLE MCR_IE 101120116Sbde#define MCR_DRS 0x04 102120116Sbde#define MCR_RTS 0x02 103120116Sbde#define MCR_DTR 0x01 104120116Sbde 105194600Ssam#define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE" 106194600Ssam 107120119Sbde#define com_lsr 5 /* line status register (R/W) */ 108137948Smarcel#define REG_LSR com_lsr 109120116Sbde#define LSR_RCV_FIFO 0x80 110137948Smarcel#define LSR_TEMT 0x40 111137948Smarcel#define LSR_TSRE LSR_TEMT 112137948Smarcel#define LSR_THRE 0x20 113137948Smarcel#define LSR_TXRDY LSR_THRE 114120116Sbde#define LSR_BI 0x10 115120116Sbde#define LSR_FE 0x08 116120116Sbde#define LSR_PE 0x04 117120116Sbde#define LSR_OE 0x02 118120116Sbde#define LSR_RXRDY 0x01 119120116Sbde#define LSR_RCV_MASK 0x1f 120120116Sbde 121194600Ssam#define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO" 122194600Ssam 123120119Sbde#define com_msr 6 /* modem status register (R/W) */ 124137948Smarcel#define REG_MSR com_msr 125120116Sbde#define MSR_DCD 0x80 126120116Sbde#define MSR_RI 0x40 127120116Sbde#define MSR_DSR 0x20 128120116Sbde#define MSR_CTS 0x10 129120116Sbde#define MSR_DDCD 0x08 130120116Sbde#define MSR_TERI 0x04 131120116Sbde#define MSR_DDSR 0x02 132120116Sbde#define MSR_DCTS 0x01 133120116Sbde 134194600Ssam#define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD" 135194600Ssam 136120119Sbde/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 137120122Sbde#define com_dll 0 /* divisor latch low (R/W) */ 138120122Sbde#define com_dlbl com_dll 139120122Sbde#define com_dlm 1 /* divisor latch high (R/W) */ 140120122Sbde#define com_dlbh com_dlm 141158844Sbenno#define REG_DLL com_dll 142158844Sbenno#define REG_DLH com_dlm 143120116Sbde 144120119Sbde/* 16450 register #7. Not multiplexed. */ 145120119Sbde#define com_scr 7 /* scratch register (R/W) */ 146120119Sbde 147120119Sbde/* 16550 register #2. Not multiplexed. */ 148120122Sbde#define com_fcr 2 /* FIFO control register (W) */ 149120122Sbde#define com_fifo com_fcr 150137948Smarcel#define REG_FCR com_fcr 151137948Smarcel#define FCR_ENABLE 0x01 152137948Smarcel#define FIFO_ENABLE FCR_ENABLE 153137948Smarcel#define FCR_RCV_RST 0x02 154137948Smarcel#define FIFO_RCV_RST FCR_RCV_RST 155137948Smarcel#define FCR_XMT_RST 0x04 156137948Smarcel#define FIFO_XMT_RST FCR_XMT_RST 157137948Smarcel#define FCR_DMA 0x08 158137948Smarcel#define FIFO_DMA_MODE FCR_DMA 159137948Smarcel#define FCR_RX_LOW 0x00 160137948Smarcel#define FIFO_RX_LOW FCR_RX_LOW 161137948Smarcel#define FCR_RX_MEDL 0x40 162137948Smarcel#define FIFO_RX_MEDL FCR_RX_MEDL 163137948Smarcel#define FCR_RX_MEDH 0x80 164137948Smarcel#define FIFO_RX_MEDH FCR_RX_MEDH 165137948Smarcel#define FCR_RX_HIGH 0xc0 166137948Smarcel#define FIFO_RX_HIGH FCR_RX_HIGH 167120119Sbde 168194600Ssam#define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA" 169194600Ssam 170120119Sbde/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 171120119Sbde 172120122Sbde#define com_efr 2 /* enhanced features register (R/W) */ 173137948Smarcel#define REG_EFR com_efr 174137948Smarcel#define EFR_CTS 0x80 175137948Smarcel#define EFR_AUTOCTS EFR_CTS 176137948Smarcel#define EFR_RTS 0x40 177137948Smarcel#define EFR_AUTORTS EFR_RTS 178120119Sbde#define EFR_EFE 0x10 /* enhanced functions enable */ 179120119Sbde 180120123Sbde#define com_xon1 4 /* XON 1 character (R/W) */ 181120123Sbde#define com_xon2 5 /* XON 2 character (R/W) */ 182120123Sbde#define com_xoff1 6 /* XOFF 1 character (R/W) */ 183120123Sbde#define com_xoff2 7 /* XOFF 2 character (R/W) */ 184120123Sbde 185247519Sganbold#define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */ 186202062Simp#define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ 187202062Simp#define REG_USR com_usr 188266046Sian#define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */ 189202062Simp#define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ 190202062Simp 191120124Sbde/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 192120124Sbde#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 193120124Sbde 194120124Sbde/* 16950 register #3. R/W access enabled by ACR[7]. */ 195120124Sbde#define com_rfl 3 /* receiver fifo level (R) */ 196120124Sbde 197120124Sbde/* 198120124Sbde * 16950 register #4. Access enabled by ACR[7]. Also requires 199120124Sbde * !LCR_EFR_ENABLE. 200120124Sbde */ 201120124Sbde#define com_tfl 4 /* transmitter fifo level (R) */ 202120124Sbde 203120124Sbde/* 204120124Sbde * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 205120124Sbde * requires ACR[6]. 206120124Sbde */ 207120124Sbde#define com_icr 5 /* index control register (R/W) */ 208120124Sbde 209120124Sbde/* 210120124Sbde * 16950 register #7. It is the same as com_scr except it has a different 211120124Sbde * abbreviation in the manufacturer's data sheet and it also serves as an 212120124Sbde * index into the Indexed Control register set. 213120124Sbde */ 214120124Sbde#define com_spr com_scr /* scratch pad (and index) register (R/W) */ 215137948Smarcel#define REG_SPR com_scr 216120124Sbde 217120124Sbde/* 218120124Sbde * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 219120124Sbde * data in ICR (if ICR is accessible). 220120124Sbde */ 221120124Sbde 222120124Sbde#define com_acr 0 /* additional control register (R/W) */ 223120124Sbde#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 224120124Sbde#define ACR_ICRE 0x40 /* ICR enable */ 225120124Sbde#define ACR_TLE 0x20 /* TTL/RTL enable */ 226120124Sbde 227120124Sbde#define com_cpr 1 /* clock prescaler register (R/W) */ 228120124Sbde#define com_tcr 2 /* times clock register (R/W) */ 229120124Sbde#define com_ttl 4 /* transmitter trigger level (R/W) */ 230120124Sbde#define com_rtl 5 /* receiver trigger level (R/W) */ 231120124Sbde/* ... */ 232120124Sbde 233120116Sbde/* Hardware extension mode register for RSB-2000/3000. */ 234120116Sbde#define com_emr com_msr 235120116Sbde#define EMR_EXBUFF 0x04 236120116Sbde#define EMR_CTSFLW 0x08 237120116Sbde#define EMR_DSRFLW 0x10 238120116Sbde#define EMR_RTSFLW 0x20 239120116Sbde#define EMR_DTRFLW 0x40 240120116Sbde#define EMR_EFMODE 0x80 241