ns16550.h revision 137948
14Srgrimes/*- 24Srgrimes * Copyright (c) 1991 The Regents of the University of California. 34Srgrimes * All rights reserved. 44Srgrimes * 54Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 114Srgrimes * notice, this list of conditions and the following disclaimer in the 124Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 4. Neither the name of the University nor the names of its contributors 144Srgrimes * may be used to endorse or promote products derived from this software 154Srgrimes * without specific prior written permission. 164Srgrimes * 174Srgrimes * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 184Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 194Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 204Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 214Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 224Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 234Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 244Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 254Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 264Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 274Srgrimes * SUCH DAMAGE. 284Srgrimes * 29619Srgrimes * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 3050477Speter * $FreeBSD: head/sys/dev/ic/ns16550.h 137948 2004-11-20 23:19:42Z marcel $ 314Srgrimes */ 324Srgrimes 334Srgrimes/* 34120119Sbde * NS8250... UART registers. 354Srgrimes */ 36120119Sbde 37120119Sbde/* 8250 registers #[0-6]. */ 38120119Sbde 394Srgrimes#define com_data 0 /* data register (R/W) */ 40137948Smarcel#define REG_DATA com_data 41120116Sbde 42120119Sbde#define com_ier 1 /* interrupt enable register (W) */ 43137948Smarcel#define REG_IER com_ier 44120116Sbde#define IER_ERXRDY 0x1 45120116Sbde#define IER_ETXRDY 0x2 46120116Sbde#define IER_ERLS 0x4 47120116Sbde#define IER_EMSC 0x8 48120116Sbde 49120119Sbde#define com_iir 2 /* interrupt identification register (R) */ 50137948Smarcel#define REG_IIR com_iir 51120116Sbde#define IIR_IMASK 0xf 52120116Sbde#define IIR_RXTOUT 0xc 53120116Sbde#define IIR_RLS 0x6 54120116Sbde#define IIR_RXRDY 0x4 55120116Sbde#define IIR_TXRDY 0x2 56120116Sbde#define IIR_NOPEND 0x1 57120116Sbde#define IIR_MLSC 0x0 58120116Sbde#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 59120116Sbde 60120122Sbde#define com_lcr 3 /* line control register (R/W) */ 61120122Sbde#define com_cfcr com_lcr /* character format control register (R/W) */ 62137948Smarcel#define REG_LCR com_lcr 63120122Sbde#define LCR_DLAB 0x80 64120122Sbde#define CFCR_DLAB LCR_DLAB 65120122Sbde#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 66120122Sbde#define CFCR_EFR_ENABLE LCR_EFR_ENABLE 67137948Smarcel#define LCR_SBREAK 0x40 68137948Smarcel#define CFCR_SBREAK LCR_SBREAK 69137948Smarcel#define LCR_PZERO 0x30 70137948Smarcel#define CFCR_PZERO LCR_PZERO 71137948Smarcel#define LCR_PONE 0x20 72137948Smarcel#define CFCR_PONE LCR_PONE 73137948Smarcel#define LCR_PEVEN 0x10 74137948Smarcel#define CFCR_PEVEN LCR_PEVEN 75137948Smarcel#define LCR_PODD 0x00 76137948Smarcel#define CFCR_PODD LCR_PODD 77137948Smarcel#define LCR_PENAB 0x08 78137948Smarcel#define CFCR_PENAB LCR_PENAB 79137948Smarcel#define LCR_STOPB 0x04 80137948Smarcel#define CFCR_STOPB LCR_STOPB 81137948Smarcel#define LCR_8BITS 0x03 82137948Smarcel#define CFCR_8BITS LCR_8BITS 83137948Smarcel#define LCR_7BITS 0x02 84137948Smarcel#define CFCR_7BITS LCR_7BITS 85137948Smarcel#define LCR_6BITS 0x01 86137948Smarcel#define CFCR_6BITS LCR_6BITS 87137948Smarcel#define LCR_5BITS 0x00 88137948Smarcel#define CFCR_5BITS LCR_5BITS 89120116Sbde 90120119Sbde#define com_mcr 4 /* modem control register (R/W) */ 91137948Smarcel#define REG_MCR com_mcr 92120119Sbde#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 93120116Sbde#define MCR_LOOPBACK 0x10 94137948Smarcel#define MCR_IE 0x08 95137948Smarcel#define MCR_IENABLE MCR_IE 96120116Sbde#define MCR_DRS 0x04 97120116Sbde#define MCR_RTS 0x02 98120116Sbde#define MCR_DTR 0x01 99120116Sbde 100120119Sbde#define com_lsr 5 /* line status register (R/W) */ 101137948Smarcel#define REG_LSR com_lsr 102120116Sbde#define LSR_RCV_FIFO 0x80 103137948Smarcel#define LSR_TEMT 0x40 104137948Smarcel#define LSR_TSRE LSR_TEMT 105137948Smarcel#define LSR_THRE 0x20 106137948Smarcel#define LSR_TXRDY LSR_THRE 107120116Sbde#define LSR_BI 0x10 108120116Sbde#define LSR_FE 0x08 109120116Sbde#define LSR_PE 0x04 110120116Sbde#define LSR_OE 0x02 111120116Sbde#define LSR_RXRDY 0x01 112120116Sbde#define LSR_RCV_MASK 0x1f 113120116Sbde 114120119Sbde#define com_msr 6 /* modem status register (R/W) */ 115137948Smarcel#define REG_MSR com_msr 116120116Sbde#define MSR_DCD 0x80 117120116Sbde#define MSR_RI 0x40 118120116Sbde#define MSR_DSR 0x20 119120116Sbde#define MSR_CTS 0x10 120120116Sbde#define MSR_DDCD 0x08 121120116Sbde#define MSR_TERI 0x04 122120116Sbde#define MSR_DDSR 0x02 123120116Sbde#define MSR_DCTS 0x01 124120116Sbde 125120119Sbde/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 126120122Sbde#define com_dll 0 /* divisor latch low (R/W) */ 127120122Sbde#define com_dlbl com_dll 128120122Sbde#define com_dlm 1 /* divisor latch high (R/W) */ 129120122Sbde#define com_dlbh com_dlm 130137948Smarcel#define REG_DL com_dll 131120116Sbde 132120119Sbde/* 16450 register #7. Not multiplexed. */ 133120119Sbde#define com_scr 7 /* scratch register (R/W) */ 134120119Sbde 135120119Sbde/* 16550 register #2. Not multiplexed. */ 136120122Sbde#define com_fcr 2 /* FIFO control register (W) */ 137120122Sbde#define com_fifo com_fcr 138137948Smarcel#define REG_FCR com_fcr 139137948Smarcel#define FCR_ENABLE 0x01 140137948Smarcel#define FIFO_ENABLE FCR_ENABLE 141137948Smarcel#define FCR_RCV_RST 0x02 142137948Smarcel#define FIFO_RCV_RST FCR_RCV_RST 143137948Smarcel#define FCR_XMT_RST 0x04 144137948Smarcel#define FIFO_XMT_RST FCR_XMT_RST 145137948Smarcel#define FCR_DMA 0x08 146137948Smarcel#define FIFO_DMA_MODE FCR_DMA 147137948Smarcel#define FCR_RX_LOW 0x00 148137948Smarcel#define FIFO_RX_LOW FCR_RX_LOW 149137948Smarcel#define FCR_RX_MEDL 0x40 150137948Smarcel#define FIFO_RX_MEDL FCR_RX_MEDL 151137948Smarcel#define FCR_RX_MEDH 0x80 152137948Smarcel#define FIFO_RX_MEDH FCR_RX_MEDH 153137948Smarcel#define FCR_RX_HIGH 0xc0 154137948Smarcel#define FIFO_RX_HIGH FCR_RX_HIGH 155120119Sbde 156120119Sbde/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 157120119Sbde 158120122Sbde#define com_efr 2 /* enhanced features register (R/W) */ 159137948Smarcel#define REG_EFR com_efr 160137948Smarcel#define EFR_CTS 0x80 161137948Smarcel#define EFR_AUTOCTS EFR_CTS 162137948Smarcel#define EFR_RTS 0x40 163137948Smarcel#define EFR_AUTORTS EFR_RTS 164120119Sbde#define EFR_EFE 0x10 /* enhanced functions enable */ 165120119Sbde 166120123Sbde#define com_xon1 4 /* XON 1 character (R/W) */ 167120123Sbde#define com_xon2 5 /* XON 2 character (R/W) */ 168120123Sbde#define com_xoff1 6 /* XOFF 1 character (R/W) */ 169120123Sbde#define com_xoff2 7 /* XOFF 2 character (R/W) */ 170120123Sbde 171120124Sbde/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 172120124Sbde#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 173120124Sbde 174120124Sbde/* 16950 register #3. R/W access enabled by ACR[7]. */ 175120124Sbde#define com_rfl 3 /* receiver fifo level (R) */ 176120124Sbde 177120124Sbde/* 178120124Sbde * 16950 register #4. Access enabled by ACR[7]. Also requires 179120124Sbde * !LCR_EFR_ENABLE. 180120124Sbde */ 181120124Sbde#define com_tfl 4 /* transmitter fifo level (R) */ 182120124Sbde 183120124Sbde/* 184120124Sbde * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 185120124Sbde * requires ACR[6]. 186120124Sbde */ 187120124Sbde#define com_icr 5 /* index control register (R/W) */ 188120124Sbde 189120124Sbde/* 190120124Sbde * 16950 register #7. It is the same as com_scr except it has a different 191120124Sbde * abbreviation in the manufacturer's data sheet and it also serves as an 192120124Sbde * index into the Indexed Control register set. 193120124Sbde */ 194120124Sbde#define com_spr com_scr /* scratch pad (and index) register (R/W) */ 195137948Smarcel#define REG_SPR com_scr 196120124Sbde 197120124Sbde/* 198120124Sbde * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 199120124Sbde * data in ICR (if ICR is accessible). 200120124Sbde */ 201120124Sbde 202120124Sbde#define com_acr 0 /* additional control register (R/W) */ 203120124Sbde#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 204120124Sbde#define ACR_ICRE 0x40 /* ICR enable */ 205120124Sbde#define ACR_TLE 0x20 /* TTL/RTL enable */ 206120124Sbde 207120124Sbde#define com_cpr 1 /* clock prescaler register (R/W) */ 208120124Sbde#define com_tcr 2 /* times clock register (R/W) */ 209120124Sbde#define com_ttl 4 /* transmitter trigger level (R/W) */ 210120124Sbde#define com_rtl 5 /* receiver trigger level (R/W) */ 211120124Sbde/* ... */ 212120124Sbde 213120116Sbde#ifdef PC98 214120116Sbde/* Hardware extension mode register for RSB-2000/3000. */ 215120116Sbde#define com_emr com_msr 216120116Sbde#define EMR_EXBUFF 0x04 217120116Sbde#define EMR_CTSFLW 0x08 218120116Sbde#define EMR_DSRFLW 0x10 219120116Sbde#define EMR_RTSFLW 0x20 220120116Sbde#define EMR_DTRFLW 0x40 221120116Sbde#define EMR_EFMODE 0x80 222120116Sbde#endif 223