ns16550.h revision 120124
14Srgrimes/*- 24Srgrimes * Copyright (c) 1991 The Regents of the University of California. 34Srgrimes * All rights reserved. 44Srgrimes * 54Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 114Srgrimes * notice, this list of conditions and the following disclaimer in the 124Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 3. All advertising materials mentioning features or use of this software 144Srgrimes * must display the following acknowledgement: 154Srgrimes * This product includes software developed by the University of 164Srgrimes * California, Berkeley and its contributors. 174Srgrimes * 4. Neither the name of the University nor the names of its contributors 184Srgrimes * may be used to endorse or promote products derived from this software 194Srgrimes * without specific prior written permission. 204Srgrimes * 214Srgrimes * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 224Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 234Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 244Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 254Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 264Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 274Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 284Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 294Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 304Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 314Srgrimes * SUCH DAMAGE. 324Srgrimes * 33619Srgrimes * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 3450477Speter * $FreeBSD: head/sys/dev/ic/ns16550.h 120124 2003-09-16 14:21:17Z bde $ 354Srgrimes */ 364Srgrimes 374Srgrimes/* 38120119Sbde * NS8250... UART registers. 394Srgrimes */ 40120119Sbde 41120119Sbde/* 8250 registers #[0-6]. */ 42120119Sbde 434Srgrimes#define com_data 0 /* data register (R/W) */ 44120122Sbde#define com_thr com_data /* transmitter holding register (W) */ 45120122Sbde#define com_rhr com_data /* receiver holding register (R) */ 46120116Sbde 47120119Sbde#define com_ier 1 /* interrupt enable register (W) */ 48120116Sbde#define IER_ERXRDY 0x1 49120116Sbde#define IER_ETXRDY 0x2 50120116Sbde#define IER_ERLS 0x4 51120116Sbde#define IER_EMSC 0x8 52120116Sbde 53120119Sbde#define com_iir 2 /* interrupt identification register (R) */ 54120122Sbde#define com_isr com_iir /* interrupt status register (R) */ 55120116Sbde#define IIR_IMASK 0xf 56120116Sbde#define IIR_RXTOUT 0xc 57120116Sbde#define IIR_RLS 0x6 58120116Sbde#define IIR_RXRDY 0x4 59120116Sbde#define IIR_TXRDY 0x2 60120116Sbde#define IIR_NOPEND 0x1 61120116Sbde#define IIR_MLSC 0x0 62120116Sbde#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 63120116Sbde 64120122Sbde#define com_lcr 3 /* line control register (R/W) */ 65120122Sbde#define com_lctl com_lcr 66120122Sbde#define com_cfcr com_lcr /* character format control register (R/W) */ 67120122Sbde#define LCR_DLAB 0x80 68120122Sbde#define CFCR_DLAB LCR_DLAB 69120122Sbde#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 70120122Sbde#define CFCR_EFR_ENABLE LCR_EFR_ENABLE 71120116Sbde#define CFCR_SBREAK 0x40 72120116Sbde#define CFCR_PZERO 0x30 73120116Sbde#define CFCR_PONE 0x20 74120116Sbde#define CFCR_PEVEN 0x10 75120116Sbde#define CFCR_PODD 0x00 76120116Sbde#define CFCR_PENAB 0x08 77120116Sbde#define CFCR_STOPB 0x04 78120116Sbde#define CFCR_8BITS 0x03 79120116Sbde#define CFCR_7BITS 0x02 80120116Sbde#define CFCR_6BITS 0x01 81120116Sbde#define CFCR_5BITS 0x00 82120116Sbde 83120119Sbde#define com_mcr 4 /* modem control register (R/W) */ 84120119Sbde#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 85120116Sbde#define MCR_LOOPBACK 0x10 86120116Sbde#define MCR_IENABLE 0x08 87120116Sbde#define MCR_DRS 0x04 88120116Sbde#define MCR_RTS 0x02 89120116Sbde#define MCR_DTR 0x01 90120116Sbde 91120119Sbde#define com_lsr 5 /* line status register (R/W) */ 92120116Sbde#define LSR_RCV_FIFO 0x80 93120116Sbde#define LSR_TSRE 0x40 94120116Sbde#define LSR_TXRDY 0x20 95120116Sbde#define LSR_BI 0x10 96120116Sbde#define LSR_FE 0x08 97120116Sbde#define LSR_PE 0x04 98120116Sbde#define LSR_OE 0x02 99120116Sbde#define LSR_RXRDY 0x01 100120116Sbde#define LSR_RCV_MASK 0x1f 101120116Sbde 102120119Sbde#define com_msr 6 /* modem status register (R/W) */ 103120116Sbde#define MSR_DCD 0x80 104120116Sbde#define MSR_RI 0x40 105120116Sbde#define MSR_DSR 0x20 106120116Sbde#define MSR_CTS 0x10 107120116Sbde#define MSR_DDCD 0x08 108120116Sbde#define MSR_TERI 0x04 109120116Sbde#define MSR_DDSR 0x02 110120116Sbde#define MSR_DCTS 0x01 111120116Sbde 112120119Sbde/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 113120122Sbde#define com_dll 0 /* divisor latch low (R/W) */ 114120122Sbde#define com_dlbl com_dll 115120122Sbde#define com_dlm 1 /* divisor latch high (R/W) */ 116120122Sbde#define com_dlbh com_dlm 117120116Sbde 118120119Sbde/* 16450 register #7. Not multiplexed. */ 119120119Sbde#define com_scr 7 /* scratch register (R/W) */ 120120119Sbde 121120119Sbde/* 16550 register #2. Not multiplexed. */ 122120122Sbde#define com_fcr 2 /* FIFO control register (W) */ 123120122Sbde#define com_fifo com_fcr 124120119Sbde#define FIFO_ENABLE 0x01 125120119Sbde#define FIFO_RCV_RST 0x02 126120119Sbde#define FIFO_XMT_RST 0x04 127120119Sbde#define FIFO_DMA_MODE 0x08 128120119Sbde#define FIFO_RX_LOW 0x00 129120119Sbde#define FIFO_RX_MEDL 0x40 130120119Sbde#define FIFO_RX_MEDH 0x80 131120119Sbde#define FIFO_RX_HIGH 0xc0 132120119Sbde 133120119Sbde/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 134120119Sbde 135120122Sbde#define com_efr 2 /* enhanced features register (R/W) */ 136120123Sbde#define EFR_AUTOCTS 0x80 137120123Sbde#define EFR_AUTORTS 0x40 138120119Sbde#define EFR_EFE 0x10 /* enhanced functions enable */ 139120119Sbde 140120123Sbde#define com_xon1 4 /* XON 1 character (R/W) */ 141120123Sbde#define com_xon2 5 /* XON 2 character (R/W) */ 142120123Sbde#define com_xoff1 6 /* XOFF 1 character (R/W) */ 143120123Sbde#define com_xoff2 7 /* XOFF 2 character (R/W) */ 144120123Sbde 145120124Sbde/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 146120124Sbde#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 147120124Sbde 148120124Sbde/* 16950 register #3. R/W access enabled by ACR[7]. */ 149120124Sbde#define com_rfl 3 /* receiver fifo level (R) */ 150120124Sbde 151120124Sbde/* 152120124Sbde * 16950 register #4. Access enabled by ACR[7]. Also requires 153120124Sbde * !LCR_EFR_ENABLE. 154120124Sbde */ 155120124Sbde#define com_tfl 4 /* transmitter fifo level (R) */ 156120124Sbde 157120124Sbde/* 158120124Sbde * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 159120124Sbde * requires ACR[6]. 160120124Sbde */ 161120124Sbde#define com_icr 5 /* index control register (R/W) */ 162120124Sbde 163120124Sbde/* 164120124Sbde * 16950 register #7. It is the same as com_scr except it has a different 165120124Sbde * abbreviation in the manufacturer's data sheet and it also serves as an 166120124Sbde * index into the Indexed Control register set. 167120124Sbde */ 168120124Sbde#define com_spr com_scr /* scratch pad (and index) register (R/W) */ 169120124Sbde 170120124Sbde/* 171120124Sbde * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 172120124Sbde * data in ICR (if ICR is accessible). 173120124Sbde */ 174120124Sbde 175120124Sbde#define com_acr 0 /* additional control register (R/W) */ 176120124Sbde#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 177120124Sbde#define ACR_ICRE 0x40 /* ICR enable */ 178120124Sbde#define ACR_TLE 0x20 /* TTL/RTL enable */ 179120124Sbde 180120124Sbde#define com_cpr 1 /* clock prescaler register (R/W) */ 181120124Sbde#define com_tcr 2 /* times clock register (R/W) */ 182120124Sbde#define com_ttl 4 /* transmitter trigger level (R/W) */ 183120124Sbde#define com_rtl 5 /* receiver trigger level (R/W) */ 184120124Sbde/* ... */ 185120124Sbde 186120116Sbde#ifdef PC98 187120116Sbde/* Hardware extension mode register for RSB-2000/3000. */ 188120116Sbde#define com_emr com_msr 189120116Sbde#define EMR_EXBUFF 0x04 190120116Sbde#define EMR_CTSFLW 0x08 191120116Sbde#define EMR_DSRFLW 0x10 192120116Sbde#define EMR_RTSFLW 0x20 193120116Sbde#define EMR_DTRFLW 0x40 194120116Sbde#define EMR_EFMODE 0x80 195120116Sbde#endif 196