19406Sbde/*- 26261Sjkh * cyclades cyclom-y serial driver 36261Sjkh * Andrew Herbert <andrew@werple.apana.org.au>, 17 August 1993 46261Sjkh * 56261Sjkh * Copyright (c) 1993 Andrew Herbert. 66261Sjkh * All rights reserved. 76261Sjkh * 86261Sjkh * Redistribution and use in source and binary forms, with or without 96261Sjkh * modification, are permitted provided that the following conditions 106261Sjkh * are met: 116261Sjkh * 1. Redistributions of source code must retain the above copyright 126261Sjkh * notice, this list of conditions and the following disclaimer. 136261Sjkh * 2. Redistributions in binary form must reproduce the above copyright 146261Sjkh * notice, this list of conditions and the following disclaimer in the 156261Sjkh * documentation and/or other materials provided with the distribution. 166261Sjkh * 3. The name Andrew Herbert may not be used to endorse or promote products 176261Sjkh * derived from this software without specific prior written permission. 186261Sjkh * 196261Sjkh * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED 206261Sjkh * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 216261Sjkh * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 226261Sjkh * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 236261Sjkh * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 246261Sjkh * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 256261Sjkh * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 266261Sjkh * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 276261Sjkh * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 286261Sjkh * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 299406Sbde * 3050477Speter * $FreeBSD: releng/10.2/sys/dev/ic/cd1400.h 50477 1999-08-28 01:08:13Z peter $ 316261Sjkh */ 326261Sjkh 339406Sbde/* 349406Sbde * Definitions for Cirrus Logic CD1400 serial/parallel chips. 359406Sbde */ 366261Sjkh 379406Sbde#define CD1400_NO_OF_CHANNELS 4 /* 4 serial channels per chip */ 389406Sbde#define CD1400_RX_FIFO_SIZE 12 399406Sbde#define CD1400_TX_FIFO_SIZE 12 406261Sjkh 419406Sbde/* 429406Sbde * Global registers. 439406Sbde */ 449406Sbde#define CD1400_GFRCR 0x40 /* global firmware revision code */ 459406Sbde#define CD1400_CAR 0x68 /* channel access */ 469406Sbde#define CD1400_CAR_CHAN (3<<0) /* channel select */ 479406Sbde#define CD1400_GCR 0x4B /* global configuration */ 489406Sbde#define CD1400_GCR_PARALLEL (1<<7) /* channel 0 is parallel */ 499406Sbde#define CD1400_SVRR 0x67 /* service request */ 509406Sbde#define CD1400_SVRR_MDMCH (1<<2) 519406Sbde#define CD1400_SVRR_TXRDY (1<<1) 529406Sbde#define CD1400_SVRR_RXRDY (1<<0) 539406Sbde#define CD1400_RICR 0x44 /* receive interrupting channel */ 549406Sbde#define CD1400_TICR 0x45 /* transmit interrupting channel */ 559406Sbde#define CD1400_MICR 0x46 /* modem interrupting channel */ 569406Sbde#define CD1400_RIR 0x6B /* receive interrupt status */ 579406Sbde#define CD1400_RIR_RDIREQ (1<<7) /* rx service required */ 589406Sbde#define CD1400_RIR_RBUSY (1<<6) /* rx service in progress */ 599406Sbde#define CD1400_RIR_CHAN (3<<0) /* channel select */ 609406Sbde#define CD1400_TIR 0x6A /* transmit interrupt status */ 619406Sbde#define CD1400_TIR_RDIREQ (1<<7) /* tx service required */ 629406Sbde#define CD1400_TIR_RBUSY (1<<6) /* tx service in progress */ 639406Sbde#define CD1400_TIR_CHAN (3<<0) /* channel select */ 649406Sbde#define CD1400_MIR 0x69 /* modem interrupt status */ 659406Sbde#define CD1400_MIR_RDIREQ (1<<7) /* modem service required */ 669406Sbde#define CD1400_MIR_RBUSY (1<<6) /* modem service in progress */ 679406Sbde#define CD1400_MIR_CHAN (3<<0) /* channel select */ 689406Sbde#define CD1400_PPR 0x7E /* prescaler period */ 699406Sbde#define CD1400_PPR_PRESCALER 512 706261Sjkh 719406Sbde/* 729406Sbde * Virtual registers. 739406Sbde */ 749406Sbde#define CD1400_RIVR 0x43 /* receive interrupt vector */ 759406Sbde#define CD1400_RIVR_EXCEPTION (1<<2) /* receive exception bit */ 769406Sbde#define CD1400_TIVR 0x42 /* transmit interrupt vector */ 779406Sbde#define CD1400_MIVR 0x41 /* modem interrupt vector */ 789406Sbde#define CD1400_TDR 0x63 /* transmit data */ 799406Sbde#define CD1400_RDSR 0x62 /* receive data/status */ 809406Sbde#define CD1400_RDSR_TIMEOUT (1<<7) /* rx timeout */ 819406Sbde#define CD1400_RDSR_SPECIAL_SHIFT 4 /* rx special char shift */ 829406Sbde#define CD1400_RDSR_SPECIAL (7<<4) /* rx special char */ 839406Sbde#define CD1400_RDSR_BREAK (1<<3) /* rx break */ 849406Sbde#define CD1400_RDSR_PE (1<<2) /* rx parity error */ 859406Sbde#define CD1400_RDSR_FE (1<<1) /* rx framing error */ 869406Sbde#define CD1400_RDSR_OE (1<<0) /* rx overrun error */ 879406Sbde#define CD1400_MISR 0x4C /* modem interrupt status */ 889406Sbde#define CD1400_MISR_DSRd (1<<7) /* DSR delta */ 899406Sbde#define CD1400_MISR_CTSd (1<<6) /* CTS delta */ 909406Sbde#define CD1400_MISR_RId (1<<5) /* RI delta */ 919406Sbde#define CD1400_MISR_CDd (1<<4) /* CD delta */ 929406Sbde#define CD1400_EOSRR 0x60 /* end of service request */ 936261Sjkh 949406Sbde/* 959406Sbde * Channel registers. 969406Sbde */ 979406Sbde#define CD1400_LIVR 0x18 /* local interrupt vector */ 989406Sbde#define CD1400_CCR 0x05 /* channel control */ 999406Sbde#define CD1400_CCR_CMDRESET (1<<7) /* enables following: */ 1009406Sbde#define CD1400_CCR_FTF (1<<1) /* flush tx fifo */ 1019406Sbde#define CD1400_CCR_FULLRESET (1<<0) /* full reset */ 10241903Sbde#define CD1400_CCR_CHANRESET 0 /* current channel */ 1039406Sbde#define CD1400_CCR_CMDCORCHG (1<<6) /* enables following: */ 1049406Sbde#define CD1400_CCR_COR3 (1<<3) /* COR3 changed */ 1059406Sbde#define CD1400_CCR_COR2 (1<<2) /* COR2 changed */ 1069406Sbde#define CD1400_CCR_COR1 (1<<1) /* COR1 changed */ 1079406Sbde#define CD1400_CCR_CMDSENDSC (1<<5) /* enables following: */ 1089406Sbde#define CD1400_CCR_SC (7<<0) /* special char 1-4 */ 1099406Sbde#define CD1400_CCR_CMDCHANCTL (1<<4) /* enables following: */ 1109406Sbde#define CD1400_CCR_XMTEN (1<<3) /* tx enable */ 1119406Sbde#define CD1400_CCR_XMTDIS (1<<2) /* tx disable */ 1129406Sbde#define CD1400_CCR_RCVEN (1<<1) /* rx enable */ 1139406Sbde#define CD1400_CCR_RCVDIS (1<<0) /* rx disable */ 1149406Sbde#define CD1400_SRER 0x06 /* service request enable */ 1159406Sbde#define CD1400_SRER_MDMCH (1<<7) /* modem change */ 1169406Sbde#define CD1400_SRER_RXDATA (1<<4) /* rx data */ 1179406Sbde#define CD1400_SRER_TXRDY (1<<2) /* tx fifo empty */ 1189406Sbde#define CD1400_SRER_TXMPTY (1<<1) /* tx shift reg empty */ 1199406Sbde#define CD1400_SRER_NNDT (1<<0) /* no new data */ 1209406Sbde#define CD1400_COR1 0x08 /* channel option 1 */ 1219406Sbde#define CD1400_COR1_PARODD (1<<7) 1229406Sbde#define CD1400_COR1_PARNORMAL (2<<5) 1239406Sbde#define CD1400_COR1_PARFORCE (1<<5) /* odd/even = force 1/0 */ 1249406Sbde#define CD1400_COR1_PARNONE (0<<5) 1259406Sbde#define CD1400_COR1_NOINPCK (1<<4) 1269406Sbde#define CD1400_COR1_STOP2 (2<<2) 1279406Sbde#define CD1400_COR1_STOP15 (1<<2) /* 1.5 stop bits */ 1289406Sbde#define CD1400_COR1_STOP1 (0<<2) 1299406Sbde#define CD1400_COR1_CS8 (3<<0) 1309406Sbde#define CD1400_COR1_CS7 (2<<0) 1319406Sbde#define CD1400_COR1_CS6 (1<<0) 1329406Sbde#define CD1400_COR1_CS5 (0<<0) 1339406Sbde#define CD1400_COR2 0x09 /* channel option 2 */ 1349406Sbde#define CD1400_COR2_IXANY (1<<7) /* implied XON mode */ 1359406Sbde#define CD1400_COR2_IXOFF (1<<6) /* in-band tx flow control */ 1369406Sbde#define CD1400_COR2_ETC (1<<5) /* embedded tx command */ 13741903Sbde#define CD1400_ETC_CMD 0x00 /* start an ETC */ 13841903Sbde#define CD1400_ETC_SENDBREAK 0x81 13941903Sbde#define CD1400_ETC_INSERTDELAY 0x82 14041903Sbde#define CD1400_ETC_STOPBREAK 0x83 1419406Sbde#define CD1400_COR2_LLM (1<<4) /* local loopback mode */ 1429406Sbde#define CD1400_COR2_RLM (1<<3) /* remote loopback mode */ 1439406Sbde#define CD1400_COR2_RTSAO (1<<2) /* RTS auto output */ 1449406Sbde#define CD1400_COR2_CCTS_OFLOW (1<<1) /* CTS auto enable */ 1459406Sbde#define CD1400_COR2_CDSR_OFLOW (1<<0) /* DSR auto enable */ 1469406Sbde#define CD1400_COR3 0x0A /* channel option 3 */ 1479406Sbde#define CD1400_COR3_SCDRNG (1<<7) /* special char detect range */ 1489406Sbde#define CD1400_COR3_SCD34 (1<<6) /* special char detect 3-4 */ 1499406Sbde#define CD1400_COR3_FTC (1<<5) /* flow control transparency */ 1509406Sbde#define CD1400_COR3_SCD12 (1<<4) /* special char detect 1-2 */ 1519406Sbde#define CD1400_COR3_RXTH (15<<0) /* rx fifo threshold */ 1529406Sbde#define CD1400_COR4 0x1E /* channel option 4 */ 1539406Sbde#define CD1400_COR4_IGNCR (1<<7) 1549406Sbde#define CD1400_COR4_ICRNL (1<<6) 1559406Sbde#define CD1400_COR4_INLCR (1<<5) 1569406Sbde#define CD1400_COR4_IGNBRK (1<<4) 1579406Sbde#define CD1400_COR4_NOBRKINT (1<<3) 1589406Sbde#define CD1400_COR4_PFO_ESC (4<<0) /* parity/framing/overrun... */ 1599406Sbde#define CD1400_COR4_PFO_NUL (3<<0) 1609406Sbde#define CD1400_COR4_PFO_DISCARD (2<<0) 1619406Sbde#define CD1400_COR4_PFO_GOOD (1<<0) 1629406Sbde#define CD1400_COR4_PFO_EXCEPTION (0<<0) 1639406Sbde#define CD1400_COR5 0x1F /* channel option 5 */ 1649406Sbde#define CD1400_COR5_ISTRIP (1<<7) 1659406Sbde#define CD1400_COR5_LNEXT (1<<6) 1669406Sbde#define CD1400_COR5_CMOE (1<<5) /* char matching on error */ 1679406Sbde#define CD1400_COR5_EBD (1<<2) /* end of break detected */ 1689406Sbde#define CD1400_COR5_ONLCR (1<<1) 1699406Sbde#define CD1400_COR5_OCRNL (1<<0) 1709406Sbde#define CD1400_CCSR 0x0B /* channel control status */ 1719406Sbde#define CD1400_RDCR 0x0E /* received data count */ 1729406Sbde#define CD1400_SCHR1 0x1A /* special character 1 */ 1739406Sbde#define CD1400_SCHR2 0x1B /* special character 2 */ 1749406Sbde#define CD1400_SCHR3 0x1C /* special character 3 */ 1759406Sbde#define CD1400_SCHR4 0x1D /* special character 4 */ 1769406Sbde#define CD1400_SCRL 0x22 /* special character range, low */ 1779406Sbde#define CD1400_SCRH 0x23 /* special character range, high */ 1789406Sbde#define CD1400_LNC 0x24 /* lnext character */ 1799406Sbde#define CD1400_MCOR1 0x15 /* modem change option 1 */ 1809406Sbde#define CD1400_MCOR1_DSRzd (1<<7) /* DSR one-to-zero delta */ 1819406Sbde#define CD1400_MCOR1_CTSzd (1<<6) 1829406Sbde#define CD1400_MCOR1_RIzd (1<<5) 1839406Sbde#define CD1400_MCOR1_CDzd (1<<4) 1849406Sbde#define CD1400_MCOR1_DTRth (15<<0) /* dtrflow threshold */ 1859406Sbde#define CD1400_MCOR2 0x16 /* modem change option 2 */ 1869406Sbde#define CD1400_MCOR2_DSRod (1<<7) /* DSR zero-to-one delta */ 1879406Sbde#define CD1400_MCOR2_CTSod (1<<6) 1889406Sbde#define CD1400_MCOR2_RIod (1<<5) 1899406Sbde#define CD1400_MCOR2_CDod (1<<4) 1909406Sbde#define CD1400_RTPR 0x21 /* receive timeout period */ 1919406Sbde#define CD1400_MSVR1 0x6C /* modem signal value 1 */ 1929406Sbde#define CD1400_MSVR1_RTS (1<<0) /* RTS line (r/w) */ 1939406Sbde#define CD1400_MSVR2 0x6D /* modem signal value 2 */ 1949406Sbde#define CD1400_MSVR2_DSR (1<<7) /* !DSR line (r) */ 1959406Sbde#define CD1400_MSVR2_CTS (1<<6) /* !CTS line (r) */ 1969406Sbde#define CD1400_MSVR2_RI (1<<5) /* !RI line (r) */ 1979406Sbde#define CD1400_MSVR2_CD (1<<4) /* !CD line (r) */ 1989406Sbde#define CD1400_MSVR2_DTR (1<<1) /* DTR line (r/w) */ 1999406Sbde#define CD1400_PSVR 0x6F /* printer signal value */ 2009406Sbde#define CD1400_RBPR 0x78 /* receive baud rate period */ 2019406Sbde#define CD1400_RCOR 0x7C /* receive clock option */ 2029406Sbde#define CD1400_TBPR 0x72 /* transmit baud rate period */ 2039406Sbde#define CD1400_TCOR 0x76 /* transmit clock option */ 204