1185363Sjkoshy/*- 2185363Sjkoshy * Copyright (c) 2008 Joseph Koshy 3185363Sjkoshy * All rights reserved. 4185363Sjkoshy * 5185363Sjkoshy * Redistribution and use in source and binary forms, with or without 6185363Sjkoshy * modification, are permitted provided that the following conditions 7185363Sjkoshy * are met: 8185363Sjkoshy * 1. Redistributions of source code must retain the above copyright 9185363Sjkoshy * notice, this list of conditions and the following disclaimer. 10185363Sjkoshy * 2. Redistributions in binary form must reproduce the above copyright 11185363Sjkoshy * notice, this list of conditions and the following disclaimer in the 12185363Sjkoshy * documentation and/or other materials provided with the distribution. 13185363Sjkoshy * 14185363Sjkoshy * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15185363Sjkoshy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16185363Sjkoshy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17185363Sjkoshy * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18185363Sjkoshy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19185363Sjkoshy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20185363Sjkoshy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21185363Sjkoshy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22185363Sjkoshy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23185363Sjkoshy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24185363Sjkoshy * SUCH DAMAGE. 25185363Sjkoshy * 26185363Sjkoshy * $FreeBSD: releng/10.2/sys/dev/hwpmc/hwpmc_core.h 266452 2014-05-19 19:49:06Z markj $ 27185363Sjkoshy */ 28185363Sjkoshy 29185363Sjkoshy#ifndef _DEV_HWPMC_CORE_H_ 30185363Sjkoshy#define _DEV_HWPMC_CORE_H_ 1 31185363Sjkoshy 32185363Sjkoshy/* 33185363Sjkoshy * Fixed-function PMCs. 34185363Sjkoshy */ 35185363Sjkoshystruct pmc_md_iaf_op_pmcallocate { 36185363Sjkoshy uint16_t pm_iaf_flags; /* additional flags */ 37185363Sjkoshy}; 38185363Sjkoshy 39185363Sjkoshy#define IAF_OS 0x1 40185363Sjkoshy#define IAF_USR 0x2 41185363Sjkoshy#define IAF_ANY 0x4 42185363Sjkoshy#define IAF_PMI 0x8 43185363Sjkoshy 44185363Sjkoshy/* 45185363Sjkoshy * Programmable PMCs. 46185363Sjkoshy */ 47185363Sjkoshystruct pmc_md_iap_op_pmcallocate { 48185363Sjkoshy uint32_t pm_iap_config; 49240164Sfabient uint64_t pm_iap_rsp; 50185363Sjkoshy}; 51185363Sjkoshy 52185363Sjkoshy#define IAP_EVSEL(C) ((C) & 0xFF) 53185363Sjkoshy#define IAP_UMASK(C) ((C) & 0xFF00) 54185363Sjkoshy#define IAP_USR (1 << 16) 55185363Sjkoshy#define IAP_OS (1 << 17) 56185363Sjkoshy#define IAP_EDGE (1 << 18) 57185363Sjkoshy#define IAP_INT (1 << 20) 58185363Sjkoshy#define IAP_ANY (1 << 21) 59185363Sjkoshy#define IAP_EN (1 << 22) 60185363Sjkoshy#define IAP_INV (1 << 23) 61185363Sjkoshy#define IAP_CMASK(C) (((C) & 0xFF) << 24) 62185363Sjkoshy 63240164Sfabient#define IA_OFFCORE_RSP_MASK_I7WM 0x000000F7FF 64240164Sfabient#define IA_OFFCORE_RSP_MASK_SBIB 0x3F807F8FFF 65206089Sfabient 66185363Sjkoshy#ifdef _KERNEL 67185363Sjkoshy 68185363Sjkoshy/* 69185363Sjkoshy * Fixed-function counters. 70185363Sjkoshy */ 71210012Sgnn 72185363Sjkoshy#define IAF_MASK 0xF 73185363Sjkoshy 74210012Sgnn#define IAF_COUNTER_MASK 0x0000ffffffffffff 75185363Sjkoshy#define IAF_CTR0 0x309 76185363Sjkoshy#define IAF_CTR1 0x30A 77185363Sjkoshy#define IAF_CTR2 0x30B 78185363Sjkoshy 79210012Sgnn/* 80210012Sgnn * The IAF_CTRL MSR is laid out in the following way. 81210012Sgnn * 82210012Sgnn * Bit Position Use 83210012Sgnn * 63 - 12 Reserved (do not touch) 84210012Sgnn * 11 Ctr 2 PMI 85210012Sgnn * 10 Reserved (do not touch) 86210012Sgnn * 9-8 Ctr 2 Enable 87210012Sgnn * 7 Ctr 1 PMI 88210012Sgnn * 6 Reserved (do not touch) 89210012Sgnn * 5-4 Ctr 1 Enable 90210012Sgnn * 3 Ctr 0 PMI 91210012Sgnn * 2 Reserved (do not touch) 92210012Sgnn * 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable) 93210012Sgnn */ 94210012Sgnn 95185363Sjkoshy#define IAF_OFFSET 32 96185363Sjkoshy#define IAF_CTRL 0x38D 97210012Sgnn#define IAF_CTRL_MASK 0x0000000000000bbb 98185363Sjkoshy 99185363Sjkoshy/* 100185363Sjkoshy * Programmable counters. 101185363Sjkoshy */ 102206089Sfabient 103185363Sjkoshy#define IAP_PMC0 0x0C1 104210012Sgnn 105210012Sgnn/* 106210012Sgnn * IAP_EVSEL(n) is laid out in the following way. 107210012Sgnn * 108210012Sgnn * Bit Position Use 109210012Sgnn * 63-31 Reserved (do not touch) 110210012Sgnn * 31-24 Counter Mask 111210012Sgnn * 23 Invert 112210012Sgnn * 22 Enable 113210012Sgnn * 21 Reserved (do not touch) 114210012Sgnn * 20 APIC Interrupt Enable 115210012Sgnn * 19 Pin Control 116210012Sgnn * 18 Edge Detect 117210012Sgnn * 17 OS 118210012Sgnn * 16 User 119210012Sgnn * 15-8 Unit Mask 120210012Sgnn * 7-0 Event Select 121210012Sgnn */ 122210012Sgnn 123210012Sgnn#define IAP_EVSEL_MASK 0x00000000ffdfffff 124185363Sjkoshy#define IAP_EVSEL0 0x186 125185363Sjkoshy 126185363Sjkoshy/* 127185363Sjkoshy * Simplified programming interface in Intel Performance Architecture 128185363Sjkoshy * v2 and later. 129185363Sjkoshy */ 130206089Sfabient 131185363Sjkoshy#define IA_GLOBAL_STATUS 0x38E 132185363Sjkoshy#define IA_GLOBAL_CTRL 0x38F 133210012Sgnn 134210012Sgnn/* 135210012Sgnn * IA_GLOBAL_CTRL is layed out in the following way. 136210012Sgnn * 137210012Sgnn * Bit Position Use 138210012Sgnn * 63-35 Reserved (do not touch) 139210012Sgnn * 34 IAF Counter 2 Enable 140210012Sgnn * 33 IAF Counter 1 Enable 141210012Sgnn * 32 IAF Counter 0 Enable 142210012Sgnn * 31-0 Depends on programmable counters 143210012Sgnn */ 144210012Sgnn 145210012Sgnn/* The mask is only for the fixed porttion of the register. */ 146210012Sgnn#define IAF_GLOBAL_CTRL_MASK 0x0000000700000000 147210012Sgnn 148210621Sgnn/* The mask is only for the programmable porttion of the register. */ 149210621Sgnn#define IAP_GLOBAL_CTRL_MASK 0x00000000ffffffff 150210621Sgnn 151210621Sgnn/* The mask is for both the fixed and programmable porttions of the register. */ 152210621Sgnn#define IA_GLOBAL_CTRL_MASK 0x00000007ffffffff 153210621Sgnn 154185363Sjkoshy#define IA_GLOBAL_OVF_CTRL 0x390 155185363Sjkoshy 156185363Sjkoshy#define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 157185363Sjkoshy#define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 158185363Sjkoshy 159206089Sfabient/* 160206089Sfabient * Offcore response configuration. 161206089Sfabient */ 162206089Sfabient#define IA_OFFCORE_RSP0 0x1A6 163206089Sfabient#define IA_OFFCORE_RSP1 0x1A7 164206089Sfabient 165185363Sjkoshystruct pmc_md_iaf_pmc { 166185363Sjkoshy uint64_t pm_iaf_ctrl; 167185363Sjkoshy}; 168185363Sjkoshy 169185363Sjkoshystruct pmc_md_iap_pmc { 170185363Sjkoshy uint32_t pm_iap_evsel; 171240164Sfabient uint64_t pm_iap_rsp; 172185363Sjkoshy}; 173185363Sjkoshy 174185363Sjkoshy/* 175185363Sjkoshy * Prototypes. 176185363Sjkoshy */ 177185363Sjkoshy 178185363Sjkoshyint pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu); 179185363Sjkoshyvoid pmc_core_finalize(struct pmc_mdep *_md); 180185363Sjkoshy 181185363Sjkoshyint pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width); 182185363Sjkoshyvoid pmc_iaf_finalize(struct pmc_mdep *_md); 183185363Sjkoshy 184185363Sjkoshyint pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width, 185185363Sjkoshy int _flags); 186185363Sjkoshyvoid pmc_iap_finalize(struct pmc_mdep *_md); 187185363Sjkoshy 188185363Sjkoshy#endif /* _KERNEL */ 189185363Sjkoshy#endif /* _DEV_HWPMC_CORE_H */ 190