hwpmc_core.c revision 248842
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 248842 2013-03-28 19:15:54Z sbruno $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#include <machine/apicvar.h> 42#include <machine/cpu.h> 43#include <machine/cpufunc.h> 44#include <machine/md_var.h> 45#include <machine/specialreg.h> 46 47#define CORE_CPUID_REQUEST 0xA 48#define CORE_CPUID_REQUEST_SIZE 0x4 49#define CORE_CPUID_EAX 0x0 50#define CORE_CPUID_EBX 0x1 51#define CORE_CPUID_ECX 0x2 52#define CORE_CPUID_EDX 0x3 53 54#define IAF_PMC_CAPS \ 55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 56 PMC_CAP_USER | PMC_CAP_SYSTEM) 57#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 58 59#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 62 63/* 64 * "Architectural" events defined by Intel. The values of these 65 * symbols correspond to positions in the bitmask returned by 66 * the CPUID.0AH instruction. 67 */ 68enum core_arch_events { 69 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 70 CORE_AE_BRANCH_MISSES_RETIRED = 6, 71 CORE_AE_INSTRUCTION_RETIRED = 1, 72 CORE_AE_LLC_MISSES = 4, 73 CORE_AE_LLC_REFERENCE = 3, 74 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 75 CORE_AE_UNHALTED_CORE_CYCLES = 0 76}; 77 78static enum pmc_cputype core_cputype; 79 80struct core_cpu { 81 volatile uint32_t pc_resync; 82 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 83 volatile uint64_t pc_globalctrl; /* Global control register. */ 84 struct pmc_hw pc_corepmcs[]; 85}; 86 87static struct core_cpu **core_pcpu; 88 89static uint32_t core_architectural_events; 90static uint64_t core_pmcmask; 91 92static int core_iaf_ri; /* relative index of fixed counters */ 93static int core_iaf_width; 94static int core_iaf_npmc; 95 96static int core_iap_width; 97static int core_iap_npmc; 98 99static int 100core_pcpu_noop(struct pmc_mdep *md, int cpu) 101{ 102 (void) md; 103 (void) cpu; 104 return (0); 105} 106 107static int 108core_pcpu_init(struct pmc_mdep *md, int cpu) 109{ 110 struct pmc_cpu *pc; 111 struct core_cpu *cc; 112 struct pmc_hw *phw; 113 int core_ri, n, npmc; 114 115 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 116 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 117 118 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 119 120 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 121 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 122 123 if (core_cputype != PMC_CPU_INTEL_CORE) 124 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 125 126 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 127 M_PMC, M_WAITOK | M_ZERO); 128 129 core_pcpu[cpu] = cc; 130 pc = pmc_pcpu[cpu]; 131 132 KASSERT(pc != NULL && cc != NULL, 133 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 134 135 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 136 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 137 PMC_PHW_CPU_TO_STATE(cpu) | 138 PMC_PHW_INDEX_TO_STATE(n + core_ri); 139 phw->phw_pmc = NULL; 140 pc->pc_hwpmcs[n + core_ri] = phw; 141 } 142 143 return (0); 144} 145 146static int 147core_pcpu_fini(struct pmc_mdep *md, int cpu) 148{ 149 int core_ri, n, npmc; 150 struct pmc_cpu *pc; 151 struct core_cpu *cc; 152 uint64_t msr = 0; 153 154 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 155 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 156 157 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 158 159 if ((cc = core_pcpu[cpu]) == NULL) 160 return (0); 161 162 core_pcpu[cpu] = NULL; 163 164 pc = pmc_pcpu[cpu]; 165 166 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 167 cpu)); 168 169 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 170 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 171 172 for (n = 0; n < npmc; n++) { 173 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 174 wrmsr(IAP_EVSEL0 + n, msr); 175 } 176 177 if (core_cputype != PMC_CPU_INTEL_CORE) { 178 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 179 wrmsr(IAF_CTRL, msr); 180 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 181 } 182 183 for (n = 0; n < npmc; n++) 184 pc->pc_hwpmcs[n + core_ri] = NULL; 185 186 free(cc, M_PMC); 187 188 return (0); 189} 190 191/* 192 * Fixed function counters. 193 */ 194 195static pmc_value_t 196iaf_perfctr_value_to_reload_count(pmc_value_t v) 197{ 198 v &= (1ULL << core_iaf_width) - 1; 199 return (1ULL << core_iaf_width) - v; 200} 201 202static pmc_value_t 203iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 204{ 205 return (1ULL << core_iaf_width) - rlc; 206} 207 208static int 209iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 210 const struct pmc_op_pmcallocate *a) 211{ 212 enum pmc_event ev; 213 uint32_t caps, flags, validflags; 214 215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 216 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 217 218 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 219 220 if (ri < 0 || ri > core_iaf_npmc) 221 return (EINVAL); 222 223 caps = a->pm_caps; 224 225 if (a->pm_class != PMC_CLASS_IAF || 226 (caps & IAF_PMC_CAPS) != caps) 227 return (EINVAL); 228 229 ev = pm->pm_event; 230 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 231 return (EINVAL); 232 233 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 234 return (EINVAL); 235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 236 return (EINVAL); 237 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 238 return (EINVAL); 239 240 flags = a->pm_md.pm_iaf.pm_iaf_flags; 241 242 validflags = IAF_MASK; 243 244 if (core_cputype != PMC_CPU_INTEL_ATOM) 245 validflags &= ~IAF_ANY; 246 247 if ((flags & ~validflags) != 0) 248 return (EINVAL); 249 250 if (caps & PMC_CAP_INTERRUPT) 251 flags |= IAF_PMI; 252 if (caps & PMC_CAP_SYSTEM) 253 flags |= IAF_OS; 254 if (caps & PMC_CAP_USER) 255 flags |= IAF_USR; 256 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 257 flags |= (IAF_OS | IAF_USR); 258 259 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 260 261 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 262 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 263 264 return (0); 265} 266 267static int 268iaf_config_pmc(int cpu, int ri, struct pmc *pm) 269{ 270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 271 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 272 273 KASSERT(ri >= 0 && ri < core_iaf_npmc, 274 ("[core,%d] illegal row-index %d", __LINE__, ri)); 275 276 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 277 278 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 279 cpu)); 280 281 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 282 283 return (0); 284} 285 286static int 287iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 288{ 289 int error; 290 struct pmc_hw *phw; 291 char iaf_name[PMC_NAME_MAX]; 292 293 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 294 295 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 296 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 297 NULL)) != 0) 298 return (error); 299 300 pi->pm_class = PMC_CLASS_IAF; 301 302 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 303 pi->pm_enabled = TRUE; 304 *ppmc = phw->phw_pmc; 305 } else { 306 pi->pm_enabled = FALSE; 307 *ppmc = NULL; 308 } 309 310 return (0); 311} 312 313static int 314iaf_get_config(int cpu, int ri, struct pmc **ppm) 315{ 316 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 317 318 return (0); 319} 320 321static int 322iaf_get_msr(int ri, uint32_t *msr) 323{ 324 KASSERT(ri >= 0 && ri < core_iaf_npmc, 325 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 326 327 *msr = IAF_RI_TO_MSR(ri); 328 329 return (0); 330} 331 332static int 333iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 334{ 335 struct pmc *pm; 336 pmc_value_t tmp; 337 338 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 339 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 340 KASSERT(ri >= 0 && ri < core_iaf_npmc, 341 ("[core,%d] illegal row-index %d", __LINE__, ri)); 342 343 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 344 345 KASSERT(pm, 346 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 347 ri, ri + core_iaf_ri)); 348 349 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 350 351 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 352 *v = iaf_perfctr_value_to_reload_count(tmp); 353 else 354 *v = tmp; 355 356 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 357 IAF_RI_TO_MSR(ri), *v); 358 359 return (0); 360} 361 362static int 363iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 364{ 365 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 366 367 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 368 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 369 KASSERT(ri >= 0 && ri < core_iaf_npmc, 370 ("[core,%d] illegal row-index %d", __LINE__, ri)); 371 372 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 373 ("[core,%d] PHW pmc non-NULL", __LINE__)); 374 375 return (0); 376} 377 378static int 379iaf_start_pmc(int cpu, int ri) 380{ 381 struct pmc *pm; 382 struct core_cpu *iafc; 383 uint64_t msr = 0; 384 385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 386 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 387 KASSERT(ri >= 0 && ri < core_iaf_npmc, 388 ("[core,%d] illegal row-index %d", __LINE__, ri)); 389 390 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 391 392 iafc = core_pcpu[cpu]; 393 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 394 395 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 396 397 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 398 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 399 400 do { 401 iafc->pc_resync = 0; 402 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 403 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 404 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 405 IAF_GLOBAL_CTRL_MASK)); 406 } while (iafc->pc_resync != 0); 407 408 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 409 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 410 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 411 412 return (0); 413} 414 415static int 416iaf_stop_pmc(int cpu, int ri) 417{ 418 uint32_t fc; 419 struct core_cpu *iafc; 420 uint64_t msr = 0; 421 422 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 423 424 iafc = core_pcpu[cpu]; 425 426 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 427 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 428 KASSERT(ri >= 0 && ri < core_iaf_npmc, 429 ("[core,%d] illegal row-index %d", __LINE__, ri)); 430 431 fc = (IAF_MASK << (ri * 4)); 432 433 if (core_cputype != PMC_CPU_INTEL_ATOM) 434 fc &= ~IAF_ANY; 435 436 iafc->pc_iafctrl &= ~fc; 437 438 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 439 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 440 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 441 442 do { 443 iafc->pc_resync = 0; 444 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 445 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 446 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 447 IAF_GLOBAL_CTRL_MASK)); 448 } while (iafc->pc_resync != 0); 449 450 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 451 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 452 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 453 454 return (0); 455} 456 457static int 458iaf_write_pmc(int cpu, int ri, pmc_value_t v) 459{ 460 struct core_cpu *cc; 461 struct pmc *pm; 462 uint64_t msr; 463 464 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 465 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 466 KASSERT(ri >= 0 && ri < core_iaf_npmc, 467 ("[core,%d] illegal row-index %d", __LINE__, ri)); 468 469 cc = core_pcpu[cpu]; 470 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 471 472 KASSERT(pm, 473 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 474 475 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 476 v = iaf_reload_count_to_perfctr_value(v); 477 478 /* Turn off fixed counters */ 479 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 480 wrmsr(IAF_CTRL, msr); 481 482 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 483 484 /* Turn on fixed counters */ 485 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 486 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 487 488 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 489 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 490 (uintmax_t) rdmsr(IAF_CTRL), 491 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 492 493 return (0); 494} 495 496 497static void 498iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 499{ 500 struct pmc_classdep *pcd; 501 502 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 503 504 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 505 506 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 507 508 pcd->pcd_caps = IAF_PMC_CAPS; 509 pcd->pcd_class = PMC_CLASS_IAF; 510 pcd->pcd_num = npmc; 511 pcd->pcd_ri = md->pmd_npmc; 512 pcd->pcd_width = pmcwidth; 513 514 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 515 pcd->pcd_config_pmc = iaf_config_pmc; 516 pcd->pcd_describe = iaf_describe; 517 pcd->pcd_get_config = iaf_get_config; 518 pcd->pcd_get_msr = iaf_get_msr; 519 pcd->pcd_pcpu_fini = core_pcpu_noop; 520 pcd->pcd_pcpu_init = core_pcpu_noop; 521 pcd->pcd_read_pmc = iaf_read_pmc; 522 pcd->pcd_release_pmc = iaf_release_pmc; 523 pcd->pcd_start_pmc = iaf_start_pmc; 524 pcd->pcd_stop_pmc = iaf_stop_pmc; 525 pcd->pcd_write_pmc = iaf_write_pmc; 526 527 md->pmd_npmc += npmc; 528} 529 530/* 531 * Intel programmable PMCs. 532 */ 533 534/* 535 * Event descriptor tables. 536 * 537 * For each event id, we track: 538 * 539 * 1. The CPUs that the event is valid for. 540 * 541 * 2. If the event uses a fixed UMASK, the value of the umask field. 542 * If the event doesn't use a fixed UMASK, a mask of legal bits 543 * to check against. 544 */ 545 546struct iap_event_descr { 547 enum pmc_event iap_ev; 548 unsigned char iap_evcode; 549 unsigned char iap_umask; 550 unsigned int iap_flags; 551}; 552 553#define IAP_F_CC (1 << 0) /* CPU: Core */ 554#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 555#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 556#define IAP_F_CA (1 << 3) /* CPU: Atom */ 557#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 558#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 559#define IAP_F_WM (1 << 5) /* CPU: Westmere */ 560#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 561#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 562#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 563#define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge */ 564#define IAP_F_HW (1 << 10) /* CPU: Haswell */ 565#define IAP_F_FM (1 << 11) /* Fixed mask */ 566 567#define IAP_F_ALLCPUSCORE2 \ 568 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 569 570/* Sub fields of UMASK that this event supports. */ 571#define IAP_M_CORE (1 << 0) /* Core specificity */ 572#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 573#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 574#define IAP_M_MESI (1 << 3) /* MESI */ 575#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 576#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 577#define IAP_M_TRANSITION (1 << 6) /* Transition */ 578 579#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 580#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 581#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 582#define IAP_F_MESI (0xF << 8) /* MESI */ 583#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 584#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 585#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 586 587#define IAP_PREFETCH_RESERVED (0x2 << 12) 588#define IAP_CORE_THIS (0x1 << 14) 589#define IAP_CORE_ALL (0x3 << 14) 590#define IAP_F_CMASK 0xFF000000 591 592static struct iap_event_descr iap_events[] = { 593#undef IAPDESCR 594#define IAPDESCR(N,EV,UM,FLAGS) { \ 595 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 596 .iap_evcode = (EV), \ 597 .iap_umask = (UM), \ 598 .iap_flags = (FLAGS) \ 599 } 600 601 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 602 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 603 604 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 605 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 606 IAP_F_SBX), 607 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 608 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 609 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 610 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 611 IAP_F_SBX), 612 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 613 IAP_F_SBX), 614 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 615 616 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 617 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 618 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 619 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 620 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 621 622 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 623 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 624 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 625 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB | 626 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 627 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 628 629 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 630 IAP_F_CC2E | IAP_F_CA), 631 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 632 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 633 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 634 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 635 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 636 637 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 638 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 639 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 640 IAP_F_HW), 641 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 642 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 643 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 644 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 645 IAP_F_SBX), 646 647 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 648 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 649 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 650 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 651 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 652 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 653 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 654 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 655 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 656 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 657 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 658 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW), 659 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 660 IAP_F_SBX | IAP_F_HW), 661 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW), 662 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 663 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW), 664 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW), 665 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 666 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 667 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 668 669 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 670 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 671 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 672 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 673 674 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 675 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 676 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 677 678 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 679 IAP_F_WM), 680 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 681 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 682 683 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 684 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 685 686 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 687 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 688 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 689 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 690 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 691 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 692 693 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 694 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 695 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 696 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 697 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 698 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 699 700 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 701 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 702 IAP_F_WM | IAP_F_SB | IAP_F_SBX), 703 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 704 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 705 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 706 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 707 IAP_F_SBX), 708 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 709 IAP_F_SBX), 710 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 711 IAP_F_SBX), 712 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 713 IAP_F_SBX), 714 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 715 716 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 717 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 718 IAP_F_SBX), 719 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 720 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 721 722 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 723 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 724 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 725 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 726 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 727 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 728 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 729 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 731 732 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 733 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 734 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 735 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 736 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 737 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 738 739 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 740 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 741 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 742 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 743 744 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 745 IAP_F_SBX), 746 747 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 748 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 749 750 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 751 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 752 IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 754 755 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 756 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 757 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 758 759 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 761 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 762 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 763 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 764 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 765 766 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 767 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 768 IAP_F_SBX | IAP_F_IBX), 769 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 770 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 771 IAP_F_SBX | IAP_F_IBX), 772 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 773 IAP_F_SBX | IAP_F_IBX), 774 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 775 IAP_F_SBX | IAP_F_IBX), 776 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 777 IAP_F_SBX | IAP_F_IBX), 778 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 779 IAP_F_SBX | IAP_F_IBX), 780 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 781 IAP_F_SBX | IAP_F_IBX), 782 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW), 783 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW), 784 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW), 785 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW), 786 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 787 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 788 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 789 IAP_F_SBX | IAP_F_IBX), 790 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW), 791 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW), 792 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW), 793 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW), 794 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 795 IAP_F_SBX | IAP_F_IBX), 796 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 797 IAP_F_SBX | IAP_F_IBX), 798 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW), 799 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW), 800 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW), 801 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW), 802 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 803 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW), 804 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW), 805 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW), 806 807 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 808 809 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 810 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 811 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 812 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 813 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 814 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 815 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 816 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 817 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 818 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 819 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 820 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 821 822 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 823 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 824 IAP_F_SBX | IAP_F_IBX), 825 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 826 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 827 IAP_F_SBX), 828 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 829 IAP_F_SBX | IAP_F_IBX), 830 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 831 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 832 IAP_F_SBX | IAP_F_IBX), 833 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 834 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 835 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 836 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW), 837 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 838 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 839 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 840 841 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 842 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX | 843 IAP_F_IBX), 844 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 845 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 846 IAP_F_SBX | IAP_F_IBX), 847 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 848 IAP_F_SBX | IAP_F_IBX), 849 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX | 850 IAP_F_IBX), 851 852 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 853 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 854 IAP_F_CA | IAP_F_CC2), 855 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 856 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 857 858 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 859 IAP_F_ALLCPUSCORE2), 860 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 861 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 862 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 863 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 864 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 865 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 866 867 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 868 IAP_F_ALLCPUSCORE2), 869 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 870 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 871 872 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 873 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 874 875 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 876 877 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 878 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 879 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 880 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 881 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 882 883 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 884 885 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 886 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 887 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 888 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 889 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 890 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 891 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 892 893 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 894 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 895 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 896 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 897 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 898 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 899 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 900 901 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 902 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 903 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 904 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 905 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 906 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 907 908 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 909 IAP_F_I7), 910 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 911 IAP_F_CC2 | IAP_F_I7), 912 913 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 914 915 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 916 917 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 918 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 919 920 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 921 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 922 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 923 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 924 925 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 926 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 927 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 928 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 929 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 930 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 931 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 932 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW), 933 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 934 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 935 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW), 936 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 937 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW), 938 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW), 939 940 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 941 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 942 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 943 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 944 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 945 946 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 947 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 948 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 949 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 950 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 951 952 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 953 954 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 955 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 956 IAP_F_SB | IAP_F_SBX), 957 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 958 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 959 960 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 961 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 962 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 963 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 964 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 965 966 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 967 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 968 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 969 IAP_F_SB | IAP_F_SBX), 970 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 971 IAP_F_SB | IAP_F_SBX), 972 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 973 IAP_F_SB | IAP_F_SBX), 974 975 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 976 977 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 978 979 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 980 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 981 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 982 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 983 984 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 985 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 986 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 987 988 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 989 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 990 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 991 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 992 993 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 994 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 995 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 996 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 997 998 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 999 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1000 1001 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB), 1002 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX), 1003 1004 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1005 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1006 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1007 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1008 IAP_F_IBX | IAP_F_HW), 1009 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1010 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1011 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1012 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1013 1014 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1015 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1016 1017 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1018 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1019 1020 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1021 IAP_F_CA | IAP_F_CC2), 1022 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1023 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1024 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1025 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1026 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1027 1028 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1029 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1030 1031 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1032 IAP_F_CA | IAP_F_CC2), 1033 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1034 1035 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1036 1037 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1038 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1039 1040 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1041 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1042 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1043 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1044 1045 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1046 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1047 1048 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1049 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1050 1051 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1052 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1053 1054 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1055 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1056 1057 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1058 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1059 1060 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1061 IAP_F_CA | IAP_F_CC2), 1062 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1063 1064 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1065 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1066 1067 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1068 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1069 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1070 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1071 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1072 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1073 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1074 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1075 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1076 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1077 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1078 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1079 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1080 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1081 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1082 1083 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1084 1085 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1086 1087 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1088 1089 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1090 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1091 1092 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1093 1094 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1095 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1096 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1097 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1098 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1099 IAP_F_WM), 1100 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1101 1102 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1103 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1104 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1105 1106 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1107 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1108 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1109 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1110 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1111 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1112 1113 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1114 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1115 1116 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1117 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1118 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1119 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1120 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1121 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1122 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1123 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW), 1124 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1125 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1126 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 1127 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 1128 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW), 1129 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1130 1131 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1132 1133 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1134 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1135 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1136 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1137 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1138 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1139 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1140 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1141 1142 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1143 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1144 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1145 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1146 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1147 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1148 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1149 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1150 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1151 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1152 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1153 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1154 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1155 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1156 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1157 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1158 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1159 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1160 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1161 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1162 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1163 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1164 1165 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1166 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1167 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1168 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1169 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1170 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1171 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1172 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1173 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1174 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1175 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1176 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1177 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1178 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1179 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1180 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1181 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1182 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1183 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1184 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1185 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1186 1187 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1188 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1189 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1190 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1191 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1192 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1193 1194 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1195 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1196 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1197 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1198 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1199 1200 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1201 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1202 1203 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1204 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1205 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1206 1207 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1208 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1209 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1210 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1211 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1212 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1213 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1214 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1215 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1216 IAP_F_SBX | IAP_F_IBX), 1217 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1218 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1219 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1220 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1221 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1222 IAP_F_SBX | IAP_F_IBX), 1223 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1224 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1225 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1226 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1227 1228 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1229 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1230 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1231 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1232 IAP_F_SB | IAP_F_SBX), 1233 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1234 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1235 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1236 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1237 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1238 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1239 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1240 IAP_F_SB | IAP_F_SBX), 1241 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1242 IAP_F_SB | IAP_F_SBX), 1243 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1244 IAP_F_SB | IAP_F_SBX), 1245 1246 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1247 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1248 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1249 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW), 1250 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW), 1251 1252 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1253 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1254 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1255 1256 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1257 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1258 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1259 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1260 1261 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1262 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1263 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1264 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1265 1266 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1267 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1268 IAP_F_SBX | IAP_F_IBX), 1269 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1270 1271 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1272 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1273 1274 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1275 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1276 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1277 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1278 IAP_F_IBX | IAP_F_HW), 1279 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1280 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1281 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1282 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1283 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1284 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1285 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1286 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1287 1288 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1289 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1290 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1291 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1292 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1293 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1294 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1295 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1296 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1297 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1298 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1299 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1300 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1301 IAP_F_WM), 1302 1303 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1304 IAP_F_SB | IAP_F_SBX), 1305 1306 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1307 IAP_F_WM | IAP_F_I7O), 1308 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1309 IAP_F_WM | IAP_F_I7O), 1310 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1311 IAP_F_WM | IAP_F_I7O), 1312 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1313 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1314 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1315 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1316 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1317 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1318 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1319 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1320 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1321 1322 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1323 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1324 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1325 1326 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1327 1328 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1329 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1330 1331 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1332 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1333 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1334 1335 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1336 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1337 1338 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1339 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1340 1341 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW), 1342 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW), 1343 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW), 1344 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW), 1345 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW), 1346 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW), 1347 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW), 1348 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW), 1349 1350 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1351 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1352 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1353 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1354 1355 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1356 1357 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1358 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1359 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1360 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1361 IAP_F_IBX | IAP_F_HW), 1362 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1363 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1364 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1365 IAP_F_I7 | IAP_F_WM), 1366 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1367 1368 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1369 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1370 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1371 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1372 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1373 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1374 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1375 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1376 IAP_F_SBX | IAP_F_IBX), 1377 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW), 1378 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1379 1380 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1381 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1382 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1383 IAP_F_IBX | IAP_F_HW), 1384 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1385 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1386 IAP_F_IBX | IAP_F_HW), 1387 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1388 IAP_F_I7 | IAP_F_WM), 1389 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1390 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1391 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1392 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1393 1394 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1395 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1396 IAP_F_I7 | IAP_F_WM), 1397 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1398 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1399 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1400 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1401 IAP_F_IBX | IAP_F_HW), 1402 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1403 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1404 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1405 1406 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1407 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1408 IAP_F_IBX | IAP_F_HW), 1409 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1410 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1411 IAP_F_IBX | IAP_F_HW), 1412 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1413 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1414 IAP_F_IBX | IAP_F_HW), 1415 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1416 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1417 IAP_F_IBX | IAP_F_HW), 1418 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1419 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1420 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1421 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1422 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1423 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1424 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1425 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1426 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1427 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1428 1429 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1430 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1431 IAP_F_IBX | IAP_F_HW), 1432 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1433 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1434 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1435 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1436 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1437 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1438 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1439 IAP_F_SBX | IAP_F_IBX), 1440 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1441 IAP_F_SBX | IAP_F_IBX), 1442 1443 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1444 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1445 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1446 1447 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1448 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1449 IAP_F_I7 | IAP_F_WM), 1450 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1451 IAP_F_I7 | IAP_F_WM), 1452 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1453 IAP_F_I7 | IAP_F_WM), 1454 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1455 IAP_F_I7 | IAP_F_WM), 1456 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1457 IAP_F_I7 | IAP_F_WM), 1458 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1459 1460 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1461 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1462 1463 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1464 1465 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1466 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1467 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1468 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1469 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1470 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1471 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1472 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1473 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1474 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1475 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1476 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1477 1478 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1479 IAP_F_I7 | IAP_F_WM), 1480 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1481 IAP_F_I7 | IAP_F_WM), 1482 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1483 IAP_F_I7 | IAP_F_WM), 1484 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1485 IAP_F_I7 | IAP_F_WM), 1486 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1487 IAP_F_WM), 1488 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1489 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1490 1491 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1492 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1493 IAP_F_I7 | IAP_F_WM), 1494 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1495 IAP_F_I7 | IAP_F_WM), 1496 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1497 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1498 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1499 1500 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1501 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1502 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1503 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1504 IAP_F_SBX | IAP_F_IBX), 1505 1506 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1507 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1508 1509 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1510 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1511 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1512 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1513 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1514 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1515 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1516 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1517 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1518 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1519 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1520 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1521 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1522 1523 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1524 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1525 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1526 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1527 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1528 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1529 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1530 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW), 1531 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1532 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1533 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1534 1535 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1536 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1537 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1538 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1539 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1540 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1541 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1542 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1543 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1544 IAP_F_I7 | IAP_F_WM), 1545 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1546 1547 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1548 IAP_F_IBX | IAP_F_HW), 1549 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1550 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX), 1551 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX), 1552 1553 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1554 IAP_F_I7 | IAP_F_WM), 1555 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1556 IAP_F_SB | IAP_F_SBX), 1557 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1558 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1559 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1560 1561 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1562 IAP_F_I7 | IAP_F_WM), 1563 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1564 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1565 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1566 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1567 1568 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1569 1570 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1571 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1572 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1573 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1574 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1575 1576 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1577 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1578 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1579 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1580 1581 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1582 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1583 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1584 1585 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1586 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1587 1588 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1589 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1590 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1591 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1592 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1593 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1594 1595 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1596 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1597 IAP_F_WM), 1598 1599 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1600 1601 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1602 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1603 1604 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1605 1606 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1607 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1608 IAP_F_WM | IAP_F_SBX), 1609 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1610 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IBX | IAP_F_HW), 1611 1612 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1613 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1614 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1615 1616 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1617 1618 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1619 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1620 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1621 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1622 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1623 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1624 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1625 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1626 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1627 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1628 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1629 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1630 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1631 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1632 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1633 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1634 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1635 1636 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1637 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1638 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1639 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1640 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1641 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1642 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1643 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1644 1645 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1646 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1647 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1648 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1649 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1650 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1651 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW), 1652 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW), 1653 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1654 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1655 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1656 IAP_F_IBX), 1657 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1658 1659 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1660 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1661 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1662 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1663 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1664 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1665 1666 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1667 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1668 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1669 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1670 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1671 IAP_F_SB | IAP_F_SBX), 1672 1673 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1674 1675 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1676 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1677 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1678 1679 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1680 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1681 1682 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1683 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1684 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1685 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1686 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1687 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1688 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1689}; 1690 1691static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1692 1693static pmc_value_t 1694iap_perfctr_value_to_reload_count(pmc_value_t v) 1695{ 1696 v &= (1ULL << core_iap_width) - 1; 1697 return (1ULL << core_iap_width) - v; 1698} 1699 1700static pmc_value_t 1701iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1702{ 1703 return (1ULL << core_iap_width) - rlc; 1704} 1705 1706static int 1707iap_pmc_has_overflowed(int ri) 1708{ 1709 uint64_t v; 1710 1711 /* 1712 * We treat a Core (i.e., Intel architecture v1) PMC as has 1713 * having overflowed if its MSB is zero. 1714 */ 1715 v = rdpmc(ri); 1716 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1717} 1718 1719/* 1720 * Check an event against the set of supported architectural events. 1721 * 1722 * Returns 1 if the event is architectural and unsupported on this 1723 * CPU. Returns 0 otherwise. 1724 */ 1725 1726static int 1727iap_architectural_event_is_unsupported(enum pmc_event pe) 1728{ 1729 enum core_arch_events ae; 1730 1731 switch (pe) { 1732 case PMC_EV_IAP_EVENT_3CH_00H: 1733 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1734 break; 1735 case PMC_EV_IAP_EVENT_C0H_00H: 1736 ae = CORE_AE_INSTRUCTION_RETIRED; 1737 break; 1738 case PMC_EV_IAP_EVENT_3CH_01H: 1739 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1740 break; 1741 case PMC_EV_IAP_EVENT_2EH_4FH: 1742 ae = CORE_AE_LLC_REFERENCE; 1743 break; 1744 case PMC_EV_IAP_EVENT_2EH_41H: 1745 ae = CORE_AE_LLC_MISSES; 1746 break; 1747 case PMC_EV_IAP_EVENT_C4H_00H: 1748 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1749 break; 1750 case PMC_EV_IAP_EVENT_C5H_00H: 1751 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1752 break; 1753 1754 default: /* Non architectural event. */ 1755 return (0); 1756 } 1757 1758 return ((core_architectural_events & (1 << ae)) == 0); 1759} 1760 1761static int 1762iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1763{ 1764 uint32_t mask; 1765 1766 switch (pe) { 1767 /* 1768 * Events valid only on counter 0, 1. 1769 */ 1770 case PMC_EV_IAP_EVENT_40H_01H: 1771 case PMC_EV_IAP_EVENT_40H_02H: 1772 case PMC_EV_IAP_EVENT_40H_04H: 1773 case PMC_EV_IAP_EVENT_40H_08H: 1774 case PMC_EV_IAP_EVENT_40H_0FH: 1775 case PMC_EV_IAP_EVENT_41H_02H: 1776 case PMC_EV_IAP_EVENT_41H_04H: 1777 case PMC_EV_IAP_EVENT_41H_08H: 1778 case PMC_EV_IAP_EVENT_42H_01H: 1779 case PMC_EV_IAP_EVENT_42H_02H: 1780 case PMC_EV_IAP_EVENT_42H_04H: 1781 case PMC_EV_IAP_EVENT_42H_08H: 1782 case PMC_EV_IAP_EVENT_43H_01H: 1783 case PMC_EV_IAP_EVENT_43H_02H: 1784 case PMC_EV_IAP_EVENT_51H_01H: 1785 case PMC_EV_IAP_EVENT_51H_02H: 1786 case PMC_EV_IAP_EVENT_51H_04H: 1787 case PMC_EV_IAP_EVENT_51H_08H: 1788 case PMC_EV_IAP_EVENT_63H_01H: 1789 case PMC_EV_IAP_EVENT_63H_02H: 1790 mask = 0x3; 1791 break; 1792 1793 default: 1794 mask = ~0; /* Any row index is ok. */ 1795 } 1796 1797 return (mask & (1 << ri)); 1798} 1799 1800static int 1801iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1802{ 1803 uint32_t mask; 1804 1805 switch (pe) { 1806 /* 1807 * Events valid only on counter 0. 1808 */ 1809 case PMC_EV_IAP_EVENT_60H_01H: 1810 case PMC_EV_IAP_EVENT_60H_02H: 1811 case PMC_EV_IAP_EVENT_60H_04H: 1812 case PMC_EV_IAP_EVENT_60H_08H: 1813 case PMC_EV_IAP_EVENT_B3H_01H: 1814 case PMC_EV_IAP_EVENT_B3H_02H: 1815 case PMC_EV_IAP_EVENT_B3H_04H: 1816 mask = 0x1; 1817 break; 1818 1819 /* 1820 * Events valid only on counter 0, 1. 1821 */ 1822 case PMC_EV_IAP_EVENT_4CH_01H: 1823 case PMC_EV_IAP_EVENT_4EH_01H: 1824 case PMC_EV_IAP_EVENT_4EH_02H: 1825 case PMC_EV_IAP_EVENT_4EH_04H: 1826 case PMC_EV_IAP_EVENT_51H_01H: 1827 case PMC_EV_IAP_EVENT_51H_02H: 1828 case PMC_EV_IAP_EVENT_51H_04H: 1829 case PMC_EV_IAP_EVENT_51H_08H: 1830 case PMC_EV_IAP_EVENT_63H_01H: 1831 case PMC_EV_IAP_EVENT_63H_02H: 1832 mask = 0x3; 1833 break; 1834 1835 default: 1836 mask = ~0; /* Any row index is ok. */ 1837 } 1838 1839 return (mask & (1 << ri)); 1840} 1841 1842static int 1843iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 1844{ 1845 uint32_t mask; 1846 1847 switch (pe) { 1848 /* Events valid only on counter 0. */ 1849 case PMC_EV_IAP_EVENT_B7H_01H: 1850 mask = 0x1; 1851 break; 1852 /* Events valid only on counter 1. */ 1853 case PMC_EV_IAP_EVENT_C0H_01H: 1854 mask = 0x1; 1855 break; 1856 /* Events valid only on counter 2. */ 1857 case PMC_EV_IAP_EVENT_48H_01H: 1858 case PMC_EV_IAP_EVENT_A2H_02H: 1859 mask = 0x4; 1860 break; 1861 /* Events valid only on counter 3. */ 1862 case PMC_EV_IAP_EVENT_A3H_08H: 1863 case PMC_EV_IAP_EVENT_BBH_01H: 1864 case PMC_EV_IAP_EVENT_CDH_01H: 1865 case PMC_EV_IAP_EVENT_CDH_02H: 1866 mask = 0x8; 1867 break; 1868 default: 1869 mask = ~0; /* Any row index is ok. */ 1870 } 1871 1872 return (mask & (1 << ri)); 1873} 1874 1875static int 1876iap_event_ok_on_counter(enum pmc_event pe, int ri) 1877{ 1878 uint32_t mask; 1879 1880 switch (pe) { 1881 /* 1882 * Events valid only on counter 0. 1883 */ 1884 case PMC_EV_IAP_EVENT_10H_00H: 1885 case PMC_EV_IAP_EVENT_14H_00H: 1886 case PMC_EV_IAP_EVENT_18H_00H: 1887 case PMC_EV_IAP_EVENT_B3H_01H: 1888 case PMC_EV_IAP_EVENT_B3H_02H: 1889 case PMC_EV_IAP_EVENT_B3H_04H: 1890 case PMC_EV_IAP_EVENT_C1H_00H: 1891 case PMC_EV_IAP_EVENT_CBH_01H: 1892 case PMC_EV_IAP_EVENT_CBH_02H: 1893 mask = (1 << 0); 1894 break; 1895 1896 /* 1897 * Events valid only on counter 1. 1898 */ 1899 case PMC_EV_IAP_EVENT_11H_00H: 1900 case PMC_EV_IAP_EVENT_12H_00H: 1901 case PMC_EV_IAP_EVENT_13H_00H: 1902 mask = (1 << 1); 1903 break; 1904 1905 default: 1906 mask = ~0; /* Any row index is ok. */ 1907 } 1908 1909 return (mask & (1 << ri)); 1910} 1911 1912static int 1913iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1914 const struct pmc_op_pmcallocate *a) 1915{ 1916 int n, model; 1917 enum pmc_event ev; 1918 struct iap_event_descr *ie; 1919 uint32_t c, caps, config, cpuflag, evsel, mask; 1920 1921 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1922 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1923 KASSERT(ri >= 0 && ri < core_iap_npmc, 1924 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1925 1926 /* check requested capabilities */ 1927 caps = a->pm_caps; 1928 if ((IAP_PMC_CAPS & caps) != caps) 1929 return (EPERM); 1930 1931 ev = pm->pm_event; 1932 1933 if (iap_architectural_event_is_unsupported(ev)) 1934 return (EOPNOTSUPP); 1935 1936 /* 1937 * A small number of events are not supported in all the 1938 * processors based on a given microarchitecture. 1939 */ 1940 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 1941 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 1942 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 1943 return (EINVAL); 1944 } 1945 1946 switch (core_cputype) { 1947 case PMC_CPU_INTEL_COREI7: 1948 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1949 return (EINVAL); 1950 break; 1951 case PMC_CPU_INTEL_SANDYBRIDGE: 1952 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 1953 case PMC_CPU_INTEL_IVYBRIDGE: 1954 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 1955 case PMC_CPU_INTEL_HASWELL: 1956 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 1957 return (EINVAL); 1958 break; 1959 case PMC_CPU_INTEL_WESTMERE: 1960 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1961 return (EINVAL); 1962 break; 1963 default: 1964 if (iap_event_ok_on_counter(ev, ri) == 0) 1965 return (EINVAL); 1966 } 1967 1968 /* 1969 * Look for an event descriptor with matching CPU and event id 1970 * fields. 1971 */ 1972 1973 switch (core_cputype) { 1974 default: 1975 case PMC_CPU_INTEL_ATOM: 1976 cpuflag = IAP_F_CA; 1977 break; 1978 case PMC_CPU_INTEL_CORE: 1979 cpuflag = IAP_F_CC; 1980 break; 1981 case PMC_CPU_INTEL_CORE2: 1982 cpuflag = IAP_F_CC2; 1983 break; 1984 case PMC_CPU_INTEL_CORE2EXTREME: 1985 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1986 break; 1987 case PMC_CPU_INTEL_COREI7: 1988 cpuflag = IAP_F_I7; 1989 break; 1990 case PMC_CPU_INTEL_HASWELL: 1991 cpuflag = IAP_F_HW; 1992 break; 1993 case PMC_CPU_INTEL_IVYBRIDGE: 1994 cpuflag = IAP_F_IB; 1995 break; 1996 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 1997 cpuflag = IAP_F_IBX; 1998 break; 1999 case PMC_CPU_INTEL_SANDYBRIDGE: 2000 cpuflag = IAP_F_SB; 2001 break; 2002 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2003 cpuflag = IAP_F_SBX; 2004 break; 2005 case PMC_CPU_INTEL_WESTMERE: 2006 cpuflag = IAP_F_WM; 2007 break; 2008 } 2009 2010 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 2011 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2012 break; 2013 2014 if (n == niap_events) 2015 return (EINVAL); 2016 2017 /* 2018 * A matching event descriptor has been found, so start 2019 * assembling the contents of the event select register. 2020 */ 2021 evsel = ie->iap_evcode; 2022 2023 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2024 2025 /* 2026 * If the event uses a fixed umask value, reject any umask 2027 * bits set by the user. 2028 */ 2029 if (ie->iap_flags & IAP_F_FM) { 2030 2031 if (IAP_UMASK(config) != 0) 2032 return (EINVAL); 2033 2034 evsel |= (ie->iap_umask << 8); 2035 2036 } else { 2037 2038 /* 2039 * Otherwise, the UMASK value needs to be taken from 2040 * the MD fields of the allocation request. Reject 2041 * requests that specify reserved bits. 2042 */ 2043 2044 mask = 0; 2045 2046 if (ie->iap_umask & IAP_M_CORE) { 2047 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2048 c != IAP_CORE_THIS) 2049 return (EINVAL); 2050 mask |= IAP_F_CORE; 2051 } 2052 2053 if (ie->iap_umask & IAP_M_AGENT) 2054 mask |= IAP_F_AGENT; 2055 2056 if (ie->iap_umask & IAP_M_PREFETCH) { 2057 2058 if ((c = (config & IAP_F_PREFETCH)) == 2059 IAP_PREFETCH_RESERVED) 2060 return (EINVAL); 2061 2062 mask |= IAP_F_PREFETCH; 2063 } 2064 2065 if (ie->iap_umask & IAP_M_MESI) 2066 mask |= IAP_F_MESI; 2067 2068 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2069 mask |= IAP_F_SNOOPRESPONSE; 2070 2071 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2072 mask |= IAP_F_SNOOPTYPE; 2073 2074 if (ie->iap_umask & IAP_M_TRANSITION) 2075 mask |= IAP_F_TRANSITION; 2076 2077 /* 2078 * If bits outside of the allowed set of umask bits 2079 * are set, reject the request. 2080 */ 2081 if (config & ~mask) 2082 return (EINVAL); 2083 2084 evsel |= (config & mask); 2085 2086 } 2087 2088 /* 2089 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2090 */ 2091 if (core_cputype == PMC_CPU_INTEL_ATOM || 2092 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2093 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2094 evsel |= (config & IAP_ANY); 2095 else if (config & IAP_ANY) 2096 return (EINVAL); 2097 2098 /* 2099 * Check offcore response configuration. 2100 */ 2101 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2102 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2103 ev != PMC_EV_IAP_EVENT_BBH_01H) 2104 return (EINVAL); 2105 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2106 ev == PMC_EV_IAP_EVENT_BBH_01H) 2107 return (EINVAL); 2108 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2109 core_cputype == PMC_CPU_INTEL_WESTMERE) && 2110 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2111 return (EINVAL); 2112 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2113 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2114 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2115 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2116 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2117 return (EINVAL); 2118 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2119 } 2120 2121 if (caps & PMC_CAP_THRESHOLD) 2122 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2123 if (caps & PMC_CAP_USER) 2124 evsel |= IAP_USR; 2125 if (caps & PMC_CAP_SYSTEM) 2126 evsel |= IAP_OS; 2127 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2128 evsel |= (IAP_OS | IAP_USR); 2129 if (caps & PMC_CAP_EDGE) 2130 evsel |= IAP_EDGE; 2131 if (caps & PMC_CAP_INVERT) 2132 evsel |= IAP_INV; 2133 if (caps & PMC_CAP_INTERRUPT) 2134 evsel |= IAP_INT; 2135 2136 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2137 2138 return (0); 2139} 2140 2141static int 2142iap_config_pmc(int cpu, int ri, struct pmc *pm) 2143{ 2144 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2145 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2146 2147 KASSERT(ri >= 0 && ri < core_iap_npmc, 2148 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2149 2150 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2151 2152 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2153 cpu)); 2154 2155 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2156 2157 return (0); 2158} 2159 2160static int 2161iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2162{ 2163 int error; 2164 struct pmc_hw *phw; 2165 char iap_name[PMC_NAME_MAX]; 2166 2167 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2168 2169 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2170 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2171 NULL)) != 0) 2172 return (error); 2173 2174 pi->pm_class = PMC_CLASS_IAP; 2175 2176 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2177 pi->pm_enabled = TRUE; 2178 *ppmc = phw->phw_pmc; 2179 } else { 2180 pi->pm_enabled = FALSE; 2181 *ppmc = NULL; 2182 } 2183 2184 return (0); 2185} 2186 2187static int 2188iap_get_config(int cpu, int ri, struct pmc **ppm) 2189{ 2190 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2191 2192 return (0); 2193} 2194 2195static int 2196iap_get_msr(int ri, uint32_t *msr) 2197{ 2198 KASSERT(ri >= 0 && ri < core_iap_npmc, 2199 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2200 2201 *msr = ri; 2202 2203 return (0); 2204} 2205 2206static int 2207iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2208{ 2209 struct pmc *pm; 2210 pmc_value_t tmp; 2211 2212 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2213 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2214 KASSERT(ri >= 0 && ri < core_iap_npmc, 2215 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2216 2217 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2218 2219 KASSERT(pm, 2220 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2221 ri)); 2222 2223 tmp = rdpmc(ri); 2224 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2225 *v = iap_perfctr_value_to_reload_count(tmp); 2226 else 2227 *v = tmp & ((1ULL << core_iap_width) - 1); 2228 2229 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2230 ri, *v); 2231 2232 return (0); 2233} 2234 2235static int 2236iap_release_pmc(int cpu, int ri, struct pmc *pm) 2237{ 2238 (void) pm; 2239 2240 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2241 pm); 2242 2243 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2244 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2245 KASSERT(ri >= 0 && ri < core_iap_npmc, 2246 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2247 2248 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2249 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2250 2251 return (0); 2252} 2253 2254static int 2255iap_start_pmc(int cpu, int ri) 2256{ 2257 struct pmc *pm; 2258 uint32_t evsel; 2259 struct core_cpu *cc; 2260 2261 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2262 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2263 KASSERT(ri >= 0 && ri < core_iap_npmc, 2264 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2265 2266 cc = core_pcpu[cpu]; 2267 pm = cc->pc_corepmcs[ri].phw_pmc; 2268 2269 KASSERT(pm, 2270 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2271 __LINE__, cpu, ri)); 2272 2273 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2274 2275 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2276 2277 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2278 cpu, ri, IAP_EVSEL0 + ri, evsel); 2279 2280 /* Event specific configuration. */ 2281 switch (pm->pm_event) { 2282 case PMC_EV_IAP_EVENT_B7H_01H: 2283 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2284 break; 2285 case PMC_EV_IAP_EVENT_BBH_01H: 2286 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2287 break; 2288 default: 2289 break; 2290 } 2291 2292 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2293 2294 if (core_cputype == PMC_CPU_INTEL_CORE) 2295 return (0); 2296 2297 do { 2298 cc->pc_resync = 0; 2299 cc->pc_globalctrl |= (1ULL << ri); 2300 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2301 } while (cc->pc_resync != 0); 2302 2303 return (0); 2304} 2305 2306static int 2307iap_stop_pmc(int cpu, int ri) 2308{ 2309 struct pmc *pm; 2310 struct core_cpu *cc; 2311 uint64_t msr; 2312 2313 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2314 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2315 KASSERT(ri >= 0 && ri < core_iap_npmc, 2316 ("[core,%d] illegal row index %d", __LINE__, ri)); 2317 2318 cc = core_pcpu[cpu]; 2319 pm = cc->pc_corepmcs[ri].phw_pmc; 2320 2321 KASSERT(pm, 2322 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2323 cpu, ri)); 2324 2325 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2326 2327 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2328 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2329 2330 if (core_cputype == PMC_CPU_INTEL_CORE) 2331 return (0); 2332 2333 msr = 0; 2334 do { 2335 cc->pc_resync = 0; 2336 cc->pc_globalctrl &= ~(1ULL << ri); 2337 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2338 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2339 } while (cc->pc_resync != 0); 2340 2341 return (0); 2342} 2343 2344static int 2345iap_write_pmc(int cpu, int ri, pmc_value_t v) 2346{ 2347 struct pmc *pm; 2348 struct core_cpu *cc; 2349 2350 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2351 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2352 KASSERT(ri >= 0 && ri < core_iap_npmc, 2353 ("[core,%d] illegal row index %d", __LINE__, ri)); 2354 2355 cc = core_pcpu[cpu]; 2356 pm = cc->pc_corepmcs[ri].phw_pmc; 2357 2358 KASSERT(pm, 2359 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2360 cpu, ri)); 2361 2362 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2363 IAP_PMC0 + ri, v); 2364 2365 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2366 v = iap_reload_count_to_perfctr_value(v); 2367 2368 /* 2369 * Write the new value to the counter. The counter will be in 2370 * a stopped state when the pcd_write() entry point is called. 2371 */ 2372 2373 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2374 2375 return (0); 2376} 2377 2378 2379static void 2380iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2381 int flags) 2382{ 2383 struct pmc_classdep *pcd; 2384 2385 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2386 2387 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2388 2389 /* Remember the set of architectural events supported. */ 2390 core_architectural_events = ~flags; 2391 2392 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2393 2394 pcd->pcd_caps = IAP_PMC_CAPS; 2395 pcd->pcd_class = PMC_CLASS_IAP; 2396 pcd->pcd_num = npmc; 2397 pcd->pcd_ri = md->pmd_npmc; 2398 pcd->pcd_width = pmcwidth; 2399 2400 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2401 pcd->pcd_config_pmc = iap_config_pmc; 2402 pcd->pcd_describe = iap_describe; 2403 pcd->pcd_get_config = iap_get_config; 2404 pcd->pcd_get_msr = iap_get_msr; 2405 pcd->pcd_pcpu_fini = core_pcpu_fini; 2406 pcd->pcd_pcpu_init = core_pcpu_init; 2407 pcd->pcd_read_pmc = iap_read_pmc; 2408 pcd->pcd_release_pmc = iap_release_pmc; 2409 pcd->pcd_start_pmc = iap_start_pmc; 2410 pcd->pcd_stop_pmc = iap_stop_pmc; 2411 pcd->pcd_write_pmc = iap_write_pmc; 2412 2413 md->pmd_npmc += npmc; 2414} 2415 2416static int 2417core_intr(int cpu, struct trapframe *tf) 2418{ 2419 pmc_value_t v; 2420 struct pmc *pm; 2421 struct core_cpu *cc; 2422 int error, found_interrupt, ri; 2423 uint64_t msr; 2424 2425 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2426 TRAPF_USERMODE(tf)); 2427 2428 found_interrupt = 0; 2429 cc = core_pcpu[cpu]; 2430 2431 for (ri = 0; ri < core_iap_npmc; ri++) { 2432 2433 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2434 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2435 continue; 2436 2437 if (!iap_pmc_has_overflowed(ri)) 2438 continue; 2439 2440 found_interrupt = 1; 2441 2442 if (pm->pm_state != PMC_STATE_RUNNING) 2443 continue; 2444 2445 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2446 TRAPF_USERMODE(tf)); 2447 2448 v = pm->pm_sc.pm_reloadcount; 2449 v = iaf_reload_count_to_perfctr_value(v); 2450 2451 /* 2452 * Stop the counter, reload it but only restart it if 2453 * the PMC is not stalled. 2454 */ 2455 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2456 wrmsr(IAP_EVSEL0 + ri, msr); 2457 wrmsr(IAP_PMC0 + ri, v); 2458 2459 if (error) 2460 continue; 2461 2462 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2463 IAP_EN)); 2464 } 2465 2466 if (found_interrupt) 2467 lapic_reenable_pmc(); 2468 2469 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2470 &pmc_stats.pm_intr_ignored, 1); 2471 2472 return (found_interrupt); 2473} 2474 2475static int 2476core2_intr(int cpu, struct trapframe *tf) 2477{ 2478 int error, found_interrupt, n; 2479 uint64_t flag, intrstatus, intrenable, msr; 2480 struct pmc *pm; 2481 struct core_cpu *cc; 2482 pmc_value_t v; 2483 2484 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2485 TRAPF_USERMODE(tf)); 2486 2487 /* 2488 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2489 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2490 * the current set of interrupting PMCs and process these 2491 * after stopping them. 2492 */ 2493 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2494 intrenable = intrstatus & core_pmcmask; 2495 2496 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2497 (uintmax_t) intrstatus); 2498 2499 found_interrupt = 0; 2500 cc = core_pcpu[cpu]; 2501 2502 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2503 2504 cc->pc_globalctrl &= ~intrenable; 2505 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2506 2507 /* 2508 * Stop PMCs and clear overflow status bits. 2509 */ 2510 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2511 wrmsr(IA_GLOBAL_CTRL, msr); 2512 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2513 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2514 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2515 2516 /* 2517 * Look for interrupts from fixed function PMCs. 2518 */ 2519 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2520 n++, flag <<= 1) { 2521 2522 if ((intrstatus & flag) == 0) 2523 continue; 2524 2525 found_interrupt = 1; 2526 2527 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2528 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2529 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2530 continue; 2531 2532 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2533 TRAPF_USERMODE(tf)); 2534 if (error) 2535 intrenable &= ~flag; 2536 2537 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2538 2539 /* Reload sampling count. */ 2540 wrmsr(IAF_CTR0 + n, v); 2541 2542 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2543 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2544 } 2545 2546 /* 2547 * Process interrupts from the programmable counters. 2548 */ 2549 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2550 if ((intrstatus & flag) == 0) 2551 continue; 2552 2553 found_interrupt = 1; 2554 2555 pm = cc->pc_corepmcs[n].phw_pmc; 2556 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2557 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2558 continue; 2559 2560 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2561 TRAPF_USERMODE(tf)); 2562 if (error) 2563 intrenable &= ~flag; 2564 2565 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2566 2567 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2568 (uintmax_t) v); 2569 2570 /* Reload sampling count. */ 2571 wrmsr(IAP_PMC0 + n, v); 2572 } 2573 2574 /* 2575 * Reenable all non-stalled PMCs. 2576 */ 2577 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2578 (uintmax_t) intrenable); 2579 2580 cc->pc_globalctrl |= intrenable; 2581 2582 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2583 2584 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2585 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2586 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2587 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2588 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2589 2590 if (found_interrupt) 2591 lapic_reenable_pmc(); 2592 2593 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2594 &pmc_stats.pm_intr_ignored, 1); 2595 2596 return (found_interrupt); 2597} 2598 2599int 2600pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2601{ 2602 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2603 int ipa_version, flags, nflags; 2604 2605 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2606 2607 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2608 2609 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2610 md->pmd_cputype, maxcpu, ipa_version); 2611 2612 if (ipa_version < 1 || ipa_version > 3) { 2613 /* Unknown PMC architecture. */ 2614 printf("hwpc_core: unknown PMC architecture: %d\n", 2615 ipa_version); 2616 return (EPROGMISMATCH); 2617 } 2618 2619 core_cputype = md->pmd_cputype; 2620 2621 core_pmcmask = 0; 2622 2623 /* 2624 * Initialize programmable counters. 2625 */ 2626 KASSERT(ipa_version >= 1, 2627 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2628 2629 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2630 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2631 2632 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2633 2634 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2635 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2636 2637 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2638 2639 /* 2640 * Initialize fixed function counters, if present. 2641 */ 2642 if (core_cputype != PMC_CPU_INTEL_CORE) { 2643 KASSERT(ipa_version >= 2, 2644 ("[core,%d] ipa_version %d too small", __LINE__, 2645 ipa_version)); 2646 2647 core_iaf_ri = core_iap_npmc; 2648 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2649 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2650 2651 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2652 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2653 } 2654 2655 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2656 core_iaf_ri); 2657 2658 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2659 M_ZERO | M_WAITOK); 2660 2661 /* 2662 * Choose the appropriate interrupt handler. 2663 */ 2664 if (ipa_version == 1) 2665 md->pmd_intr = core_intr; 2666 else 2667 md->pmd_intr = core2_intr; 2668 2669 md->pmd_pcpu_fini = NULL; 2670 md->pmd_pcpu_init = NULL; 2671 2672 return (0); 2673} 2674 2675void 2676pmc_core_finalize(struct pmc_mdep *md) 2677{ 2678 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2679 2680 free(core_pcpu, M_PMC); 2681 core_pcpu = NULL; 2682} 2683