hwpmc_core.c revision 241738
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 241738 2012-10-19 17:01:27Z sbruno $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#include <machine/apicvar.h> 42#include <machine/cpu.h> 43#include <machine/cpufunc.h> 44#include <machine/md_var.h> 45#include <machine/specialreg.h> 46 47#define CORE_CPUID_REQUEST 0xA 48#define CORE_CPUID_REQUEST_SIZE 0x4 49#define CORE_CPUID_EAX 0x0 50#define CORE_CPUID_EBX 0x1 51#define CORE_CPUID_ECX 0x2 52#define CORE_CPUID_EDX 0x3 53 54#define IAF_PMC_CAPS \ 55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 56 PMC_CAP_USER | PMC_CAP_SYSTEM) 57#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 58 59#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 62 63/* 64 * "Architectural" events defined by Intel. The values of these 65 * symbols correspond to positions in the bitmask returned by 66 * the CPUID.0AH instruction. 67 */ 68enum core_arch_events { 69 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 70 CORE_AE_BRANCH_MISSES_RETIRED = 6, 71 CORE_AE_INSTRUCTION_RETIRED = 1, 72 CORE_AE_LLC_MISSES = 4, 73 CORE_AE_LLC_REFERENCE = 3, 74 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 75 CORE_AE_UNHALTED_CORE_CYCLES = 0 76}; 77 78static enum pmc_cputype core_cputype; 79 80struct core_cpu { 81 volatile uint32_t pc_resync; 82 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 83 volatile uint64_t pc_globalctrl; /* Global control register. */ 84 struct pmc_hw pc_corepmcs[]; 85}; 86 87static struct core_cpu **core_pcpu; 88 89static uint32_t core_architectural_events; 90static uint64_t core_pmcmask; 91 92static int core_iaf_ri; /* relative index of fixed counters */ 93static int core_iaf_width; 94static int core_iaf_npmc; 95 96static int core_iap_width; 97static int core_iap_npmc; 98 99static int 100core_pcpu_noop(struct pmc_mdep *md, int cpu) 101{ 102 (void) md; 103 (void) cpu; 104 return (0); 105} 106 107static int 108core_pcpu_init(struct pmc_mdep *md, int cpu) 109{ 110 struct pmc_cpu *pc; 111 struct core_cpu *cc; 112 struct pmc_hw *phw; 113 int core_ri, n, npmc; 114 115 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 116 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 117 118 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 119 120 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 121 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 122 123 if (core_cputype != PMC_CPU_INTEL_CORE) 124 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 125 126 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 127 M_PMC, M_WAITOK | M_ZERO); 128 129 core_pcpu[cpu] = cc; 130 pc = pmc_pcpu[cpu]; 131 132 KASSERT(pc != NULL && cc != NULL, 133 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 134 135 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 136 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 137 PMC_PHW_CPU_TO_STATE(cpu) | 138 PMC_PHW_INDEX_TO_STATE(n + core_ri); 139 phw->phw_pmc = NULL; 140 pc->pc_hwpmcs[n + core_ri] = phw; 141 } 142 143 return (0); 144} 145 146static int 147core_pcpu_fini(struct pmc_mdep *md, int cpu) 148{ 149 int core_ri, n, npmc; 150 struct pmc_cpu *pc; 151 struct core_cpu *cc; 152 uint64_t msr = 0; 153 154 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 155 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 156 157 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 158 159 if ((cc = core_pcpu[cpu]) == NULL) 160 return (0); 161 162 core_pcpu[cpu] = NULL; 163 164 pc = pmc_pcpu[cpu]; 165 166 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 167 cpu)); 168 169 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 170 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 171 172 for (n = 0; n < npmc; n++) { 173 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 174 wrmsr(IAP_EVSEL0 + n, msr); 175 } 176 177 if (core_cputype != PMC_CPU_INTEL_CORE) { 178 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 179 wrmsr(IAF_CTRL, msr); 180 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 181 } 182 183 for (n = 0; n < npmc; n++) 184 pc->pc_hwpmcs[n + core_ri] = NULL; 185 186 free(cc, M_PMC); 187 188 return (0); 189} 190 191/* 192 * Fixed function counters. 193 */ 194 195static pmc_value_t 196iaf_perfctr_value_to_reload_count(pmc_value_t v) 197{ 198 v &= (1ULL << core_iaf_width) - 1; 199 return (1ULL << core_iaf_width) - v; 200} 201 202static pmc_value_t 203iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 204{ 205 return (1ULL << core_iaf_width) - rlc; 206} 207 208static int 209iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 210 const struct pmc_op_pmcallocate *a) 211{ 212 enum pmc_event ev; 213 uint32_t caps, flags, validflags; 214 215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 216 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 217 218 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 219 220 if (ri < 0 || ri > core_iaf_npmc) 221 return (EINVAL); 222 223 caps = a->pm_caps; 224 225 if (a->pm_class != PMC_CLASS_IAF || 226 (caps & IAF_PMC_CAPS) != caps) 227 return (EINVAL); 228 229 ev = pm->pm_event; 230 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 231 return (EINVAL); 232 233 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 234 return (EINVAL); 235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 236 return (EINVAL); 237 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 238 return (EINVAL); 239 240 flags = a->pm_md.pm_iaf.pm_iaf_flags; 241 242 validflags = IAF_MASK; 243 244 if (core_cputype != PMC_CPU_INTEL_ATOM) 245 validflags &= ~IAF_ANY; 246 247 if ((flags & ~validflags) != 0) 248 return (EINVAL); 249 250 if (caps & PMC_CAP_INTERRUPT) 251 flags |= IAF_PMI; 252 if (caps & PMC_CAP_SYSTEM) 253 flags |= IAF_OS; 254 if (caps & PMC_CAP_USER) 255 flags |= IAF_USR; 256 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 257 flags |= (IAF_OS | IAF_USR); 258 259 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 260 261 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 262 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 263 264 return (0); 265} 266 267static int 268iaf_config_pmc(int cpu, int ri, struct pmc *pm) 269{ 270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 271 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 272 273 KASSERT(ri >= 0 && ri < core_iaf_npmc, 274 ("[core,%d] illegal row-index %d", __LINE__, ri)); 275 276 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 277 278 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 279 cpu)); 280 281 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 282 283 return (0); 284} 285 286static int 287iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 288{ 289 int error; 290 struct pmc_hw *phw; 291 char iaf_name[PMC_NAME_MAX]; 292 293 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 294 295 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 296 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 297 NULL)) != 0) 298 return (error); 299 300 pi->pm_class = PMC_CLASS_IAF; 301 302 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 303 pi->pm_enabled = TRUE; 304 *ppmc = phw->phw_pmc; 305 } else { 306 pi->pm_enabled = FALSE; 307 *ppmc = NULL; 308 } 309 310 return (0); 311} 312 313static int 314iaf_get_config(int cpu, int ri, struct pmc **ppm) 315{ 316 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 317 318 return (0); 319} 320 321static int 322iaf_get_msr(int ri, uint32_t *msr) 323{ 324 KASSERT(ri >= 0 && ri < core_iaf_npmc, 325 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 326 327 *msr = IAF_RI_TO_MSR(ri); 328 329 return (0); 330} 331 332static int 333iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 334{ 335 struct pmc *pm; 336 pmc_value_t tmp; 337 338 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 339 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 340 KASSERT(ri >= 0 && ri < core_iaf_npmc, 341 ("[core,%d] illegal row-index %d", __LINE__, ri)); 342 343 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 344 345 KASSERT(pm, 346 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 347 ri, ri + core_iaf_ri)); 348 349 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 350 351 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 352 *v = iaf_perfctr_value_to_reload_count(tmp); 353 else 354 *v = tmp; 355 356 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 357 IAF_RI_TO_MSR(ri), *v); 358 359 return (0); 360} 361 362static int 363iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 364{ 365 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 366 367 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 368 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 369 KASSERT(ri >= 0 && ri < core_iaf_npmc, 370 ("[core,%d] illegal row-index %d", __LINE__, ri)); 371 372 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 373 ("[core,%d] PHW pmc non-NULL", __LINE__)); 374 375 return (0); 376} 377 378static int 379iaf_start_pmc(int cpu, int ri) 380{ 381 struct pmc *pm; 382 struct core_cpu *iafc; 383 uint64_t msr = 0; 384 385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 386 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 387 KASSERT(ri >= 0 && ri < core_iaf_npmc, 388 ("[core,%d] illegal row-index %d", __LINE__, ri)); 389 390 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 391 392 iafc = core_pcpu[cpu]; 393 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 394 395 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 396 397 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 398 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 399 400 do { 401 iafc->pc_resync = 0; 402 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 403 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 404 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 405 IAF_GLOBAL_CTRL_MASK)); 406 } while (iafc->pc_resync != 0); 407 408 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 409 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 410 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 411 412 return (0); 413} 414 415static int 416iaf_stop_pmc(int cpu, int ri) 417{ 418 uint32_t fc; 419 struct core_cpu *iafc; 420 uint64_t msr = 0; 421 422 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 423 424 iafc = core_pcpu[cpu]; 425 426 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 427 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 428 KASSERT(ri >= 0 && ri < core_iaf_npmc, 429 ("[core,%d] illegal row-index %d", __LINE__, ri)); 430 431 fc = (IAF_MASK << (ri * 4)); 432 433 if (core_cputype != PMC_CPU_INTEL_ATOM) 434 fc &= ~IAF_ANY; 435 436 iafc->pc_iafctrl &= ~fc; 437 438 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 439 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 440 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 441 442 do { 443 iafc->pc_resync = 0; 444 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 445 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 446 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 447 IAF_GLOBAL_CTRL_MASK)); 448 } while (iafc->pc_resync != 0); 449 450 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 451 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 452 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 453 454 return (0); 455} 456 457static int 458iaf_write_pmc(int cpu, int ri, pmc_value_t v) 459{ 460 struct core_cpu *cc; 461 struct pmc *pm; 462 uint64_t msr; 463 464 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 465 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 466 KASSERT(ri >= 0 && ri < core_iaf_npmc, 467 ("[core,%d] illegal row-index %d", __LINE__, ri)); 468 469 cc = core_pcpu[cpu]; 470 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 471 472 KASSERT(pm, 473 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 474 475 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 476 v = iaf_reload_count_to_perfctr_value(v); 477 478 /* Turn off fixed counters */ 479 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 480 wrmsr(IAF_CTRL, msr); 481 482 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 483 484 /* Turn on fixed counters */ 485 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 486 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 487 488 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 489 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 490 (uintmax_t) rdmsr(IAF_CTRL), 491 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 492 493 return (0); 494} 495 496 497static void 498iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 499{ 500 struct pmc_classdep *pcd; 501 502 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 503 504 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 505 506 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 507 508 pcd->pcd_caps = IAF_PMC_CAPS; 509 pcd->pcd_class = PMC_CLASS_IAF; 510 pcd->pcd_num = npmc; 511 pcd->pcd_ri = md->pmd_npmc; 512 pcd->pcd_width = pmcwidth; 513 514 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 515 pcd->pcd_config_pmc = iaf_config_pmc; 516 pcd->pcd_describe = iaf_describe; 517 pcd->pcd_get_config = iaf_get_config; 518 pcd->pcd_get_msr = iaf_get_msr; 519 pcd->pcd_pcpu_fini = core_pcpu_noop; 520 pcd->pcd_pcpu_init = core_pcpu_noop; 521 pcd->pcd_read_pmc = iaf_read_pmc; 522 pcd->pcd_release_pmc = iaf_release_pmc; 523 pcd->pcd_start_pmc = iaf_start_pmc; 524 pcd->pcd_stop_pmc = iaf_stop_pmc; 525 pcd->pcd_write_pmc = iaf_write_pmc; 526 527 md->pmd_npmc += npmc; 528} 529 530/* 531 * Intel programmable PMCs. 532 */ 533 534/* 535 * Event descriptor tables. 536 * 537 * For each event id, we track: 538 * 539 * 1. The CPUs that the event is valid for. 540 * 541 * 2. If the event uses a fixed UMASK, the value of the umask field. 542 * If the event doesn't use a fixed UMASK, a mask of legal bits 543 * to check against. 544 */ 545 546struct iap_event_descr { 547 enum pmc_event iap_ev; 548 unsigned char iap_evcode; 549 unsigned char iap_umask; 550 unsigned int iap_flags; 551}; 552 553#define IAP_F_CC (1 << 0) /* CPU: Core */ 554#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 555#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 556#define IAP_F_CA (1 << 3) /* CPU: Atom */ 557#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 558#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 559#define IAP_F_WM (1 << 5) /* CPU: Westmere */ 560#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 561#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 562#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 563#define IAP_F_FM (1 << 9) /* Fixed mask */ 564 565#define IAP_F_ALLCPUSCORE2 \ 566 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 567 568/* Sub fields of UMASK that this event supports. */ 569#define IAP_M_CORE (1 << 0) /* Core specificity */ 570#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 571#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 572#define IAP_M_MESI (1 << 3) /* MESI */ 573#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 574#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 575#define IAP_M_TRANSITION (1 << 6) /* Transition */ 576 577#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 578#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 579#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 580#define IAP_F_MESI (0xF << 8) /* MESI */ 581#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 582#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 583#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 584 585#define IAP_PREFETCH_RESERVED (0x2 << 12) 586#define IAP_CORE_THIS (0x1 << 14) 587#define IAP_CORE_ALL (0x3 << 14) 588#define IAP_F_CMASK 0xFF000000 589 590static struct iap_event_descr iap_events[] = { 591#undef IAPDESCR 592#define IAPDESCR(N,EV,UM,FLAGS) { \ 593 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 594 .iap_evcode = (EV), \ 595 .iap_umask = (UM), \ 596 .iap_flags = (FLAGS) \ 597 } 598 599 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 600 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 601 602 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 603 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 604 IAP_F_SBX), 605 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 606 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 607 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 608 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 609 IAP_F_SBX), 610 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 611 IAP_F_SBX), 612 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 613 614 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 615 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 616 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 617 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 618 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 619 620 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 621 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 622 IAP_F_SBX), 623 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB | 624 IAP_F_SBX), 625 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 626 627 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 628 IAP_F_CC2E | IAP_F_CA), 629 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 630 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 631 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 632 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 633 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 634 635 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 636 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 637 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 638 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 639 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 640 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 641 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 642 IAP_F_SBX), 643 644 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 645 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), 646 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 647 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), 648 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 649 IAP_F_WM | IAP_F_SB | IAP_F_SBX), 650 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 651 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 652 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 653 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 654 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 655 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 656 IAP_F_SBX), 657 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 658 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), 659 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 660 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB), 661 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB), 662 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB), 663 664 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 665 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 666 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 667 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 668 669 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 670 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 671 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 672 673 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 674 IAP_F_WM), 675 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 676 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 677 678 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 679 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 680 681 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 682 IAP_F_SBX), 683 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 684 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB), 685 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB), 686 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB), 687 688 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 689 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 690 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 691 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 692 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 693 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 694 695 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 696 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 697 IAP_F_WM | IAP_F_SB | IAP_F_SBX), 698 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 699 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 700 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 701 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 702 IAP_F_SBX), 703 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 704 IAP_F_SBX), 705 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 706 IAP_F_SBX), 707 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 708 IAP_F_SBX), 709 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 710 711 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 712 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 713 IAP_F_SBX), 714 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 715 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 716 717 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 718 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 719 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 720 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 721 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 722 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 723 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 724 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 725 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 726 727 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 728 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 729 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 731 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 733 734 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 735 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 736 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 737 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 738 739 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 740 IAP_F_SBX), 741 742 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 743 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 744 745 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 746 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 747 IAP_F_I7 | IAP_F_WM), 748 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 749 750 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 751 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 752 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 753 754 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 755 756 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 757 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 758 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 759 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 760 761 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 762 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 763 IAP_F_SBX), 764 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 765 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 766 IAP_F_SBX), 767 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 768 IAP_F_SBX), 769 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 770 IAP_F_SBX), 771 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 772 IAP_F_SBX), 773 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 774 IAP_F_SBX), 775 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 776 IAP_F_SBX), 777 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 778 IAP_F_SBX), 779 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 780 IAP_F_SBX), 781 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 782 IAP_F_SBX), 783 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 784 IAP_F_SBX), 785 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 786 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 787 788 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 789 790 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 791 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 792 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 793 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 794 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 795 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 796 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 797 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 798 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 799 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 800 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 801 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 802 803 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 804 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 805 IAP_F_SBX), 806 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 807 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 808 IAP_F_SBX), 809 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 810 IAP_F_SBX), 811 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 812 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 813 IAP_F_SBX), 814 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 815 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 816 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 817 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 818 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 819 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 820 821 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 822 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX), 823 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 824 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 825 IAP_F_SBX), 826 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 827 IAP_F_SBX), 828 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX), 829 830 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 831 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 832 IAP_F_CA | IAP_F_CC2), 833 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 834 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 835 836 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 837 IAP_F_ALLCPUSCORE2), 838 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 839 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 840 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 841 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 842 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 843 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 844 845 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 846 IAP_F_ALLCPUSCORE2), 847 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 848 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 849 850 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 851 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 852 853 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 854 855 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 856 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 857 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 858 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 859 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 860 861 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 862 863 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 864 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 865 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 866 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 867 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 868 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 869 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 870 871 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 872 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 873 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 874 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 875 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 876 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 877 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 878 879 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 880 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 881 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 882 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 883 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 884 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 885 886 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 887 IAP_F_I7), 888 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 889 IAP_F_CC2 | IAP_F_I7), 890 891 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 892 893 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 894 895 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 896 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 897 898 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 899 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 900 IAP_F_SBX), 901 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 902 903 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 904 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 905 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 906 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 907 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 908 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 909 IAP_F_SBX), 910 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 911 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 912 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), 913 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), 914 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7), 915 916 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 917 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 918 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 919 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 920 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 921 922 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 923 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 924 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 925 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 926 IAP_F_SBX), 927 928 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 929 930 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 931 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 932 IAP_F_SB | IAP_F_SBX), 933 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 934 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 935 936 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 937 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 938 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 939 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 940 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 941 942 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 943 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 944 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 945 IAP_F_SB | IAP_F_SBX), 946 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 947 IAP_F_SB | IAP_F_SBX), 948 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 949 IAP_F_SB | IAP_F_SBX), 950 951 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 952 953 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 954 955 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB), 956 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB), 957 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB), 958 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB), 959 960 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 961 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 962 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 963 964 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 965 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 966 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 967 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 968 969 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 970 IAP_F_SBX), 971 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 972 IAP_F_SBX), 973 974 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 975 IAP_F_SBX), 976 977 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB), 978 979 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 980 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 981 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 982 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB), 983 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 984 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 985 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 986 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 987 988 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 989 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 990 991 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 992 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 993 994 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 995 IAP_F_CA | IAP_F_CC2), 996 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 997 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 998 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 999 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1000 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1001 1002 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1003 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1004 1005 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1006 IAP_F_CA | IAP_F_CC2), 1007 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1008 1009 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1010 1011 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1012 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1013 1014 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1015 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1016 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1017 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1018 1019 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1020 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1021 1022 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1023 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1024 1025 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1026 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1027 1028 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1029 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1030 1031 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1032 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1033 1034 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1035 IAP_F_CA | IAP_F_CC2), 1036 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1037 1038 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1039 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1040 1041 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1042 IAP_F_SBX), 1043 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1044 IAP_F_SBX), 1045 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1046 IAP_F_SBX), 1047 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1048 IAP_F_SBX), 1049 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1050 IAP_F_SBX), 1051 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1052 IAP_F_SBX), 1053 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB), 1054 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB), 1055 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB), 1056 1057 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1058 1059 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1060 1061 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1062 1063 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1064 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1065 1066 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1067 1068 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1069 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1070 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1071 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1072 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1073 IAP_F_WM), 1074 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1075 1076 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1077 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1078 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1079 1080 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1081 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1082 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1083 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1084 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1085 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1086 1087 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1088 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1089 1090 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1091 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1092 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1093 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1094 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1095 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1096 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1097 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1098 IAP_F_SBX), 1099 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), 1100 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), 1101 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1102 1103 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1104 1105 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1106 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1107 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1108 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1109 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1110 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1111 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1112 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1113 1114 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1115 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1116 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1117 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1118 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1119 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1120 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1121 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1122 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1123 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1124 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1125 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1126 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1127 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1128 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1129 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1130 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1131 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1132 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1133 IAP_F_SBX), 1134 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1135 IAP_F_SBX), 1136 1137 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1138 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1139 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1140 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1141 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1142 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1143 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1144 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1145 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1146 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1147 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1148 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1149 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1150 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1151 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1152 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1153 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1154 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1155 IAP_F_SBX), 1156 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1157 IAP_F_SBX), 1158 1159 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1160 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1161 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1162 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1163 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1164 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1165 1166 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1167 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1168 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1169 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1170 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1171 1172 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1173 IAP_F_SBX), 1174 1175 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1176 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1177 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1178 1179 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1180 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1181 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1182 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1183 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1184 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1185 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1186 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1187 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1188 IAP_F_SBX), 1189 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1190 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1191 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1192 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1193 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1194 IAP_F_SBX), 1195 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1196 IAP_F_SBX), 1197 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1198 IAP_F_SBX), 1199 1200 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1201 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1202 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1203 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1204 IAP_F_SB | IAP_F_SBX), 1205 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1206 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1207 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1208 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1209 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1210 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1211 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1212 IAP_F_SB | IAP_F_SBX), 1213 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1214 IAP_F_SB | IAP_F_SBX), 1215 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1216 IAP_F_SB | IAP_F_SBX), 1217 1218 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX), 1219 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX), 1220 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX), 1221 1222 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1223 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1224 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1225 1226 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1227 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1228 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1229 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1230 1231 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1232 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1233 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1234 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1235 1236 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1237 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1238 IAP_F_SBX), 1239 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1240 1241 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1242 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IB), 1243 1244 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1245 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1246 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1247 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB), 1248 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1249 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1250 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1251 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1252 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1253 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1254 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1255 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1256 1257 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1258 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1259 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1260 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1261 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1262 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1263 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1264 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1265 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1266 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1267 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1268 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1269 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1270 IAP_F_WM), 1271 1272 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1273 IAP_F_SB | IAP_F_SBX), 1274 1275 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1276 IAP_F_WM | IAP_F_I7O), 1277 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1278 IAP_F_WM | IAP_F_I7O), 1279 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1280 IAP_F_WM | IAP_F_I7O), 1281 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1282 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1283 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1284 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1285 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1286 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1287 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1288 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1289 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1290 1291 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1292 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1293 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1294 1295 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1296 1297 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1298 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1299 1300 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1301 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1302 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1303 1304 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1305 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1306 1307 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1308 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1309 1310 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1311 IAP_F_SBX), 1312 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1313 IAP_F_SBX), 1314 1315 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1316 1317 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1318 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1319 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1320 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1321 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1322 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1323 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1324 IAP_F_I7 | IAP_F_WM), 1325 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1326 1327 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1328 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1329 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1330 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1331 IAP_F_SBX), 1332 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1333 IAP_F_SBX), 1334 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1335 IAP_F_SBX), 1336 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1337 1338 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1339 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1340 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1341 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1342 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1343 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1344 IAP_F_I7 | IAP_F_WM), 1345 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1346 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1347 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1348 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1349 1350 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1351 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1352 IAP_F_I7 | IAP_F_WM), 1353 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1354 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1355 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1356 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1357 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1358 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1359 IAP_F_SBX), 1360 1361 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1362 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1363 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1364 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1365 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1366 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1367 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1368 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1369 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1370 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1371 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1372 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1373 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1374 IAP_F_SBX), 1375 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1376 IAP_F_SBX), 1377 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1378 IAP_F_SBX), 1379 1380 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1381 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1382 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1383 IAP_F_IB | IAP_F_SBX), 1384 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1385 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1386 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1387 IAP_F_IB | IAP_F_SBX), 1388 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1389 IAP_F_SBX), 1390 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1391 IAP_F_SBX), 1392 1393 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1394 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1395 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1396 1397 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1398 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1399 IAP_F_I7 | IAP_F_WM), 1400 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1401 IAP_F_I7 | IAP_F_WM), 1402 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1403 IAP_F_I7 | IAP_F_WM), 1404 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1405 IAP_F_I7 | IAP_F_WM), 1406 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1407 IAP_F_I7 | IAP_F_WM), 1408 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1409 1410 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1411 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1412 1413 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1414 1415 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1416 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1417 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1418 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1419 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1420 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1421 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1422 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1423 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1424 IAP_F_SBX), 1425 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1426 IAP_F_SBX), 1427 1428 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1429 IAP_F_I7 | IAP_F_WM), 1430 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1431 IAP_F_I7 | IAP_F_WM), 1432 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1433 IAP_F_I7 | IAP_F_WM), 1434 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1435 IAP_F_I7 | IAP_F_WM), 1436 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1437 IAP_F_WM), 1438 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1439 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1440 1441 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1442 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1443 IAP_F_I7 | IAP_F_WM), 1444 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1445 IAP_F_I7 | IAP_F_WM), 1446 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1447 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1448 IAP_F_SBX), 1449 1450 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1451 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1452 IAP_F_SBX), 1453 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1454 IAP_F_SBX), 1455 1456 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1457 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1458 1459 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1460 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1461 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1462 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1463 IAP_F_SBX), 1464 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1465 IAP_F_SBX), 1466 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1467 IAP_F_SBX), 1468 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1469 IAP_F_SBX), 1470 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1471 IAP_F_SBX), 1472 1473 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1474 IAP_F_IB | IAP_F_SBX), 1475 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1476 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1477 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1478 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1479 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1480 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX), 1481 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1482 IAP_F_SBX), 1483 1484 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1485 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1486 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1487 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1488 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1489 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1490 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1491 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1492 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1493 IAP_F_I7 | IAP_F_WM), 1494 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1495 1496 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX), 1497 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX), 1498 1499 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1500 IAP_F_I7 | IAP_F_WM), 1501 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1502 IAP_F_SB | IAP_F_SBX), 1503 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1504 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1505 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1506 1507 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1508 IAP_F_I7 | IAP_F_WM), 1509 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1510 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1511 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1512 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1513 1514 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1515 1516 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1517 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1518 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1519 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1520 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1521 1522 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1523 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1524 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1525 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1526 1527 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1528 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1529 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1530 1531 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1532 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1533 1534 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1535 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1536 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1537 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1538 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1539 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1540 1541 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1542 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1543 IAP_F_WM), 1544 1545 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1546 1547 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1548 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1549 1550 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1551 1552 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1553 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1554 IAP_F_WM | IAP_F_SBX), 1555 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1556 1557 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1558 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1559 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1560 1561 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1562 1563 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1564 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1565 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1566 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1567 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1568 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1569 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1570 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1571 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1572 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1573 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1574 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1575 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1576 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1577 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1578 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1579 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1580 1581 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1582 IAP_F_SBX), 1583 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1584 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1585 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1586 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1587 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1588 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1589 1590 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1591 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1592 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1593 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1594 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1595 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1596 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1597 IAP_F_SB | IAP_F_IB | IAP_F_SBX), 1598 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1599 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1600 1601 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1602 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1603 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1604 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1605 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1606 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1607 1608 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1609 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1610 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1611 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1612 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1613 IAP_F_SB | IAP_F_SBX), 1614 1615 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1616 1617 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1618 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1619 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1620 1621 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1622 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1623 1624 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1625 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1626 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1627 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1628 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1629 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1630 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1631}; 1632 1633static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1634 1635static pmc_value_t 1636iap_perfctr_value_to_reload_count(pmc_value_t v) 1637{ 1638 v &= (1ULL << core_iap_width) - 1; 1639 return (1ULL << core_iap_width) - v; 1640} 1641 1642static pmc_value_t 1643iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1644{ 1645 return (1ULL << core_iap_width) - rlc; 1646} 1647 1648static int 1649iap_pmc_has_overflowed(int ri) 1650{ 1651 uint64_t v; 1652 1653 /* 1654 * We treat a Core (i.e., Intel architecture v1) PMC as has 1655 * having overflowed if its MSB is zero. 1656 */ 1657 v = rdpmc(ri); 1658 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1659} 1660 1661/* 1662 * Check an event against the set of supported architectural events. 1663 * 1664 * Returns 1 if the event is architectural and unsupported on this 1665 * CPU. Returns 0 otherwise. 1666 */ 1667 1668static int 1669iap_architectural_event_is_unsupported(enum pmc_event pe) 1670{ 1671 enum core_arch_events ae; 1672 1673 switch (pe) { 1674 case PMC_EV_IAP_EVENT_3CH_00H: 1675 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1676 break; 1677 case PMC_EV_IAP_EVENT_C0H_00H: 1678 ae = CORE_AE_INSTRUCTION_RETIRED; 1679 break; 1680 case PMC_EV_IAP_EVENT_3CH_01H: 1681 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1682 break; 1683 case PMC_EV_IAP_EVENT_2EH_4FH: 1684 ae = CORE_AE_LLC_REFERENCE; 1685 break; 1686 case PMC_EV_IAP_EVENT_2EH_41H: 1687 ae = CORE_AE_LLC_MISSES; 1688 break; 1689 case PMC_EV_IAP_EVENT_C4H_00H: 1690 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1691 break; 1692 case PMC_EV_IAP_EVENT_C5H_00H: 1693 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1694 break; 1695 1696 default: /* Non architectural event. */ 1697 return (0); 1698 } 1699 1700 return ((core_architectural_events & (1 << ae)) == 0); 1701} 1702 1703static int 1704iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1705{ 1706 uint32_t mask; 1707 1708 switch (pe) { 1709 /* 1710 * Events valid only on counter 0, 1. 1711 */ 1712 case PMC_EV_IAP_EVENT_40H_01H: 1713 case PMC_EV_IAP_EVENT_40H_02H: 1714 case PMC_EV_IAP_EVENT_40H_04H: 1715 case PMC_EV_IAP_EVENT_40H_08H: 1716 case PMC_EV_IAP_EVENT_40H_0FH: 1717 case PMC_EV_IAP_EVENT_41H_02H: 1718 case PMC_EV_IAP_EVENT_41H_04H: 1719 case PMC_EV_IAP_EVENT_41H_08H: 1720 case PMC_EV_IAP_EVENT_42H_01H: 1721 case PMC_EV_IAP_EVENT_42H_02H: 1722 case PMC_EV_IAP_EVENT_42H_04H: 1723 case PMC_EV_IAP_EVENT_42H_08H: 1724 case PMC_EV_IAP_EVENT_43H_01H: 1725 case PMC_EV_IAP_EVENT_43H_02H: 1726 case PMC_EV_IAP_EVENT_51H_01H: 1727 case PMC_EV_IAP_EVENT_51H_02H: 1728 case PMC_EV_IAP_EVENT_51H_04H: 1729 case PMC_EV_IAP_EVENT_51H_08H: 1730 case PMC_EV_IAP_EVENT_63H_01H: 1731 case PMC_EV_IAP_EVENT_63H_02H: 1732 mask = 0x3; 1733 break; 1734 1735 default: 1736 mask = ~0; /* Any row index is ok. */ 1737 } 1738 1739 return (mask & (1 << ri)); 1740} 1741 1742static int 1743iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1744{ 1745 uint32_t mask; 1746 1747 switch (pe) { 1748 /* 1749 * Events valid only on counter 0. 1750 */ 1751 case PMC_EV_IAP_EVENT_60H_01H: 1752 case PMC_EV_IAP_EVENT_60H_02H: 1753 case PMC_EV_IAP_EVENT_60H_04H: 1754 case PMC_EV_IAP_EVENT_60H_08H: 1755 case PMC_EV_IAP_EVENT_B3H_01H: 1756 case PMC_EV_IAP_EVENT_B3H_02H: 1757 case PMC_EV_IAP_EVENT_B3H_04H: 1758 mask = 0x1; 1759 break; 1760 1761 /* 1762 * Events valid only on counter 0, 1. 1763 */ 1764 case PMC_EV_IAP_EVENT_4CH_01H: 1765 case PMC_EV_IAP_EVENT_4EH_01H: 1766 case PMC_EV_IAP_EVENT_4EH_02H: 1767 case PMC_EV_IAP_EVENT_4EH_04H: 1768 case PMC_EV_IAP_EVENT_51H_01H: 1769 case PMC_EV_IAP_EVENT_51H_02H: 1770 case PMC_EV_IAP_EVENT_51H_04H: 1771 case PMC_EV_IAP_EVENT_51H_08H: 1772 case PMC_EV_IAP_EVENT_63H_01H: 1773 case PMC_EV_IAP_EVENT_63H_02H: 1774 mask = 0x3; 1775 break; 1776 1777 default: 1778 mask = ~0; /* Any row index is ok. */ 1779 } 1780 1781 return (mask & (1 << ri)); 1782} 1783 1784static int 1785iap_event_sb_sbx_ib_ok_on_counter(enum pmc_event pe, int ri) 1786{ 1787 uint32_t mask; 1788 1789 switch (pe) { 1790 /* Events valid only on counter 0. */ 1791 case PMC_EV_IAP_EVENT_B7H_01H: 1792 mask = 0x1; 1793 break; 1794 /* Events valid only on counter 1. */ 1795 case PMC_EV_IAP_EVENT_C0H_01H: 1796 mask = 0x1; 1797 break; 1798 /* Events valid only on counter 2. */ 1799 case PMC_EV_IAP_EVENT_48H_01H: 1800 case PMC_EV_IAP_EVENT_A2H_02H: 1801 mask = 0x4; 1802 break; 1803 /* Events valid only on counter 3. */ 1804 case PMC_EV_IAP_EVENT_BBH_01H: 1805 case PMC_EV_IAP_EVENT_CDH_01H: 1806 case PMC_EV_IAP_EVENT_CDH_02H: 1807 mask = 0x8; 1808 break; 1809 default: 1810 mask = ~0; /* Any row index is ok. */ 1811 } 1812 1813 return (mask & (1 << ri)); 1814} 1815 1816static int 1817iap_event_ok_on_counter(enum pmc_event pe, int ri) 1818{ 1819 uint32_t mask; 1820 1821 switch (pe) { 1822 /* 1823 * Events valid only on counter 0. 1824 */ 1825 case PMC_EV_IAP_EVENT_10H_00H: 1826 case PMC_EV_IAP_EVENT_14H_00H: 1827 case PMC_EV_IAP_EVENT_18H_00H: 1828 case PMC_EV_IAP_EVENT_B3H_01H: 1829 case PMC_EV_IAP_EVENT_B3H_02H: 1830 case PMC_EV_IAP_EVENT_B3H_04H: 1831 case PMC_EV_IAP_EVENT_C1H_00H: 1832 case PMC_EV_IAP_EVENT_CBH_01H: 1833 case PMC_EV_IAP_EVENT_CBH_02H: 1834 mask = (1 << 0); 1835 break; 1836 1837 /* 1838 * Events valid only on counter 1. 1839 */ 1840 case PMC_EV_IAP_EVENT_11H_00H: 1841 case PMC_EV_IAP_EVENT_12H_00H: 1842 case PMC_EV_IAP_EVENT_13H_00H: 1843 mask = (1 << 1); 1844 break; 1845 1846 default: 1847 mask = ~0; /* Any row index is ok. */ 1848 } 1849 1850 return (mask & (1 << ri)); 1851} 1852 1853static int 1854iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1855 const struct pmc_op_pmcallocate *a) 1856{ 1857 int n, model; 1858 enum pmc_event ev; 1859 struct iap_event_descr *ie; 1860 uint32_t c, caps, config, cpuflag, evsel, mask; 1861 1862 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1863 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1864 KASSERT(ri >= 0 && ri < core_iap_npmc, 1865 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1866 1867 /* check requested capabilities */ 1868 caps = a->pm_caps; 1869 if ((IAP_PMC_CAPS & caps) != caps) 1870 return (EPERM); 1871 1872 ev = pm->pm_event; 1873 1874 if (iap_architectural_event_is_unsupported(ev)) 1875 return (EOPNOTSUPP); 1876 1877 /* 1878 * A small number of events are not supported in all the 1879 * processors based on a given microarchitecture. 1880 */ 1881 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 1882 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 1883 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 1884 return (EINVAL); 1885 } 1886 1887 switch (core_cputype) { 1888 case PMC_CPU_INTEL_COREI7: 1889 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1890 return (EINVAL); 1891 break; 1892 case PMC_CPU_INTEL_SANDYBRIDGE: 1893 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 1894 case PMC_CPU_INTEL_IVYBRIDGE: 1895 if (iap_event_sb_sbx_ib_ok_on_counter(ev, ri) == 0) 1896 return (EINVAL); 1897 break; 1898 case PMC_CPU_INTEL_WESTMERE: 1899 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1900 return (EINVAL); 1901 break; 1902 default: 1903 if (iap_event_ok_on_counter(ev, ri) == 0) 1904 return (EINVAL); 1905 } 1906 1907 /* 1908 * Look for an event descriptor with matching CPU and event id 1909 * fields. 1910 */ 1911 1912 switch (core_cputype) { 1913 default: 1914 case PMC_CPU_INTEL_ATOM: 1915 cpuflag = IAP_F_CA; 1916 break; 1917 case PMC_CPU_INTEL_CORE: 1918 cpuflag = IAP_F_CC; 1919 break; 1920 case PMC_CPU_INTEL_CORE2: 1921 cpuflag = IAP_F_CC2; 1922 break; 1923 case PMC_CPU_INTEL_CORE2EXTREME: 1924 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1925 break; 1926 case PMC_CPU_INTEL_COREI7: 1927 cpuflag = IAP_F_I7; 1928 break; 1929 case PMC_CPU_INTEL_IVYBRIDGE: 1930 cpuflag = IAP_F_IB; 1931 break; 1932 case PMC_CPU_INTEL_SANDYBRIDGE: 1933 cpuflag = IAP_F_SB; 1934 break; 1935 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 1936 cpuflag = IAP_F_SBX; 1937 break; 1938 case PMC_CPU_INTEL_WESTMERE: 1939 cpuflag = IAP_F_WM; 1940 break; 1941 } 1942 1943 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1944 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1945 break; 1946 1947 if (n == niap_events) 1948 return (EINVAL); 1949 1950 /* 1951 * A matching event descriptor has been found, so start 1952 * assembling the contents of the event select register. 1953 */ 1954 evsel = ie->iap_evcode; 1955 1956 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1957 1958 /* 1959 * If the event uses a fixed umask value, reject any umask 1960 * bits set by the user. 1961 */ 1962 if (ie->iap_flags & IAP_F_FM) { 1963 1964 if (IAP_UMASK(config) != 0) 1965 return (EINVAL); 1966 1967 evsel |= (ie->iap_umask << 8); 1968 1969 } else { 1970 1971 /* 1972 * Otherwise, the UMASK value needs to be taken from 1973 * the MD fields of the allocation request. Reject 1974 * requests that specify reserved bits. 1975 */ 1976 1977 mask = 0; 1978 1979 if (ie->iap_umask & IAP_M_CORE) { 1980 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1981 c != IAP_CORE_THIS) 1982 return (EINVAL); 1983 mask |= IAP_F_CORE; 1984 } 1985 1986 if (ie->iap_umask & IAP_M_AGENT) 1987 mask |= IAP_F_AGENT; 1988 1989 if (ie->iap_umask & IAP_M_PREFETCH) { 1990 1991 if ((c = (config & IAP_F_PREFETCH)) == 1992 IAP_PREFETCH_RESERVED) 1993 return (EINVAL); 1994 1995 mask |= IAP_F_PREFETCH; 1996 } 1997 1998 if (ie->iap_umask & IAP_M_MESI) 1999 mask |= IAP_F_MESI; 2000 2001 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2002 mask |= IAP_F_SNOOPRESPONSE; 2003 2004 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2005 mask |= IAP_F_SNOOPTYPE; 2006 2007 if (ie->iap_umask & IAP_M_TRANSITION) 2008 mask |= IAP_F_TRANSITION; 2009 2010 /* 2011 * If bits outside of the allowed set of umask bits 2012 * are set, reject the request. 2013 */ 2014 if (config & ~mask) 2015 return (EINVAL); 2016 2017 evsel |= (config & mask); 2018 2019 } 2020 2021 /* 2022 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2023 */ 2024 if (core_cputype == PMC_CPU_INTEL_ATOM || 2025 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2026 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2027 evsel |= (config & IAP_ANY); 2028 else if (config & IAP_ANY) 2029 return (EINVAL); 2030 2031 /* 2032 * Check offcore response configuration. 2033 */ 2034 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2035 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2036 ev != PMC_EV_IAP_EVENT_BBH_01H) 2037 return (EINVAL); 2038 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2039 ev == PMC_EV_IAP_EVENT_BBH_01H) 2040 return (EINVAL); 2041 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2042 core_cputype == PMC_CPU_INTEL_WESTMERE) && 2043 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2044 return (EINVAL); 2045 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2046 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2047 core_cputype == PMC_CPU_INTEL_IVYBRIDGE) && 2048 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2049 return (EINVAL); 2050 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2051 } 2052 2053 if (caps & PMC_CAP_THRESHOLD) 2054 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2055 if (caps & PMC_CAP_USER) 2056 evsel |= IAP_USR; 2057 if (caps & PMC_CAP_SYSTEM) 2058 evsel |= IAP_OS; 2059 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2060 evsel |= (IAP_OS | IAP_USR); 2061 if (caps & PMC_CAP_EDGE) 2062 evsel |= IAP_EDGE; 2063 if (caps & PMC_CAP_INVERT) 2064 evsel |= IAP_INV; 2065 if (caps & PMC_CAP_INTERRUPT) 2066 evsel |= IAP_INT; 2067 2068 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2069 2070 return (0); 2071} 2072 2073static int 2074iap_config_pmc(int cpu, int ri, struct pmc *pm) 2075{ 2076 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2077 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2078 2079 KASSERT(ri >= 0 && ri < core_iap_npmc, 2080 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2081 2082 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2083 2084 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2085 cpu)); 2086 2087 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2088 2089 return (0); 2090} 2091 2092static int 2093iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2094{ 2095 int error; 2096 struct pmc_hw *phw; 2097 char iap_name[PMC_NAME_MAX]; 2098 2099 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2100 2101 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2102 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2103 NULL)) != 0) 2104 return (error); 2105 2106 pi->pm_class = PMC_CLASS_IAP; 2107 2108 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2109 pi->pm_enabled = TRUE; 2110 *ppmc = phw->phw_pmc; 2111 } else { 2112 pi->pm_enabled = FALSE; 2113 *ppmc = NULL; 2114 } 2115 2116 return (0); 2117} 2118 2119static int 2120iap_get_config(int cpu, int ri, struct pmc **ppm) 2121{ 2122 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2123 2124 return (0); 2125} 2126 2127static int 2128iap_get_msr(int ri, uint32_t *msr) 2129{ 2130 KASSERT(ri >= 0 && ri < core_iap_npmc, 2131 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2132 2133 *msr = ri; 2134 2135 return (0); 2136} 2137 2138static int 2139iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2140{ 2141 struct pmc *pm; 2142 pmc_value_t tmp; 2143 2144 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2145 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2146 KASSERT(ri >= 0 && ri < core_iap_npmc, 2147 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2148 2149 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2150 2151 KASSERT(pm, 2152 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2153 ri)); 2154 2155 tmp = rdpmc(ri); 2156 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2157 *v = iap_perfctr_value_to_reload_count(tmp); 2158 else 2159 *v = tmp & ((1ULL << core_iap_width) - 1); 2160 2161 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2162 ri, *v); 2163 2164 return (0); 2165} 2166 2167static int 2168iap_release_pmc(int cpu, int ri, struct pmc *pm) 2169{ 2170 (void) pm; 2171 2172 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2173 pm); 2174 2175 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2176 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2177 KASSERT(ri >= 0 && ri < core_iap_npmc, 2178 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2179 2180 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2181 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2182 2183 return (0); 2184} 2185 2186static int 2187iap_start_pmc(int cpu, int ri) 2188{ 2189 struct pmc *pm; 2190 uint32_t evsel; 2191 struct core_cpu *cc; 2192 2193 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2194 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2195 KASSERT(ri >= 0 && ri < core_iap_npmc, 2196 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2197 2198 cc = core_pcpu[cpu]; 2199 pm = cc->pc_corepmcs[ri].phw_pmc; 2200 2201 KASSERT(pm, 2202 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2203 __LINE__, cpu, ri)); 2204 2205 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2206 2207 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2208 2209 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2210 cpu, ri, IAP_EVSEL0 + ri, evsel); 2211 2212 /* Event specific configuration. */ 2213 switch (pm->pm_event) { 2214 case PMC_EV_IAP_EVENT_B7H_01H: 2215 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2216 break; 2217 case PMC_EV_IAP_EVENT_BBH_01H: 2218 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2219 break; 2220 default: 2221 break; 2222 } 2223 2224 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2225 2226 if (core_cputype == PMC_CPU_INTEL_CORE) 2227 return (0); 2228 2229 do { 2230 cc->pc_resync = 0; 2231 cc->pc_globalctrl |= (1ULL << ri); 2232 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2233 } while (cc->pc_resync != 0); 2234 2235 return (0); 2236} 2237 2238static int 2239iap_stop_pmc(int cpu, int ri) 2240{ 2241 struct pmc *pm; 2242 struct core_cpu *cc; 2243 uint64_t msr; 2244 2245 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2246 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2247 KASSERT(ri >= 0 && ri < core_iap_npmc, 2248 ("[core,%d] illegal row index %d", __LINE__, ri)); 2249 2250 cc = core_pcpu[cpu]; 2251 pm = cc->pc_corepmcs[ri].phw_pmc; 2252 2253 KASSERT(pm, 2254 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2255 cpu, ri)); 2256 2257 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2258 2259 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2260 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2261 2262 if (core_cputype == PMC_CPU_INTEL_CORE) 2263 return (0); 2264 2265 msr = 0; 2266 do { 2267 cc->pc_resync = 0; 2268 cc->pc_globalctrl &= ~(1ULL << ri); 2269 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2270 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2271 } while (cc->pc_resync != 0); 2272 2273 return (0); 2274} 2275 2276static int 2277iap_write_pmc(int cpu, int ri, pmc_value_t v) 2278{ 2279 struct pmc *pm; 2280 struct core_cpu *cc; 2281 2282 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2283 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2284 KASSERT(ri >= 0 && ri < core_iap_npmc, 2285 ("[core,%d] illegal row index %d", __LINE__, ri)); 2286 2287 cc = core_pcpu[cpu]; 2288 pm = cc->pc_corepmcs[ri].phw_pmc; 2289 2290 KASSERT(pm, 2291 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2292 cpu, ri)); 2293 2294 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2295 IAP_PMC0 + ri, v); 2296 2297 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2298 v = iap_reload_count_to_perfctr_value(v); 2299 2300 /* 2301 * Write the new value to the counter. The counter will be in 2302 * a stopped state when the pcd_write() entry point is called. 2303 */ 2304 2305 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2306 2307 return (0); 2308} 2309 2310 2311static void 2312iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2313 int flags) 2314{ 2315 struct pmc_classdep *pcd; 2316 2317 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2318 2319 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2320 2321 /* Remember the set of architectural events supported. */ 2322 core_architectural_events = ~flags; 2323 2324 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2325 2326 pcd->pcd_caps = IAP_PMC_CAPS; 2327 pcd->pcd_class = PMC_CLASS_IAP; 2328 pcd->pcd_num = npmc; 2329 pcd->pcd_ri = md->pmd_npmc; 2330 pcd->pcd_width = pmcwidth; 2331 2332 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2333 pcd->pcd_config_pmc = iap_config_pmc; 2334 pcd->pcd_describe = iap_describe; 2335 pcd->pcd_get_config = iap_get_config; 2336 pcd->pcd_get_msr = iap_get_msr; 2337 pcd->pcd_pcpu_fini = core_pcpu_fini; 2338 pcd->pcd_pcpu_init = core_pcpu_init; 2339 pcd->pcd_read_pmc = iap_read_pmc; 2340 pcd->pcd_release_pmc = iap_release_pmc; 2341 pcd->pcd_start_pmc = iap_start_pmc; 2342 pcd->pcd_stop_pmc = iap_stop_pmc; 2343 pcd->pcd_write_pmc = iap_write_pmc; 2344 2345 md->pmd_npmc += npmc; 2346} 2347 2348static int 2349core_intr(int cpu, struct trapframe *tf) 2350{ 2351 pmc_value_t v; 2352 struct pmc *pm; 2353 struct core_cpu *cc; 2354 int error, found_interrupt, ri; 2355 uint64_t msr; 2356 2357 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2358 TRAPF_USERMODE(tf)); 2359 2360 found_interrupt = 0; 2361 cc = core_pcpu[cpu]; 2362 2363 for (ri = 0; ri < core_iap_npmc; ri++) { 2364 2365 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2366 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2367 continue; 2368 2369 if (!iap_pmc_has_overflowed(ri)) 2370 continue; 2371 2372 found_interrupt = 1; 2373 2374 if (pm->pm_state != PMC_STATE_RUNNING) 2375 continue; 2376 2377 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2378 TRAPF_USERMODE(tf)); 2379 2380 v = pm->pm_sc.pm_reloadcount; 2381 v = iaf_reload_count_to_perfctr_value(v); 2382 2383 /* 2384 * Stop the counter, reload it but only restart it if 2385 * the PMC is not stalled. 2386 */ 2387 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2388 wrmsr(IAP_EVSEL0 + ri, msr); 2389 wrmsr(IAP_PMC0 + ri, v); 2390 2391 if (error) 2392 continue; 2393 2394 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2395 IAP_EN)); 2396 } 2397 2398 if (found_interrupt) 2399 lapic_reenable_pmc(); 2400 2401 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2402 &pmc_stats.pm_intr_ignored, 1); 2403 2404 return (found_interrupt); 2405} 2406 2407static int 2408core2_intr(int cpu, struct trapframe *tf) 2409{ 2410 int error, found_interrupt, n; 2411 uint64_t flag, intrstatus, intrenable, msr; 2412 struct pmc *pm; 2413 struct core_cpu *cc; 2414 pmc_value_t v; 2415 2416 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2417 TRAPF_USERMODE(tf)); 2418 2419 /* 2420 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2421 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2422 * the current set of interrupting PMCs and process these 2423 * after stopping them. 2424 */ 2425 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2426 intrenable = intrstatus & core_pmcmask; 2427 2428 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2429 (uintmax_t) intrstatus); 2430 2431 found_interrupt = 0; 2432 cc = core_pcpu[cpu]; 2433 2434 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2435 2436 cc->pc_globalctrl &= ~intrenable; 2437 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2438 2439 /* 2440 * Stop PMCs and clear overflow status bits. 2441 */ 2442 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2443 wrmsr(IA_GLOBAL_CTRL, msr); 2444 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2445 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2446 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2447 2448 /* 2449 * Look for interrupts from fixed function PMCs. 2450 */ 2451 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2452 n++, flag <<= 1) { 2453 2454 if ((intrstatus & flag) == 0) 2455 continue; 2456 2457 found_interrupt = 1; 2458 2459 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2460 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2461 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2462 continue; 2463 2464 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2465 TRAPF_USERMODE(tf)); 2466 if (error) 2467 intrenable &= ~flag; 2468 2469 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2470 2471 /* Reload sampling count. */ 2472 wrmsr(IAF_CTR0 + n, v); 2473 2474 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2475 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2476 } 2477 2478 /* 2479 * Process interrupts from the programmable counters. 2480 */ 2481 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2482 if ((intrstatus & flag) == 0) 2483 continue; 2484 2485 found_interrupt = 1; 2486 2487 pm = cc->pc_corepmcs[n].phw_pmc; 2488 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2489 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2490 continue; 2491 2492 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2493 TRAPF_USERMODE(tf)); 2494 if (error) 2495 intrenable &= ~flag; 2496 2497 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2498 2499 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2500 (uintmax_t) v); 2501 2502 /* Reload sampling count. */ 2503 wrmsr(IAP_PMC0 + n, v); 2504 } 2505 2506 /* 2507 * Reenable all non-stalled PMCs. 2508 */ 2509 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2510 (uintmax_t) intrenable); 2511 2512 cc->pc_globalctrl |= intrenable; 2513 2514 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2515 2516 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2517 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2518 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2519 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2520 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2521 2522 if (found_interrupt) 2523 lapic_reenable_pmc(); 2524 2525 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2526 &pmc_stats.pm_intr_ignored, 1); 2527 2528 return (found_interrupt); 2529} 2530 2531int 2532pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2533{ 2534 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2535 int ipa_version, flags, nflags; 2536 2537 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2538 2539 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2540 2541 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2542 md->pmd_cputype, maxcpu, ipa_version); 2543 2544 if (ipa_version < 1 || ipa_version > 3) { 2545 /* Unknown PMC architecture. */ 2546 printf("hwpc_core: unknown PMC architecture: %d\n", 2547 ipa_version); 2548 return (EPROGMISMATCH); 2549 } 2550 2551 core_cputype = md->pmd_cputype; 2552 2553 core_pmcmask = 0; 2554 2555 /* 2556 * Initialize programmable counters. 2557 */ 2558 KASSERT(ipa_version >= 1, 2559 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2560 2561 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2562 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2563 2564 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2565 2566 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2567 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2568 2569 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2570 2571 /* 2572 * Initialize fixed function counters, if present. 2573 */ 2574 if (core_cputype != PMC_CPU_INTEL_CORE) { 2575 KASSERT(ipa_version >= 2, 2576 ("[core,%d] ipa_version %d too small", __LINE__, 2577 ipa_version)); 2578 2579 core_iaf_ri = core_iap_npmc; 2580 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2581 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2582 2583 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2584 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2585 } 2586 2587 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2588 core_iaf_ri); 2589 2590 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2591 M_ZERO | M_WAITOK); 2592 2593 /* 2594 * Choose the appropriate interrupt handler. 2595 */ 2596 if (ipa_version == 1) 2597 md->pmd_intr = core_intr; 2598 else 2599 md->pmd_intr = core2_intr; 2600 2601 md->pmd_pcpu_fini = NULL; 2602 md->pmd_pcpu_init = NULL; 2603 2604 return (0); 2605} 2606 2607void 2608pmc_core_finalize(struct pmc_mdep *md) 2609{ 2610 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2611 2612 free(core_pcpu, M_PMC); 2613 core_pcpu = NULL; 2614} 2615