hwpmc_core.c revision 240164
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 240164 2012-09-06 13:54:01Z fabient $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#include <machine/apicvar.h> 42#include <machine/cpu.h> 43#include <machine/cpufunc.h> 44#include <machine/md_var.h> 45#include <machine/specialreg.h> 46 47#define CORE_CPUID_REQUEST 0xA 48#define CORE_CPUID_REQUEST_SIZE 0x4 49#define CORE_CPUID_EAX 0x0 50#define CORE_CPUID_EBX 0x1 51#define CORE_CPUID_ECX 0x2 52#define CORE_CPUID_EDX 0x3 53 54#define IAF_PMC_CAPS \ 55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 56 PMC_CAP_USER | PMC_CAP_SYSTEM) 57#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 58 59#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 62 63/* 64 * "Architectural" events defined by Intel. The values of these 65 * symbols correspond to positions in the bitmask returned by 66 * the CPUID.0AH instruction. 67 */ 68enum core_arch_events { 69 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 70 CORE_AE_BRANCH_MISSES_RETIRED = 6, 71 CORE_AE_INSTRUCTION_RETIRED = 1, 72 CORE_AE_LLC_MISSES = 4, 73 CORE_AE_LLC_REFERENCE = 3, 74 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 75 CORE_AE_UNHALTED_CORE_CYCLES = 0 76}; 77 78static enum pmc_cputype core_cputype; 79 80struct core_cpu { 81 volatile uint32_t pc_resync; 82 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 83 volatile uint64_t pc_globalctrl; /* Global control register. */ 84 struct pmc_hw pc_corepmcs[]; 85}; 86 87static struct core_cpu **core_pcpu; 88 89static uint32_t core_architectural_events; 90static uint64_t core_pmcmask; 91 92static int core_iaf_ri; /* relative index of fixed counters */ 93static int core_iaf_width; 94static int core_iaf_npmc; 95 96static int core_iap_width; 97static int core_iap_npmc; 98 99static int 100core_pcpu_noop(struct pmc_mdep *md, int cpu) 101{ 102 (void) md; 103 (void) cpu; 104 return (0); 105} 106 107static int 108core_pcpu_init(struct pmc_mdep *md, int cpu) 109{ 110 struct pmc_cpu *pc; 111 struct core_cpu *cc; 112 struct pmc_hw *phw; 113 int core_ri, n, npmc; 114 115 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 116 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 117 118 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 119 120 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 121 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 122 123 if (core_cputype != PMC_CPU_INTEL_CORE) 124 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 125 126 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 127 M_PMC, M_WAITOK | M_ZERO); 128 129 core_pcpu[cpu] = cc; 130 pc = pmc_pcpu[cpu]; 131 132 KASSERT(pc != NULL && cc != NULL, 133 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 134 135 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 136 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 137 PMC_PHW_CPU_TO_STATE(cpu) | 138 PMC_PHW_INDEX_TO_STATE(n + core_ri); 139 phw->phw_pmc = NULL; 140 pc->pc_hwpmcs[n + core_ri] = phw; 141 } 142 143 return (0); 144} 145 146static int 147core_pcpu_fini(struct pmc_mdep *md, int cpu) 148{ 149 int core_ri, n, npmc; 150 struct pmc_cpu *pc; 151 struct core_cpu *cc; 152 uint64_t msr = 0; 153 154 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 155 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 156 157 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 158 159 if ((cc = core_pcpu[cpu]) == NULL) 160 return (0); 161 162 core_pcpu[cpu] = NULL; 163 164 pc = pmc_pcpu[cpu]; 165 166 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 167 cpu)); 168 169 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 170 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 171 172 for (n = 0; n < npmc; n++) { 173 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 174 wrmsr(IAP_EVSEL0 + n, msr); 175 } 176 177 if (core_cputype != PMC_CPU_INTEL_CORE) { 178 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 179 wrmsr(IAF_CTRL, msr); 180 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 181 } 182 183 for (n = 0; n < npmc; n++) 184 pc->pc_hwpmcs[n + core_ri] = NULL; 185 186 free(cc, M_PMC); 187 188 return (0); 189} 190 191/* 192 * Fixed function counters. 193 */ 194 195static pmc_value_t 196iaf_perfctr_value_to_reload_count(pmc_value_t v) 197{ 198 v &= (1ULL << core_iaf_width) - 1; 199 return (1ULL << core_iaf_width) - v; 200} 201 202static pmc_value_t 203iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 204{ 205 return (1ULL << core_iaf_width) - rlc; 206} 207 208static int 209iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 210 const struct pmc_op_pmcallocate *a) 211{ 212 enum pmc_event ev; 213 uint32_t caps, flags, validflags; 214 215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 216 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 217 218 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 219 220 if (ri < 0 || ri > core_iaf_npmc) 221 return (EINVAL); 222 223 caps = a->pm_caps; 224 225 if (a->pm_class != PMC_CLASS_IAF || 226 (caps & IAF_PMC_CAPS) != caps) 227 return (EINVAL); 228 229 ev = pm->pm_event; 230 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 231 return (EINVAL); 232 233 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 234 return (EINVAL); 235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 236 return (EINVAL); 237 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 238 return (EINVAL); 239 240 flags = a->pm_md.pm_iaf.pm_iaf_flags; 241 242 validflags = IAF_MASK; 243 244 if (core_cputype != PMC_CPU_INTEL_ATOM) 245 validflags &= ~IAF_ANY; 246 247 if ((flags & ~validflags) != 0) 248 return (EINVAL); 249 250 if (caps & PMC_CAP_INTERRUPT) 251 flags |= IAF_PMI; 252 if (caps & PMC_CAP_SYSTEM) 253 flags |= IAF_OS; 254 if (caps & PMC_CAP_USER) 255 flags |= IAF_USR; 256 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 257 flags |= (IAF_OS | IAF_USR); 258 259 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 260 261 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 262 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 263 264 return (0); 265} 266 267static int 268iaf_config_pmc(int cpu, int ri, struct pmc *pm) 269{ 270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 271 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 272 273 KASSERT(ri >= 0 && ri < core_iaf_npmc, 274 ("[core,%d] illegal row-index %d", __LINE__, ri)); 275 276 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 277 278 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 279 cpu)); 280 281 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 282 283 return (0); 284} 285 286static int 287iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 288{ 289 int error; 290 struct pmc_hw *phw; 291 char iaf_name[PMC_NAME_MAX]; 292 293 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 294 295 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 296 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 297 NULL)) != 0) 298 return (error); 299 300 pi->pm_class = PMC_CLASS_IAF; 301 302 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 303 pi->pm_enabled = TRUE; 304 *ppmc = phw->phw_pmc; 305 } else { 306 pi->pm_enabled = FALSE; 307 *ppmc = NULL; 308 } 309 310 return (0); 311} 312 313static int 314iaf_get_config(int cpu, int ri, struct pmc **ppm) 315{ 316 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 317 318 return (0); 319} 320 321static int 322iaf_get_msr(int ri, uint32_t *msr) 323{ 324 KASSERT(ri >= 0 && ri < core_iaf_npmc, 325 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 326 327 *msr = IAF_RI_TO_MSR(ri); 328 329 return (0); 330} 331 332static int 333iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 334{ 335 struct pmc *pm; 336 pmc_value_t tmp; 337 338 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 339 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 340 KASSERT(ri >= 0 && ri < core_iaf_npmc, 341 ("[core,%d] illegal row-index %d", __LINE__, ri)); 342 343 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 344 345 KASSERT(pm, 346 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 347 ri, ri + core_iaf_ri)); 348 349 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 350 351 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 352 *v = iaf_perfctr_value_to_reload_count(tmp); 353 else 354 *v = tmp; 355 356 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 357 IAF_RI_TO_MSR(ri), *v); 358 359 return (0); 360} 361 362static int 363iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 364{ 365 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 366 367 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 368 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 369 KASSERT(ri >= 0 && ri < core_iaf_npmc, 370 ("[core,%d] illegal row-index %d", __LINE__, ri)); 371 372 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 373 ("[core,%d] PHW pmc non-NULL", __LINE__)); 374 375 return (0); 376} 377 378static int 379iaf_start_pmc(int cpu, int ri) 380{ 381 struct pmc *pm; 382 struct core_cpu *iafc; 383 uint64_t msr = 0; 384 385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 386 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 387 KASSERT(ri >= 0 && ri < core_iaf_npmc, 388 ("[core,%d] illegal row-index %d", __LINE__, ri)); 389 390 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 391 392 iafc = core_pcpu[cpu]; 393 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 394 395 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 396 397 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 398 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 399 400 do { 401 iafc->pc_resync = 0; 402 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 403 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 404 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 405 IAF_GLOBAL_CTRL_MASK)); 406 } while (iafc->pc_resync != 0); 407 408 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 409 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 410 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 411 412 return (0); 413} 414 415static int 416iaf_stop_pmc(int cpu, int ri) 417{ 418 uint32_t fc; 419 struct core_cpu *iafc; 420 uint64_t msr = 0; 421 422 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 423 424 iafc = core_pcpu[cpu]; 425 426 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 427 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 428 KASSERT(ri >= 0 && ri < core_iaf_npmc, 429 ("[core,%d] illegal row-index %d", __LINE__, ri)); 430 431 fc = (IAF_MASK << (ri * 4)); 432 433 if (core_cputype != PMC_CPU_INTEL_ATOM) 434 fc &= ~IAF_ANY; 435 436 iafc->pc_iafctrl &= ~fc; 437 438 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 439 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 440 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 441 442 do { 443 iafc->pc_resync = 0; 444 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 445 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 446 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 447 IAF_GLOBAL_CTRL_MASK)); 448 } while (iafc->pc_resync != 0); 449 450 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 451 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 452 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 453 454 return (0); 455} 456 457static int 458iaf_write_pmc(int cpu, int ri, pmc_value_t v) 459{ 460 struct core_cpu *cc; 461 struct pmc *pm; 462 uint64_t msr; 463 464 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 465 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 466 KASSERT(ri >= 0 && ri < core_iaf_npmc, 467 ("[core,%d] illegal row-index %d", __LINE__, ri)); 468 469 cc = core_pcpu[cpu]; 470 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 471 472 KASSERT(pm, 473 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 474 475 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 476 v = iaf_reload_count_to_perfctr_value(v); 477 478 /* Turn off fixed counters */ 479 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 480 wrmsr(IAF_CTRL, msr); 481 482 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 483 484 /* Turn on fixed counters */ 485 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 486 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 487 488 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 489 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 490 (uintmax_t) rdmsr(IAF_CTRL), 491 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 492 493 return (0); 494} 495 496 497static void 498iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 499{ 500 struct pmc_classdep *pcd; 501 502 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 503 504 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 505 506 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 507 508 pcd->pcd_caps = IAF_PMC_CAPS; 509 pcd->pcd_class = PMC_CLASS_IAF; 510 pcd->pcd_num = npmc; 511 pcd->pcd_ri = md->pmd_npmc; 512 pcd->pcd_width = pmcwidth; 513 514 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 515 pcd->pcd_config_pmc = iaf_config_pmc; 516 pcd->pcd_describe = iaf_describe; 517 pcd->pcd_get_config = iaf_get_config; 518 pcd->pcd_get_msr = iaf_get_msr; 519 pcd->pcd_pcpu_fini = core_pcpu_noop; 520 pcd->pcd_pcpu_init = core_pcpu_noop; 521 pcd->pcd_read_pmc = iaf_read_pmc; 522 pcd->pcd_release_pmc = iaf_release_pmc; 523 pcd->pcd_start_pmc = iaf_start_pmc; 524 pcd->pcd_stop_pmc = iaf_stop_pmc; 525 pcd->pcd_write_pmc = iaf_write_pmc; 526 527 md->pmd_npmc += npmc; 528} 529 530/* 531 * Intel programmable PMCs. 532 */ 533 534/* 535 * Event descriptor tables. 536 * 537 * For each event id, we track: 538 * 539 * 1. The CPUs that the event is valid for. 540 * 541 * 2. If the event uses a fixed UMASK, the value of the umask field. 542 * If the event doesn't use a fixed UMASK, a mask of legal bits 543 * to check against. 544 */ 545 546struct iap_event_descr { 547 enum pmc_event iap_ev; 548 unsigned char iap_evcode; 549 unsigned char iap_umask; 550 unsigned int iap_flags; 551}; 552 553#define IAP_F_CC (1 << 0) /* CPU: Core */ 554#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 555#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 556#define IAP_F_CA (1 << 3) /* CPU: Atom */ 557#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 558#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 559#define IAP_F_WM (1 << 5) /* CPU: Westmere */ 560#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 561#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 562#define IAP_F_FM (1 << 8) /* Fixed mask */ 563 564#define IAP_F_ALLCPUSCORE2 \ 565 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 566 567/* Sub fields of UMASK that this event supports. */ 568#define IAP_M_CORE (1 << 0) /* Core specificity */ 569#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 570#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 571#define IAP_M_MESI (1 << 3) /* MESI */ 572#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 573#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 574#define IAP_M_TRANSITION (1 << 6) /* Transition */ 575 576#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 577#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 578#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 579#define IAP_F_MESI (0xF << 8) /* MESI */ 580#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 581#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 582#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 583 584#define IAP_PREFETCH_RESERVED (0x2 << 12) 585#define IAP_CORE_THIS (0x1 << 14) 586#define IAP_CORE_ALL (0x3 << 14) 587#define IAP_F_CMASK 0xFF000000 588 589static struct iap_event_descr iap_events[] = { 590#undef IAPDESCR 591#define IAPDESCR(N,EV,UM,FLAGS) { \ 592 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 593 .iap_evcode = (EV), \ 594 .iap_umask = (UM), \ 595 .iap_flags = (FLAGS) \ 596 } 597 598 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 599 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 600 601 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 602 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB), 603 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 604 IAP_F_WM | IAP_F_SB | IAP_F_IB), 605 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 606 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), 607 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), 608 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 609 610 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 611 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 612 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 613 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 614 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 615 616 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 617 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB), 618 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB), 619 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 620 621 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 622 IAP_F_CC2E | IAP_F_CA), 623 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 624 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 625 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 626 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 627 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 628 629 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 630 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 631 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 632 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 633 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 634 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 635 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB), 636 637 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 638 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 639 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 640 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 641 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 642 IAP_F_WM | IAP_F_SB), 643 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 644 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 645 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 646 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 647 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 648 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 649 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 650 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), 651 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 652 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB), 653 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB), 654 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB), 655 656 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 657 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 658 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 659 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 660 661 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 662 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 663 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 664 665 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 666 IAP_F_WM), 667 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 668 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 669 670 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB), 671 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB), 672 673 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 674 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 675 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB), 676 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB), 677 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB), 678 679 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 680 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 681 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 682 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 683 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 684 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 685 686 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 687 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 688 IAP_F_WM | IAP_F_SB), 689 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 690 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 691 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 692 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 693 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 694 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 695 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 696 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 697 698 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 699 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB), 700 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB), 701 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 702 703 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 704 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 705 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 706 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 707 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 708 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 709 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 710 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 711 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 712 713 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 714 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 715 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 716 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 717 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 718 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 719 720 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 721 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 722 IAP_F_WM | IAP_F_SB | IAP_F_IB), 723 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 724 725 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 726 727 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 728 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 729 730 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 731 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 732 IAP_F_I7 | IAP_F_WM), 733 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 734 735 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 736 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 737 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 738 739 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 740 741 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 742 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 743 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 744 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 745 746 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 747 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 748 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 749 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 750 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 751 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 752 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 753 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 754 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 755 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 756 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 757 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 758 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 759 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 761 762 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 763 764 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 765 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 766 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 769 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 770 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 771 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 772 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 773 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 774 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 775 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 776 777 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 778 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 779 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 780 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB), 781 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 782 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 783 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 784 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 785 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 786 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 787 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 788 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 789 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 790 791 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 792 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB), 793 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 794 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 795 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 796 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB), 797 798 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 799 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 800 IAP_F_CA | IAP_F_CC2), 801 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 802 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 803 804 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 805 IAP_F_ALLCPUSCORE2), 806 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 807 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 808 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 809 IAP_F_SB | IAP_F_IB), 810 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 811 IAP_F_SB | IAP_F_IB), 812 813 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 814 IAP_F_ALLCPUSCORE2), 815 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 816 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 817 818 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 819 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 820 821 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 822 823 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 824 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 825 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 826 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 827 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 828 829 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 830 831 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 832 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 833 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 834 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 835 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 836 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 837 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 838 839 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 840 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 841 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 842 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 843 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 844 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 845 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 846 847 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 848 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 849 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 850 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 851 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 852 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 853 854 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 855 IAP_F_I7), 856 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 857 IAP_F_CC2 | IAP_F_I7), 858 859 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 860 861 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 862 863 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 864 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 865 866 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 867 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 868 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 869 870 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 871 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 872 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 873 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 874 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 875 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), 876 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 877 IAP_F_SB | IAP_F_IB), 878 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), 879 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), 880 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7), 881 882 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 883 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 884 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 885 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 886 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 887 888 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 889 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 890 IAP_F_SB | IAP_F_IB), 891 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), 892 893 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 894 895 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 896 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 897 IAP_F_SB), 898 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 899 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 900 901 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 902 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 903 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 904 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 905 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 906 907 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 908 IAP_F_SB | IAP_F_IB), 909 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 910 IAP_F_SB), 911 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 912 IAP_F_SB), 913 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 914 IAP_F_SB), 915 916 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 917 918 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 919 920 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB), 921 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB), 922 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB), 923 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB), 924 925 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB), 926 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB), 927 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB), 928 929 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB), 930 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB), 931 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB), 932 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB), 933 934 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 935 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), 936 937 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 938 939 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB), 940 941 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 942 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 943 IAP_F_SB | IAP_F_IB), 944 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB), 945 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 946 IAP_F_SB | IAP_F_IB), 947 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 948 IAP_F_SB | IAP_F_IB), 949 950 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 951 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 952 953 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 954 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 955 956 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 957 IAP_F_CA | IAP_F_CC2), 958 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 959 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 960 IAP_F_SB | IAP_F_IB), 961 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 962 IAP_F_SB | IAP_F_IB), 963 964 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 965 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 966 967 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 968 IAP_F_CA | IAP_F_CC2), 969 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 970 971 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 972 973 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 974 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 975 976 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 977 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 978 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 979 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 980 981 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 982 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 983 984 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 985 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 986 987 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 988 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 989 990 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 991 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 992 993 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 994 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 995 996 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 997 IAP_F_CA | IAP_F_CC2), 998 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 999 1000 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1001 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1002 1003 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1004 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1005 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1006 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1007 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1008 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1009 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB), 1010 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB), 1011 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB), 1012 1013 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1014 1015 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1016 1017 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1018 1019 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1020 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1021 1022 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1023 1024 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1025 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1026 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1027 IAP_F_WM | IAP_F_SB | IAP_F_IB), 1028 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1029 IAP_F_WM), 1030 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1031 1032 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1033 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1034 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1035 1036 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1037 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1038 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1039 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1040 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1041 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1042 1043 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1044 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1045 1046 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1047 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1048 IAP_F_SB | IAP_F_IB), 1049 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1050 IAP_F_SB | IAP_F_IB), 1051 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1052 IAP_F_SB | IAP_F_IB), 1053 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB), 1054 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), 1055 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), 1056 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1057 1058 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1059 1060 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1061 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1062 IAP_F_SB | IAP_F_IB), 1063 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1064 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1065 IAP_F_SB | IAP_F_IB), 1066 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1067 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1068 1069 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1070 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1071 IAP_F_SB | IAP_F_IB), 1072 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1073 IAP_F_SB | IAP_F_IB), 1074 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1075 IAP_F_SB | IAP_F_IB), 1076 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1077 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1078 IAP_F_SB | IAP_F_IB), 1079 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1080 IAP_F_SB | IAP_F_IB), 1081 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1082 IAP_F_SB | IAP_F_IB), 1083 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1084 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1085 IAP_F_SB | IAP_F_IB), 1086 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1087 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1088 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1089 1090 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1091 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1092 IAP_F_SB | IAP_F_IB), 1093 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1094 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1095 IAP_F_SB | IAP_F_IB), 1096 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1097 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1098 IAP_F_SB | IAP_F_IB), 1099 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1100 IAP_F_SB | IAP_F_IB), 1101 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1102 IAP_F_SB | IAP_F_IB), 1103 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1104 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1105 IAP_F_SB | IAP_F_IB), 1106 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1107 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1108 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1109 1110 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1111 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1112 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1113 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1114 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1115 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1116 1117 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1118 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1119 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1120 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1121 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1122 1123 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1124 1125 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1126 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1127 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1128 1129 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1130 IAP_F_SB | IAP_F_IB), 1131 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1132 IAP_F_SB | IAP_F_IB), 1133 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1134 IAP_F_SB | IAP_F_IB), 1135 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1136 IAP_F_SB | IAP_F_IB), 1137 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1138 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1139 IAP_F_SB | IAP_F_IB), 1140 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1141 IAP_F_SB | IAP_F_IB), 1142 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1143 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1144 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1145 1146 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1147 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1148 IAP_F_SB | IAP_F_IB), 1149 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1150 IAP_F_SB), 1151 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1152 IAP_F_SB | IAP_F_IB), 1153 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1154 IAP_F_SB | IAP_F_IB), 1155 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1156 IAP_F_SB | IAP_F_IB), 1157 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1158 IAP_F_SB), 1159 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1160 IAP_F_SB), 1161 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1162 IAP_F_SB), 1163 1164 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1165 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1166 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1167 1168 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1169 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1170 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1171 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1172 1173 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1174 IAP_F_SB | IAP_F_IB), 1175 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1176 IAP_F_SB | IAP_F_IB), 1177 1178 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB), 1179 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1180 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB), 1181 1182 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1183 IAP_F_SB | IAP_F_IB | IAP_F_IB), 1184 1185 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1186 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1187 IAP_F_SB | IAP_F_IB), 1188 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB), 1189 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1190 IAP_F_SB | IAP_F_IB), 1191 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1192 IAP_F_SB | IAP_F_IB), 1193 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1194 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1195 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1196 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1197 1198 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1199 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1200 IAP_F_SB | IAP_F_IB), 1201 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1202 IAP_F_SB | IAP_F_IB), 1203 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1204 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1205 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1206 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1207 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1208 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1209 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1210 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1211 IAP_F_WM), 1212 1213 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1214 IAP_F_SB), 1215 1216 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1217 IAP_F_WM | IAP_F_I7O), 1218 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1219 IAP_F_WM | IAP_F_I7O), 1220 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1221 IAP_F_WM | IAP_F_I7O), 1222 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1223 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1224 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1225 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1226 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1227 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1228 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1229 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1230 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1231 1232 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1233 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1234 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1235 1236 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB), 1237 1238 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1239 IAP_F_SB | IAP_F_IB), 1240 1241 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1242 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1243 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1244 1245 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1246 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1247 1248 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1249 IAP_F_SB | IAP_F_IB), 1250 1251 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1252 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1253 1254 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB), 1255 1256 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1257 IAP_F_SB | IAP_F_IB), 1258 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1259 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1260 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1261 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1262 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1263 IAP_F_I7 | IAP_F_WM), 1264 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1265 1266 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1267 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1268 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB), 1269 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1270 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1271 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1272 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1273 1274 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1275 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1276 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1277 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1278 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1279 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1280 IAP_F_I7 | IAP_F_WM), 1281 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1282 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1283 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1284 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1285 1286 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1287 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1288 IAP_F_I7 | IAP_F_WM), 1289 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1290 IAP_F_SB | IAP_F_IB), 1291 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1292 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1293 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1294 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1295 1296 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1297 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1298 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1299 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1300 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1301 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1302 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1303 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1304 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1305 IAP_F_SB | IAP_F_IB), 1306 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1307 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1308 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1309 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1310 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1311 1312 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1313 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1314 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1315 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1316 IAP_F_SB | IAP_F_IB), 1317 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1318 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1319 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1320 1321 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1322 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1323 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1324 1325 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1326 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1327 IAP_F_I7 | IAP_F_WM), 1328 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1329 IAP_F_I7 | IAP_F_WM), 1330 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1331 IAP_F_I7 | IAP_F_WM), 1332 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1333 IAP_F_I7 | IAP_F_WM), 1334 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1335 IAP_F_I7 | IAP_F_WM), 1336 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1337 1338 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1339 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1340 1341 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1342 1343 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1344 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1345 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1346 IAP_F_SB | IAP_F_IB), 1347 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1348 IAP_F_SB | IAP_F_IB), 1349 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1350 IAP_F_SB | IAP_F_IB), 1351 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1352 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1353 1354 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1355 IAP_F_I7 | IAP_F_WM), 1356 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1357 IAP_F_I7 | IAP_F_WM), 1358 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1359 IAP_F_I7 | IAP_F_WM), 1360 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1361 IAP_F_I7 | IAP_F_WM), 1362 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1363 IAP_F_WM), 1364 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1365 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1366 1367 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1368 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1369 IAP_F_I7 | IAP_F_WM), 1370 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1371 IAP_F_I7 | IAP_F_WM), 1372 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1373 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1374 1375 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1376 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1377 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1378 1379 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1380 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1381 1382 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1383 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1384 IAP_F_SB | IAP_F_IB), 1385 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1386 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1387 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1388 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1389 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1390 1391 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1392 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1393 IAP_F_SB | IAP_F_IB), 1394 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1395 IAP_F_SB | IAP_F_IB), 1396 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1397 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1398 1399 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1400 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1401 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1402 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1403 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1404 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1405 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1406 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), 1407 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1408 IAP_F_I7 | IAP_F_WM), 1409 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1410 1411 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB), 1412 1413 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1414 IAP_F_I7 | IAP_F_WM), 1415 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1416 IAP_F_SB), 1417 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1418 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1419 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1420 1421 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1422 IAP_F_I7 | IAP_F_WM), 1423 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1424 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1425 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1426 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1427 1428 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1429 1430 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1431 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1432 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1433 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1434 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1435 1436 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1437 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1438 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1439 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1440 1441 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1442 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1443 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1444 1445 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1446 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1447 1448 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1449 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1450 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1451 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1452 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1453 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1454 1455 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1456 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1457 IAP_F_WM), 1458 1459 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1460 1461 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1462 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1463 1464 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1465 1466 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1467 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1468 IAP_F_WM), 1469 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1470 1471 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1472 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1473 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1474 1475 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1476 1477 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1478 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1479 IAP_F_SB | IAP_F_IB), 1480 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1481 IAP_F_SB | IAP_F_IB), 1482 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1483 IAP_F_SB | IAP_F_IB), 1484 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1485 IAP_F_SB | IAP_F_IB), 1486 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1487 IAP_F_SB | IAP_F_IB), 1488 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1489 IAP_F_SB | IAP_F_IB), 1490 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1491 IAP_F_SB | IAP_F_IB), 1492 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1493 IAP_F_SB | IAP_F_IB), 1494 1495 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 1496 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1497 IAP_F_SB | IAP_F_IB), 1498 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1499 IAP_F_SB | IAP_F_IB), 1500 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1501 IAP_F_SB | IAP_F_IB), 1502 1503 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1504 IAP_F_SB | IAP_F_IB), 1505 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1506 IAP_F_SB | IAP_F_IB), 1507 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1508 IAP_F_SB | IAP_F_IB), 1509 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1510 IAP_F_SB | IAP_F_IB), 1511 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB), 1512 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1513 1514 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1515 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1516 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1517 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1518 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1519 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1520 1521 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1522 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1523 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1524 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1525 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1526 IAP_F_SB), 1527 1528 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1529 1530 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1531 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1532 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1533 1534 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1535 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1536 1537 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1538 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1539 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1540 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1541 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1542 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1543 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1544}; 1545 1546static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1547 1548static pmc_value_t 1549iap_perfctr_value_to_reload_count(pmc_value_t v) 1550{ 1551 v &= (1ULL << core_iap_width) - 1; 1552 return (1ULL << core_iap_width) - v; 1553} 1554 1555static pmc_value_t 1556iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1557{ 1558 return (1ULL << core_iap_width) - rlc; 1559} 1560 1561static int 1562iap_pmc_has_overflowed(int ri) 1563{ 1564 uint64_t v; 1565 1566 /* 1567 * We treat a Core (i.e., Intel architecture v1) PMC as has 1568 * having overflowed if its MSB is zero. 1569 */ 1570 v = rdpmc(ri); 1571 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1572} 1573 1574/* 1575 * Check an event against the set of supported architectural events. 1576 * 1577 * Returns 1 if the event is architectural and unsupported on this 1578 * CPU. Returns 0 otherwise. 1579 */ 1580 1581static int 1582iap_architectural_event_is_unsupported(enum pmc_event pe) 1583{ 1584 enum core_arch_events ae; 1585 1586 switch (pe) { 1587 case PMC_EV_IAP_EVENT_3CH_00H: 1588 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1589 break; 1590 case PMC_EV_IAP_EVENT_C0H_00H: 1591 ae = CORE_AE_INSTRUCTION_RETIRED; 1592 break; 1593 case PMC_EV_IAP_EVENT_3CH_01H: 1594 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1595 break; 1596 case PMC_EV_IAP_EVENT_2EH_4FH: 1597 ae = CORE_AE_LLC_REFERENCE; 1598 break; 1599 case PMC_EV_IAP_EVENT_2EH_41H: 1600 ae = CORE_AE_LLC_MISSES; 1601 break; 1602 case PMC_EV_IAP_EVENT_C4H_00H: 1603 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1604 break; 1605 case PMC_EV_IAP_EVENT_C5H_00H: 1606 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1607 break; 1608 1609 default: /* Non architectural event. */ 1610 return (0); 1611 } 1612 1613 return ((core_architectural_events & (1 << ae)) == 0); 1614} 1615 1616static int 1617iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1618{ 1619 uint32_t mask; 1620 1621 switch (pe) { 1622 /* 1623 * Events valid only on counter 0, 1. 1624 */ 1625 case PMC_EV_IAP_EVENT_40H_01H: 1626 case PMC_EV_IAP_EVENT_40H_02H: 1627 case PMC_EV_IAP_EVENT_40H_04H: 1628 case PMC_EV_IAP_EVENT_40H_08H: 1629 case PMC_EV_IAP_EVENT_40H_0FH: 1630 case PMC_EV_IAP_EVENT_41H_02H: 1631 case PMC_EV_IAP_EVENT_41H_04H: 1632 case PMC_EV_IAP_EVENT_41H_08H: 1633 case PMC_EV_IAP_EVENT_42H_01H: 1634 case PMC_EV_IAP_EVENT_42H_02H: 1635 case PMC_EV_IAP_EVENT_42H_04H: 1636 case PMC_EV_IAP_EVENT_42H_08H: 1637 case PMC_EV_IAP_EVENT_43H_01H: 1638 case PMC_EV_IAP_EVENT_43H_02H: 1639 case PMC_EV_IAP_EVENT_51H_01H: 1640 case PMC_EV_IAP_EVENT_51H_02H: 1641 case PMC_EV_IAP_EVENT_51H_04H: 1642 case PMC_EV_IAP_EVENT_51H_08H: 1643 case PMC_EV_IAP_EVENT_63H_01H: 1644 case PMC_EV_IAP_EVENT_63H_02H: 1645 mask = 0x3; 1646 break; 1647 1648 default: 1649 mask = ~0; /* Any row index is ok. */ 1650 } 1651 1652 return (mask & (1 << ri)); 1653} 1654 1655static int 1656iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1657{ 1658 uint32_t mask; 1659 1660 switch (pe) { 1661 /* 1662 * Events valid only on counter 0. 1663 */ 1664 case PMC_EV_IAP_EVENT_60H_01H: 1665 case PMC_EV_IAP_EVENT_60H_02H: 1666 case PMC_EV_IAP_EVENT_60H_04H: 1667 case PMC_EV_IAP_EVENT_60H_08H: 1668 case PMC_EV_IAP_EVENT_B3H_01H: 1669 case PMC_EV_IAP_EVENT_B3H_02H: 1670 case PMC_EV_IAP_EVENT_B3H_04H: 1671 mask = 0x1; 1672 break; 1673 1674 /* 1675 * Events valid only on counter 0, 1. 1676 */ 1677 case PMC_EV_IAP_EVENT_4CH_01H: 1678 case PMC_EV_IAP_EVENT_4EH_01H: 1679 case PMC_EV_IAP_EVENT_4EH_02H: 1680 case PMC_EV_IAP_EVENT_4EH_04H: 1681 case PMC_EV_IAP_EVENT_51H_01H: 1682 case PMC_EV_IAP_EVENT_51H_02H: 1683 case PMC_EV_IAP_EVENT_51H_04H: 1684 case PMC_EV_IAP_EVENT_51H_08H: 1685 case PMC_EV_IAP_EVENT_63H_01H: 1686 case PMC_EV_IAP_EVENT_63H_02H: 1687 mask = 0x3; 1688 break; 1689 1690 default: 1691 mask = ~0; /* Any row index is ok. */ 1692 } 1693 1694 return (mask & (1 << ri)); 1695} 1696 1697static int 1698iap_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri) 1699{ 1700 uint32_t mask; 1701 1702 switch (pe) { 1703 /* 1704 * Events valid only on counter 2. 1705 */ 1706 case PMC_EV_IAP_EVENT_48H_01H: 1707 mask = 0x4; 1708 break; 1709 default: 1710 mask = ~0; /* Any row index is ok. */ 1711 } 1712 1713 return (mask & (1 << ri)); 1714} 1715 1716static int 1717iap_event_ivybridge_ok_on_counter(enum pmc_event pe, int ri) 1718{ 1719 uint32_t mask; 1720 1721 switch (pe) { 1722 /* 1723 * Events valid only on counter 2. 1724 */ 1725 case PMC_EV_IAP_EVENT_48H_01H: 1726 mask = 0x4; 1727 break; 1728 default: 1729 mask = ~0; /* Any row index is ok. */ 1730 } 1731 1732 return (mask & (1 << ri)); 1733} 1734 1735static int 1736iap_event_ok_on_counter(enum pmc_event pe, int ri) 1737{ 1738 uint32_t mask; 1739 1740 switch (pe) { 1741 /* 1742 * Events valid only on counter 0. 1743 */ 1744 case PMC_EV_IAP_EVENT_10H_00H: 1745 case PMC_EV_IAP_EVENT_14H_00H: 1746 case PMC_EV_IAP_EVENT_18H_00H: 1747 case PMC_EV_IAP_EVENT_B3H_01H: 1748 case PMC_EV_IAP_EVENT_B3H_02H: 1749 case PMC_EV_IAP_EVENT_B3H_04H: 1750 case PMC_EV_IAP_EVENT_C1H_00H: 1751 case PMC_EV_IAP_EVENT_CBH_01H: 1752 case PMC_EV_IAP_EVENT_CBH_02H: 1753 mask = (1 << 0); 1754 break; 1755 1756 /* 1757 * Events valid only on counter 1. 1758 */ 1759 case PMC_EV_IAP_EVENT_11H_00H: 1760 case PMC_EV_IAP_EVENT_12H_00H: 1761 case PMC_EV_IAP_EVENT_13H_00H: 1762 mask = (1 << 1); 1763 break; 1764 1765 default: 1766 mask = ~0; /* Any row index is ok. */ 1767 } 1768 1769 return (mask & (1 << ri)); 1770} 1771 1772static int 1773iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1774 const struct pmc_op_pmcallocate *a) 1775{ 1776 int n, model; 1777 enum pmc_event ev; 1778 struct iap_event_descr *ie; 1779 uint32_t c, caps, config, cpuflag, evsel, mask; 1780 1781 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1782 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1783 KASSERT(ri >= 0 && ri < core_iap_npmc, 1784 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1785 1786 /* check requested capabilities */ 1787 caps = a->pm_caps; 1788 if ((IAP_PMC_CAPS & caps) != caps) 1789 return (EPERM); 1790 1791 ev = pm->pm_event; 1792 1793 if (iap_architectural_event_is_unsupported(ev)) 1794 return (EOPNOTSUPP); 1795 1796 /* 1797 * A small number of events are not supported in all the 1798 * processors based on a given microarchitecture. 1799 */ 1800 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 1801 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 1802 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 1803 return (EINVAL); 1804 } 1805 1806 switch (core_cputype) { 1807 case PMC_CPU_INTEL_COREI7: 1808 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1809 return (EINVAL); 1810 break; 1811 case PMC_CPU_INTEL_IVYBRIDGE: 1812 if (iap_event_ivybridge_ok_on_counter(ev, ri) == 0) 1813 return (EINVAL); 1814 break; 1815 case PMC_CPU_INTEL_SANDYBRIDGE: 1816 if (iap_event_sandybridge_ok_on_counter(ev, ri) == 0) 1817 return (EINVAL); 1818 break; 1819 case PMC_CPU_INTEL_WESTMERE: 1820 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1821 return (EINVAL); 1822 break; 1823 default: 1824 if (iap_event_ok_on_counter(ev, ri) == 0) 1825 return (EINVAL); 1826 } 1827 1828 /* 1829 * Look for an event descriptor with matching CPU and event id 1830 * fields. 1831 */ 1832 1833 switch (core_cputype) { 1834 default: 1835 case PMC_CPU_INTEL_ATOM: 1836 cpuflag = IAP_F_CA; 1837 break; 1838 case PMC_CPU_INTEL_CORE: 1839 cpuflag = IAP_F_CC; 1840 break; 1841 case PMC_CPU_INTEL_CORE2: 1842 cpuflag = IAP_F_CC2; 1843 break; 1844 case PMC_CPU_INTEL_CORE2EXTREME: 1845 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1846 break; 1847 case PMC_CPU_INTEL_COREI7: 1848 cpuflag = IAP_F_I7; 1849 break; 1850 case PMC_CPU_INTEL_IVYBRIDGE: 1851 cpuflag = IAP_F_IB; 1852 break; 1853 case PMC_CPU_INTEL_SANDYBRIDGE: 1854 cpuflag = IAP_F_SB; 1855 break; 1856 case PMC_CPU_INTEL_WESTMERE: 1857 cpuflag = IAP_F_WM; 1858 break; 1859 } 1860 1861 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1862 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1863 break; 1864 1865 if (n == niap_events) 1866 return (EINVAL); 1867 1868 /* 1869 * A matching event descriptor has been found, so start 1870 * assembling the contents of the event select register. 1871 */ 1872 evsel = ie->iap_evcode; 1873 1874 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1875 1876 /* 1877 * If the event uses a fixed umask value, reject any umask 1878 * bits set by the user. 1879 */ 1880 if (ie->iap_flags & IAP_F_FM) { 1881 1882 if (IAP_UMASK(config) != 0) 1883 return (EINVAL); 1884 1885 evsel |= (ie->iap_umask << 8); 1886 1887 } else { 1888 1889 /* 1890 * Otherwise, the UMASK value needs to be taken from 1891 * the MD fields of the allocation request. Reject 1892 * requests that specify reserved bits. 1893 */ 1894 1895 mask = 0; 1896 1897 if (ie->iap_umask & IAP_M_CORE) { 1898 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1899 c != IAP_CORE_THIS) 1900 return (EINVAL); 1901 mask |= IAP_F_CORE; 1902 } 1903 1904 if (ie->iap_umask & IAP_M_AGENT) 1905 mask |= IAP_F_AGENT; 1906 1907 if (ie->iap_umask & IAP_M_PREFETCH) { 1908 1909 if ((c = (config & IAP_F_PREFETCH)) == 1910 IAP_PREFETCH_RESERVED) 1911 return (EINVAL); 1912 1913 mask |= IAP_F_PREFETCH; 1914 } 1915 1916 if (ie->iap_umask & IAP_M_MESI) 1917 mask |= IAP_F_MESI; 1918 1919 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 1920 mask |= IAP_F_SNOOPRESPONSE; 1921 1922 if (ie->iap_umask & IAP_M_SNOOPTYPE) 1923 mask |= IAP_F_SNOOPTYPE; 1924 1925 if (ie->iap_umask & IAP_M_TRANSITION) 1926 mask |= IAP_F_TRANSITION; 1927 1928 /* 1929 * If bits outside of the allowed set of umask bits 1930 * are set, reject the request. 1931 */ 1932 if (config & ~mask) 1933 return (EINVAL); 1934 1935 evsel |= (config & mask); 1936 1937 } 1938 1939 /* 1940 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 1941 */ 1942 if (core_cputype == PMC_CPU_INTEL_ATOM || 1943 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE) 1944 evsel |= (config & IAP_ANY); 1945 else if (config & IAP_ANY) 1946 return (EINVAL); 1947 1948 /* 1949 * Check offcore response configuration. 1950 */ 1951 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 1952 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 1953 ev != PMC_EV_IAP_EVENT_BBH_01H) 1954 return (EINVAL); 1955 if (core_cputype == PMC_CPU_INTEL_COREI7 && 1956 ev == PMC_EV_IAP_EVENT_BBH_01H) 1957 return (EINVAL); 1958 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 1959 core_cputype == PMC_CPU_INTEL_WESTMERE) && 1960 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 1961 return (EINVAL); 1962 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 1963 core_cputype == PMC_CPU_INTEL_IVYBRIDGE) && 1964 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 1965 return (EINVAL); 1966 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 1967 } 1968 1969 if (caps & PMC_CAP_THRESHOLD) 1970 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 1971 if (caps & PMC_CAP_USER) 1972 evsel |= IAP_USR; 1973 if (caps & PMC_CAP_SYSTEM) 1974 evsel |= IAP_OS; 1975 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 1976 evsel |= (IAP_OS | IAP_USR); 1977 if (caps & PMC_CAP_EDGE) 1978 evsel |= IAP_EDGE; 1979 if (caps & PMC_CAP_INVERT) 1980 evsel |= IAP_INV; 1981 if (caps & PMC_CAP_INTERRUPT) 1982 evsel |= IAP_INT; 1983 1984 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 1985 1986 return (0); 1987} 1988 1989static int 1990iap_config_pmc(int cpu, int ri, struct pmc *pm) 1991{ 1992 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1993 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1994 1995 KASSERT(ri >= 0 && ri < core_iap_npmc, 1996 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1997 1998 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 1999 2000 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2001 cpu)); 2002 2003 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2004 2005 return (0); 2006} 2007 2008static int 2009iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2010{ 2011 int error; 2012 struct pmc_hw *phw; 2013 char iap_name[PMC_NAME_MAX]; 2014 2015 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2016 2017 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2018 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2019 NULL)) != 0) 2020 return (error); 2021 2022 pi->pm_class = PMC_CLASS_IAP; 2023 2024 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2025 pi->pm_enabled = TRUE; 2026 *ppmc = phw->phw_pmc; 2027 } else { 2028 pi->pm_enabled = FALSE; 2029 *ppmc = NULL; 2030 } 2031 2032 return (0); 2033} 2034 2035static int 2036iap_get_config(int cpu, int ri, struct pmc **ppm) 2037{ 2038 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2039 2040 return (0); 2041} 2042 2043static int 2044iap_get_msr(int ri, uint32_t *msr) 2045{ 2046 KASSERT(ri >= 0 && ri < core_iap_npmc, 2047 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2048 2049 *msr = ri; 2050 2051 return (0); 2052} 2053 2054static int 2055iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2056{ 2057 struct pmc *pm; 2058 pmc_value_t tmp; 2059 2060 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2061 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2062 KASSERT(ri >= 0 && ri < core_iap_npmc, 2063 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2064 2065 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2066 2067 KASSERT(pm, 2068 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2069 ri)); 2070 2071 tmp = rdpmc(ri); 2072 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2073 *v = iap_perfctr_value_to_reload_count(tmp); 2074 else 2075 *v = tmp & ((1ULL << core_iap_width) - 1); 2076 2077 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2078 ri, *v); 2079 2080 return (0); 2081} 2082 2083static int 2084iap_release_pmc(int cpu, int ri, struct pmc *pm) 2085{ 2086 (void) pm; 2087 2088 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2089 pm); 2090 2091 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2092 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2093 KASSERT(ri >= 0 && ri < core_iap_npmc, 2094 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2095 2096 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2097 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2098 2099 return (0); 2100} 2101 2102static int 2103iap_start_pmc(int cpu, int ri) 2104{ 2105 struct pmc *pm; 2106 uint32_t evsel; 2107 struct core_cpu *cc; 2108 2109 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2110 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2111 KASSERT(ri >= 0 && ri < core_iap_npmc, 2112 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2113 2114 cc = core_pcpu[cpu]; 2115 pm = cc->pc_corepmcs[ri].phw_pmc; 2116 2117 KASSERT(pm, 2118 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2119 __LINE__, cpu, ri)); 2120 2121 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2122 2123 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2124 2125 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2126 cpu, ri, IAP_EVSEL0 + ri, evsel); 2127 2128 /* Event specific configuration. */ 2129 switch (pm->pm_event) { 2130 case PMC_EV_IAP_EVENT_B7H_01H: 2131 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2132 break; 2133 case PMC_EV_IAP_EVENT_BBH_01H: 2134 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2135 break; 2136 default: 2137 break; 2138 } 2139 2140 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2141 2142 if (core_cputype == PMC_CPU_INTEL_CORE) 2143 return (0); 2144 2145 do { 2146 cc->pc_resync = 0; 2147 cc->pc_globalctrl |= (1ULL << ri); 2148 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2149 } while (cc->pc_resync != 0); 2150 2151 return (0); 2152} 2153 2154static int 2155iap_stop_pmc(int cpu, int ri) 2156{ 2157 struct pmc *pm; 2158 struct core_cpu *cc; 2159 uint64_t msr; 2160 2161 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2162 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2163 KASSERT(ri >= 0 && ri < core_iap_npmc, 2164 ("[core,%d] illegal row index %d", __LINE__, ri)); 2165 2166 cc = core_pcpu[cpu]; 2167 pm = cc->pc_corepmcs[ri].phw_pmc; 2168 2169 KASSERT(pm, 2170 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2171 cpu, ri)); 2172 2173 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2174 2175 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2176 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2177 2178 if (core_cputype == PMC_CPU_INTEL_CORE) 2179 return (0); 2180 2181 msr = 0; 2182 do { 2183 cc->pc_resync = 0; 2184 cc->pc_globalctrl &= ~(1ULL << ri); 2185 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2186 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2187 } while (cc->pc_resync != 0); 2188 2189 return (0); 2190} 2191 2192static int 2193iap_write_pmc(int cpu, int ri, pmc_value_t v) 2194{ 2195 struct pmc *pm; 2196 struct core_cpu *cc; 2197 2198 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2199 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2200 KASSERT(ri >= 0 && ri < core_iap_npmc, 2201 ("[core,%d] illegal row index %d", __LINE__, ri)); 2202 2203 cc = core_pcpu[cpu]; 2204 pm = cc->pc_corepmcs[ri].phw_pmc; 2205 2206 KASSERT(pm, 2207 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2208 cpu, ri)); 2209 2210 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2211 IAP_PMC0 + ri, v); 2212 2213 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2214 v = iap_reload_count_to_perfctr_value(v); 2215 2216 /* 2217 * Write the new value to the counter. The counter will be in 2218 * a stopped state when the pcd_write() entry point is called. 2219 */ 2220 2221 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2222 2223 return (0); 2224} 2225 2226 2227static void 2228iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2229 int flags) 2230{ 2231 struct pmc_classdep *pcd; 2232 2233 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2234 2235 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2236 2237 /* Remember the set of architectural events supported. */ 2238 core_architectural_events = ~flags; 2239 2240 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2241 2242 pcd->pcd_caps = IAP_PMC_CAPS; 2243 pcd->pcd_class = PMC_CLASS_IAP; 2244 pcd->pcd_num = npmc; 2245 pcd->pcd_ri = md->pmd_npmc; 2246 pcd->pcd_width = pmcwidth; 2247 2248 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2249 pcd->pcd_config_pmc = iap_config_pmc; 2250 pcd->pcd_describe = iap_describe; 2251 pcd->pcd_get_config = iap_get_config; 2252 pcd->pcd_get_msr = iap_get_msr; 2253 pcd->pcd_pcpu_fini = core_pcpu_fini; 2254 pcd->pcd_pcpu_init = core_pcpu_init; 2255 pcd->pcd_read_pmc = iap_read_pmc; 2256 pcd->pcd_release_pmc = iap_release_pmc; 2257 pcd->pcd_start_pmc = iap_start_pmc; 2258 pcd->pcd_stop_pmc = iap_stop_pmc; 2259 pcd->pcd_write_pmc = iap_write_pmc; 2260 2261 md->pmd_npmc += npmc; 2262} 2263 2264static int 2265core_intr(int cpu, struct trapframe *tf) 2266{ 2267 pmc_value_t v; 2268 struct pmc *pm; 2269 struct core_cpu *cc; 2270 int error, found_interrupt, ri; 2271 uint64_t msr; 2272 2273 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2274 TRAPF_USERMODE(tf)); 2275 2276 found_interrupt = 0; 2277 cc = core_pcpu[cpu]; 2278 2279 for (ri = 0; ri < core_iap_npmc; ri++) { 2280 2281 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2282 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2283 continue; 2284 2285 if (!iap_pmc_has_overflowed(ri)) 2286 continue; 2287 2288 found_interrupt = 1; 2289 2290 if (pm->pm_state != PMC_STATE_RUNNING) 2291 continue; 2292 2293 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2294 TRAPF_USERMODE(tf)); 2295 2296 v = pm->pm_sc.pm_reloadcount; 2297 v = iaf_reload_count_to_perfctr_value(v); 2298 2299 /* 2300 * Stop the counter, reload it but only restart it if 2301 * the PMC is not stalled. 2302 */ 2303 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2304 wrmsr(IAP_EVSEL0 + ri, msr); 2305 wrmsr(IAP_PMC0 + ri, v); 2306 2307 if (error) 2308 continue; 2309 2310 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2311 IAP_EN)); 2312 } 2313 2314 if (found_interrupt) 2315 lapic_reenable_pmc(); 2316 2317 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2318 &pmc_stats.pm_intr_ignored, 1); 2319 2320 return (found_interrupt); 2321} 2322 2323static int 2324core2_intr(int cpu, struct trapframe *tf) 2325{ 2326 int error, found_interrupt, n; 2327 uint64_t flag, intrstatus, intrenable, msr; 2328 struct pmc *pm; 2329 struct core_cpu *cc; 2330 pmc_value_t v; 2331 2332 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2333 TRAPF_USERMODE(tf)); 2334 2335 /* 2336 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2337 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2338 * the current set of interrupting PMCs and process these 2339 * after stopping them. 2340 */ 2341 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2342 intrenable = intrstatus & core_pmcmask; 2343 2344 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2345 (uintmax_t) intrstatus); 2346 2347 found_interrupt = 0; 2348 cc = core_pcpu[cpu]; 2349 2350 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2351 2352 cc->pc_globalctrl &= ~intrenable; 2353 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2354 2355 /* 2356 * Stop PMCs and clear overflow status bits. 2357 */ 2358 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2359 wrmsr(IA_GLOBAL_CTRL, msr); 2360 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2361 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2362 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2363 2364 /* 2365 * Look for interrupts from fixed function PMCs. 2366 */ 2367 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2368 n++, flag <<= 1) { 2369 2370 if ((intrstatus & flag) == 0) 2371 continue; 2372 2373 found_interrupt = 1; 2374 2375 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2376 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2377 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2378 continue; 2379 2380 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2381 TRAPF_USERMODE(tf)); 2382 if (error) 2383 intrenable &= ~flag; 2384 2385 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2386 2387 /* Reload sampling count. */ 2388 wrmsr(IAF_CTR0 + n, v); 2389 2390 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2391 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2392 } 2393 2394 /* 2395 * Process interrupts from the programmable counters. 2396 */ 2397 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2398 if ((intrstatus & flag) == 0) 2399 continue; 2400 2401 found_interrupt = 1; 2402 2403 pm = cc->pc_corepmcs[n].phw_pmc; 2404 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2405 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2406 continue; 2407 2408 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2409 TRAPF_USERMODE(tf)); 2410 if (error) 2411 intrenable &= ~flag; 2412 2413 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2414 2415 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2416 (uintmax_t) v); 2417 2418 /* Reload sampling count. */ 2419 wrmsr(IAP_PMC0 + n, v); 2420 } 2421 2422 /* 2423 * Reenable all non-stalled PMCs. 2424 */ 2425 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2426 (uintmax_t) intrenable); 2427 2428 cc->pc_globalctrl |= intrenable; 2429 2430 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2431 2432 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2433 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2434 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2435 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2436 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2437 2438 if (found_interrupt) 2439 lapic_reenable_pmc(); 2440 2441 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2442 &pmc_stats.pm_intr_ignored, 1); 2443 2444 return (found_interrupt); 2445} 2446 2447int 2448pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2449{ 2450 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2451 int ipa_version, flags, nflags; 2452 2453 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2454 2455 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2456 2457 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2458 md->pmd_cputype, maxcpu, ipa_version); 2459 2460 if (ipa_version < 1 || ipa_version > 3) { 2461 /* Unknown PMC architecture. */ 2462 printf("hwpc_core: unknown PMC architecture: %d\n", 2463 ipa_version); 2464 return (EPROGMISMATCH); 2465 } 2466 2467 core_cputype = md->pmd_cputype; 2468 2469 core_pmcmask = 0; 2470 2471 /* 2472 * Initialize programmable counters. 2473 */ 2474 KASSERT(ipa_version >= 1, 2475 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2476 2477 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2478 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2479 2480 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2481 2482 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2483 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2484 2485 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2486 2487 /* 2488 * Initialize fixed function counters, if present. 2489 */ 2490 if (core_cputype != PMC_CPU_INTEL_CORE) { 2491 KASSERT(ipa_version >= 2, 2492 ("[core,%d] ipa_version %d too small", __LINE__, 2493 ipa_version)); 2494 2495 core_iaf_ri = core_iap_npmc; 2496 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2497 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2498 2499 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2500 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2501 } 2502 2503 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2504 core_iaf_ri); 2505 2506 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2507 M_ZERO | M_WAITOK); 2508 2509 /* 2510 * Choose the appropriate interrupt handler. 2511 */ 2512 if (ipa_version == 1) 2513 md->pmd_intr = core_intr; 2514 else 2515 md->pmd_intr = core2_intr; 2516 2517 md->pmd_pcpu_fini = NULL; 2518 md->pmd_pcpu_init = NULL; 2519 2520 return (0); 2521} 2522 2523void 2524pmc_core_finalize(struct pmc_mdep *md) 2525{ 2526 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2527 2528 free(core_pcpu, M_PMC); 2529 core_pcpu = NULL; 2530} 2531