hwpmc_core.c revision 234930
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 234930 2012-05-02 16:23:36Z gnn $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#include <machine/apicvar.h> 42#include <machine/cpu.h> 43#include <machine/cpufunc.h> 44#include <machine/md_var.h> 45#include <machine/specialreg.h> 46 47#define CORE_CPUID_REQUEST 0xA 48#define CORE_CPUID_REQUEST_SIZE 0x4 49#define CORE_CPUID_EAX 0x0 50#define CORE_CPUID_EBX 0x1 51#define CORE_CPUID_ECX 0x2 52#define CORE_CPUID_EDX 0x3 53 54#define IAF_PMC_CAPS \ 55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 56 PMC_CAP_USER | PMC_CAP_SYSTEM) 57#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 58 59#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 62 63/* 64 * "Architectural" events defined by Intel. The values of these 65 * symbols correspond to positions in the bitmask returned by 66 * the CPUID.0AH instruction. 67 */ 68enum core_arch_events { 69 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 70 CORE_AE_BRANCH_MISSES_RETIRED = 6, 71 CORE_AE_INSTRUCTION_RETIRED = 1, 72 CORE_AE_LLC_MISSES = 4, 73 CORE_AE_LLC_REFERENCE = 3, 74 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 75 CORE_AE_UNHALTED_CORE_CYCLES = 0 76}; 77 78static enum pmc_cputype core_cputype; 79 80struct core_cpu { 81 volatile uint32_t pc_resync; 82 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 83 volatile uint64_t pc_globalctrl; /* Global control register. */ 84 struct pmc_hw pc_corepmcs[]; 85}; 86 87static struct core_cpu **core_pcpu; 88 89static uint32_t core_architectural_events; 90static uint64_t core_pmcmask; 91 92static int core_iaf_ri; /* relative index of fixed counters */ 93static int core_iaf_width; 94static int core_iaf_npmc; 95 96static int core_iap_width; 97static int core_iap_npmc; 98 99static int 100core_pcpu_noop(struct pmc_mdep *md, int cpu) 101{ 102 (void) md; 103 (void) cpu; 104 return (0); 105} 106 107static int 108core_pcpu_init(struct pmc_mdep *md, int cpu) 109{ 110 struct pmc_cpu *pc; 111 struct core_cpu *cc; 112 struct pmc_hw *phw; 113 int core_ri, n, npmc; 114 115 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 116 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 117 118 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 119 120 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 121 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 122 123 if (core_cputype != PMC_CPU_INTEL_CORE) 124 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 125 126 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 127 M_PMC, M_WAITOK | M_ZERO); 128 129 core_pcpu[cpu] = cc; 130 pc = pmc_pcpu[cpu]; 131 132 KASSERT(pc != NULL && cc != NULL, 133 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 134 135 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 136 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 137 PMC_PHW_CPU_TO_STATE(cpu) | 138 PMC_PHW_INDEX_TO_STATE(n + core_ri); 139 phw->phw_pmc = NULL; 140 pc->pc_hwpmcs[n + core_ri] = phw; 141 } 142 143 return (0); 144} 145 146static int 147core_pcpu_fini(struct pmc_mdep *md, int cpu) 148{ 149 int core_ri, n, npmc; 150 struct pmc_cpu *pc; 151 struct core_cpu *cc; 152 uint64_t msr = 0; 153 154 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 155 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 156 157 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 158 159 if ((cc = core_pcpu[cpu]) == NULL) 160 return (0); 161 162 core_pcpu[cpu] = NULL; 163 164 pc = pmc_pcpu[cpu]; 165 166 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 167 cpu)); 168 169 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 170 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 171 172 for (n = 0; n < npmc; n++) { 173 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 174 wrmsr(IAP_EVSEL0 + n, msr); 175 } 176 177 if (core_cputype != PMC_CPU_INTEL_CORE) { 178 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 179 wrmsr(IAF_CTRL, msr); 180 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 181 } 182 183 for (n = 0; n < npmc; n++) 184 pc->pc_hwpmcs[n + core_ri] = NULL; 185 186 free(cc, M_PMC); 187 188 return (0); 189} 190 191/* 192 * Fixed function counters. 193 */ 194 195static pmc_value_t 196iaf_perfctr_value_to_reload_count(pmc_value_t v) 197{ 198 v &= (1ULL << core_iaf_width) - 1; 199 return (1ULL << core_iaf_width) - v; 200} 201 202static pmc_value_t 203iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 204{ 205 return (1ULL << core_iaf_width) - rlc; 206} 207 208static int 209iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 210 const struct pmc_op_pmcallocate *a) 211{ 212 enum pmc_event ev; 213 uint32_t caps, flags, validflags; 214 215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 216 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 217 218 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 219 220 if (ri < 0 || ri > core_iaf_npmc) 221 return (EINVAL); 222 223 caps = a->pm_caps; 224 225 if (a->pm_class != PMC_CLASS_IAF || 226 (caps & IAF_PMC_CAPS) != caps) 227 return (EINVAL); 228 229 ev = pm->pm_event; 230 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 231 return (EINVAL); 232 233 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 234 return (EINVAL); 235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 236 return (EINVAL); 237 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 238 return (EINVAL); 239 240 flags = a->pm_md.pm_iaf.pm_iaf_flags; 241 242 validflags = IAF_MASK; 243 244 if (core_cputype != PMC_CPU_INTEL_ATOM) 245 validflags &= ~IAF_ANY; 246 247 if ((flags & ~validflags) != 0) 248 return (EINVAL); 249 250 if (caps & PMC_CAP_INTERRUPT) 251 flags |= IAF_PMI; 252 if (caps & PMC_CAP_SYSTEM) 253 flags |= IAF_OS; 254 if (caps & PMC_CAP_USER) 255 flags |= IAF_USR; 256 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 257 flags |= (IAF_OS | IAF_USR); 258 259 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 260 261 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 262 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 263 264 return (0); 265} 266 267static int 268iaf_config_pmc(int cpu, int ri, struct pmc *pm) 269{ 270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 271 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 272 273 KASSERT(ri >= 0 && ri < core_iaf_npmc, 274 ("[core,%d] illegal row-index %d", __LINE__, ri)); 275 276 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 277 278 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 279 cpu)); 280 281 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 282 283 return (0); 284} 285 286static int 287iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 288{ 289 int error; 290 struct pmc_hw *phw; 291 char iaf_name[PMC_NAME_MAX]; 292 293 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 294 295 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 296 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 297 NULL)) != 0) 298 return (error); 299 300 pi->pm_class = PMC_CLASS_IAF; 301 302 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 303 pi->pm_enabled = TRUE; 304 *ppmc = phw->phw_pmc; 305 } else { 306 pi->pm_enabled = FALSE; 307 *ppmc = NULL; 308 } 309 310 return (0); 311} 312 313static int 314iaf_get_config(int cpu, int ri, struct pmc **ppm) 315{ 316 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 317 318 return (0); 319} 320 321static int 322iaf_get_msr(int ri, uint32_t *msr) 323{ 324 KASSERT(ri >= 0 && ri < core_iaf_npmc, 325 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 326 327 *msr = IAF_RI_TO_MSR(ri); 328 329 return (0); 330} 331 332static int 333iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 334{ 335 struct pmc *pm; 336 pmc_value_t tmp; 337 338 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 339 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 340 KASSERT(ri >= 0 && ri < core_iaf_npmc, 341 ("[core,%d] illegal row-index %d", __LINE__, ri)); 342 343 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 344 345 KASSERT(pm, 346 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 347 ri, ri + core_iaf_ri)); 348 349 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 350 351 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 352 *v = iaf_perfctr_value_to_reload_count(tmp); 353 else 354 *v = tmp; 355 356 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 357 IAF_RI_TO_MSR(ri), *v); 358 359 return (0); 360} 361 362static int 363iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 364{ 365 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 366 367 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 368 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 369 KASSERT(ri >= 0 && ri < core_iaf_npmc, 370 ("[core,%d] illegal row-index %d", __LINE__, ri)); 371 372 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 373 ("[core,%d] PHW pmc non-NULL", __LINE__)); 374 375 return (0); 376} 377 378static int 379iaf_start_pmc(int cpu, int ri) 380{ 381 struct pmc *pm; 382 struct core_cpu *iafc; 383 uint64_t msr = 0; 384 385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 386 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 387 KASSERT(ri >= 0 && ri < core_iaf_npmc, 388 ("[core,%d] illegal row-index %d", __LINE__, ri)); 389 390 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 391 392 iafc = core_pcpu[cpu]; 393 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 394 395 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 396 397 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 398 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 399 400 do { 401 iafc->pc_resync = 0; 402 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 403 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 404 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 405 IAF_GLOBAL_CTRL_MASK)); 406 } while (iafc->pc_resync != 0); 407 408 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 409 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 410 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 411 412 return (0); 413} 414 415static int 416iaf_stop_pmc(int cpu, int ri) 417{ 418 uint32_t fc; 419 struct core_cpu *iafc; 420 uint64_t msr = 0; 421 422 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 423 424 iafc = core_pcpu[cpu]; 425 426 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 427 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 428 KASSERT(ri >= 0 && ri < core_iaf_npmc, 429 ("[core,%d] illegal row-index %d", __LINE__, ri)); 430 431 fc = (IAF_MASK << (ri * 4)); 432 433 if (core_cputype != PMC_CPU_INTEL_ATOM) 434 fc &= ~IAF_ANY; 435 436 iafc->pc_iafctrl &= ~fc; 437 438 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 439 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 440 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 441 442 do { 443 iafc->pc_resync = 0; 444 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 445 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 446 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 447 IAF_GLOBAL_CTRL_MASK)); 448 } while (iafc->pc_resync != 0); 449 450 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 451 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 452 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 453 454 return (0); 455} 456 457static int 458iaf_write_pmc(int cpu, int ri, pmc_value_t v) 459{ 460 struct core_cpu *cc; 461 struct pmc *pm; 462 uint64_t msr; 463 464 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 465 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 466 KASSERT(ri >= 0 && ri < core_iaf_npmc, 467 ("[core,%d] illegal row-index %d", __LINE__, ri)); 468 469 cc = core_pcpu[cpu]; 470 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 471 472 KASSERT(pm, 473 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 474 475 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 476 v = iaf_reload_count_to_perfctr_value(v); 477 478 /* Turn off fixed counters */ 479 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 480 wrmsr(IAF_CTRL, msr); 481 482 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 483 484 /* Turn on fixed counters */ 485 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 486 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 487 488 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 489 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 490 (uintmax_t) rdmsr(IAF_CTRL), 491 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 492 493 return (0); 494} 495 496 497static void 498iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 499{ 500 struct pmc_classdep *pcd; 501 502 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 503 504 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 505 506 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 507 508 pcd->pcd_caps = IAF_PMC_CAPS; 509 pcd->pcd_class = PMC_CLASS_IAF; 510 pcd->pcd_num = npmc; 511 pcd->pcd_ri = md->pmd_npmc; 512 pcd->pcd_width = pmcwidth; 513 514 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 515 pcd->pcd_config_pmc = iaf_config_pmc; 516 pcd->pcd_describe = iaf_describe; 517 pcd->pcd_get_config = iaf_get_config; 518 pcd->pcd_get_msr = iaf_get_msr; 519 pcd->pcd_pcpu_fini = core_pcpu_noop; 520 pcd->pcd_pcpu_init = core_pcpu_noop; 521 pcd->pcd_read_pmc = iaf_read_pmc; 522 pcd->pcd_release_pmc = iaf_release_pmc; 523 pcd->pcd_start_pmc = iaf_start_pmc; 524 pcd->pcd_stop_pmc = iaf_stop_pmc; 525 pcd->pcd_write_pmc = iaf_write_pmc; 526 527 md->pmd_npmc += npmc; 528} 529 530/* 531 * Intel programmable PMCs. 532 */ 533 534/* 535 * Event descriptor tables. 536 * 537 * For each event id, we track: 538 * 539 * 1. The CPUs that the event is valid for. 540 * 541 * 2. If the event uses a fixed UMASK, the value of the umask field. 542 * If the event doesn't use a fixed UMASK, a mask of legal bits 543 * to check against. 544 */ 545 546struct iap_event_descr { 547 enum pmc_event iap_ev; 548 unsigned char iap_evcode; 549 unsigned char iap_umask; 550 unsigned char iap_flags; 551}; 552 553#define IAP_F_CC (1 << 0) /* CPU: Core */ 554#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 555#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 556#define IAP_F_CA (1 << 3) /* CPU: Atom */ 557#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 558#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 559#define IAP_F_WM (1 << 5) /* CPU: Westmere */ 560#define IAP_F_SB (1 << 6) /* CPU: Sandy Brdige */ 561#define IAP_F_FM (1 << 7) /* Fixed mask */ 562 563#define IAP_F_ALLCPUSCORE2 \ 564 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 565 566/* Sub fields of UMASK that this event supports. */ 567#define IAP_M_CORE (1 << 0) /* Core specificity */ 568#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 569#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 570#define IAP_M_MESI (1 << 3) /* MESI */ 571#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 572#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 573#define IAP_M_TRANSITION (1 << 6) /* Transition */ 574 575#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 576#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 577#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 578#define IAP_F_MESI (0xF << 8) /* MESI */ 579#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 580#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 581#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 582 583#define IAP_PREFETCH_RESERVED (0x2 << 12) 584#define IAP_CORE_THIS (0x1 << 14) 585#define IAP_CORE_ALL (0x3 << 14) 586#define IAP_F_CMASK 0xFF000000 587 588static struct iap_event_descr iap_events[] = { 589#undef IAPDESCR 590#define IAPDESCR(N,EV,UM,FLAGS) { \ 591 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 592 .iap_evcode = (EV), \ 593 .iap_umask = (UM), \ 594 .iap_flags = (FLAGS) \ 595 } 596 597 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 598 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 599 600 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 601 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB), 602 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 603 IAP_F_WM | IAP_F_SB), 604 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 605 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), 606 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), 607 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 608 609 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 610 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 611 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 612 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 613 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 614 615 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 616 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB), 617 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB), 618 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 619 620 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 621 IAP_F_CC2E | IAP_F_CA), 622 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 623 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 624 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 625 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 626 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 627 628 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 629 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 630 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 631 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 632 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 633 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 634 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB), 635 636 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 637 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 638 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 639 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 640 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 641 IAP_F_WM | IAP_F_SB), 642 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 643 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 644 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 645 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 646 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 647 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 648 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 649 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), 650 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 651 652 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 653 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 654 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 655 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 656 657 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 658 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 659 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 660 661 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 662 IAP_F_WM), 663 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 664 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 665 666 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB), 667 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB), 668 669 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 670 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 671 672 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 673 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 674 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 675 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 676 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 677 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 678 679 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 680 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 681 IAP_F_WM | IAP_F_SB), 682 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 683 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 684 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 685 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 686 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 687 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 688 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 689 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 690 691 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 692 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB), 693 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB), 694 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 695 696 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 697 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 698 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 699 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 700 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 701 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 702 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 703 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 704 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 705 706 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 707 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 708 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 709 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 710 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 711 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 712 713 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 714 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 715 IAP_F_WM | IAP_F_SB), 716 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 717 718 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 719 720 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 721 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 722 723 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 724 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 725 IAP_F_I7 | IAP_F_WM), 726 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 727 728 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 729 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 730 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 731 732 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 733 734 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 735 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 736 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 737 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 738 739 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 740 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 741 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 742 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 743 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 744 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 745 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 746 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 747 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 748 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 749 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 750 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 751 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 752 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 755 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 756 757 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 758 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 759 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 761 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 762 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 763 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 764 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 765 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 766 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 769 770 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 771 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 772 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 773 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB), 774 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 775 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 776 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 777 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 778 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 779 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 780 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 781 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 782 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 783 784 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 785 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 786 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 787 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 788 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), 789 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 790 791 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 792 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 793 IAP_F_CA | IAP_F_CC2), 794 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 795 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 796 797 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 798 IAP_F_ALLCPUSCORE2), 799 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 800 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 801 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 802 IAP_F_SB), 803 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 804 IAP_F_SB), 805 806 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 807 IAP_F_ALLCPUSCORE2), 808 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 809 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 810 811 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 812 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 813 814 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 815 816 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 817 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 818 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 819 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 820 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 821 822 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 823 824 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 825 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 826 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 827 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 828 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 829 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 830 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 831 832 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 833 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 834 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 835 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 836 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 837 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 838 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 839 840 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 841 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 842 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 843 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 844 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 845 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 846 847 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 848 IAP_F_I7), 849 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 850 IAP_F_CC2 | IAP_F_I7), 851 852 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 853 854 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 855 856 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 857 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 858 859 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 860 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB), 861 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 862 863 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 864 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 865 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 866 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 867 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 868 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB), 869 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 870 IAP_F_SB), 871 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), 872 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), 873 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7), 874 875 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 876 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 877 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 878 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 879 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 880 881 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 882 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 883 IAP_F_SB), 884 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB), 885 886 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 887 888 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 889 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 890 IAP_F_SB), 891 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 892 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 893 894 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 895 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 896 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 897 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 898 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 899 900 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 901 IAP_F_SB), 902 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 903 IAP_F_SB), 904 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 905 IAP_F_SB), 906 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 907 IAP_F_SB), 908 909 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 910 911 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 912 913 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB), 914 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB), 915 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB), 916 917 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB), 918 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB), 919 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB), 920 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB), 921 922 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB), 923 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB), 924 925 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB), 926 927 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 928 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 929 IAP_F_SB), 930 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 931 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 932 IAP_F_SB), 933 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 934 IAP_F_SB), 935 936 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 937 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 938 939 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 940 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 941 942 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 943 IAP_F_CA | IAP_F_CC2), 944 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 945 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 946 IAP_F_SB), 947 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 948 IAP_F_SB), 949 950 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 951 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 952 953 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 954 IAP_F_CA | IAP_F_CC2), 955 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 956 957 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 958 959 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 960 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 961 962 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 963 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 964 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 965 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 966 967 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 968 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 969 970 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 971 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 972 973 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 974 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 975 976 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 977 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 978 979 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 980 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 981 982 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 983 IAP_F_CA | IAP_F_CC2), 984 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 985 986 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 987 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 988 989 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB), 990 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB), 991 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB), 992 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB), 993 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB), 994 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB), 995 996 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 997 998 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 999 1000 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1001 1002 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1003 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1004 1005 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1006 1007 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1008 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1009 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1010 IAP_F_WM | IAP_F_SB), 1011 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1012 IAP_F_WM), 1013 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1014 1015 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1016 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1017 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1018 1019 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1020 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1021 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1022 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1023 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1024 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1025 1026 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1027 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1028 1029 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1030 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1031 IAP_F_SB), 1032 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1033 IAP_F_SB), 1034 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1035 IAP_F_SB), 1036 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB), 1037 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), 1038 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), 1039 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1040 1041 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1042 1043 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1044 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1045 IAP_F_SB), 1046 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1047 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1048 IAP_F_SB), 1049 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1050 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1051 1052 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1053 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1054 IAP_F_SB), 1055 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1056 IAP_F_SB), 1057 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1058 IAP_F_SB), 1059 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1060 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1061 IAP_F_SB), 1062 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1063 IAP_F_SB), 1064 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1065 IAP_F_SB), 1066 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1067 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1068 IAP_F_SB), 1069 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1070 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB), 1071 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB), 1072 1073 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1074 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1075 IAP_F_SB), 1076 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1077 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1078 IAP_F_SB), 1079 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1080 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1081 IAP_F_SB), 1082 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1083 IAP_F_SB), 1084 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1085 IAP_F_SB), 1086 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1087 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1088 IAP_F_SB), 1089 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1090 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB), 1091 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB), 1092 1093 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1094 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1095 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1096 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1097 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1098 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1099 1100 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1101 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1102 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1103 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1104 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1105 1106 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB), 1107 1108 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1109 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1110 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1111 1112 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1113 IAP_F_SB), 1114 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1115 IAP_F_SB), 1116 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1117 IAP_F_SB), 1118 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1119 IAP_F_SB), 1120 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB), 1121 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1122 IAP_F_SB), 1123 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1124 IAP_F_SB), 1125 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB), 1126 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB), 1127 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB), 1128 1129 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1130 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1131 IAP_F_SB), 1132 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1133 IAP_F_SB), 1134 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1135 IAP_F_SB), 1136 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1137 IAP_F_SB), 1138 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1139 IAP_F_SB), 1140 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1141 IAP_F_SB), 1142 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1143 IAP_F_SB), 1144 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1145 IAP_F_SB), 1146 1147 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1148 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1149 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1150 1151 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1152 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1153 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1154 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1155 1156 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1157 IAP_F_SB), 1158 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1159 IAP_F_SB), 1160 1161 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB), 1162 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB), 1163 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB), 1164 1165 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1166 IAP_F_SB), 1167 1168 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1169 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1170 IAP_F_SB), 1171 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1172 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1173 IAP_F_SB), 1174 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1175 IAP_F_SB), 1176 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1177 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1178 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1179 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1180 1181 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1182 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1183 IAP_F_SB), 1184 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1185 IAP_F_SB), 1186 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1187 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1188 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1189 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1190 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1191 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1192 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1193 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1194 IAP_F_WM), 1195 1196 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1197 IAP_F_SB), 1198 1199 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1200 IAP_F_WM | IAP_F_I7O), 1201 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1202 IAP_F_WM | IAP_F_I7O), 1203 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1204 IAP_F_WM | IAP_F_I7O), 1205 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1206 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1207 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1208 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1209 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1210 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1211 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1212 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1213 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1214 1215 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1216 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1217 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1218 1219 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB), 1220 1221 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1222 IAP_F_SB), 1223 1224 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1225 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1226 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1227 1228 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1229 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1230 1231 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1232 IAP_F_SB), 1233 1234 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB), 1235 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB), 1236 1237 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB), 1238 1239 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1240 IAP_F_SB), 1241 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1242 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1243 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1244 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1245 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1246 IAP_F_I7 | IAP_F_WM), 1247 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1248 1249 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1250 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1251 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB), 1252 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB), 1253 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB), 1254 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB), 1255 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1256 1257 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1258 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1259 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1260 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1261 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1262 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1263 IAP_F_I7 | IAP_F_WM), 1264 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1265 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1266 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1267 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1268 1269 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1270 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1271 IAP_F_I7 | IAP_F_WM), 1272 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1273 IAP_F_SB), 1274 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1275 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1276 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1277 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB), 1278 1279 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1280 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1281 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1282 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1283 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1284 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1285 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1286 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1287 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1288 IAP_F_SB), 1289 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1290 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1291 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB), 1292 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB), 1293 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB), 1294 1295 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1296 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1297 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB), 1298 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1299 IAP_F_SB), 1300 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB), 1301 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB), 1302 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB), 1303 1304 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1305 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1306 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1307 1308 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1309 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1310 IAP_F_I7 | IAP_F_WM), 1311 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1312 IAP_F_I7 | IAP_F_WM), 1313 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1314 IAP_F_I7 | IAP_F_WM), 1315 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1316 IAP_F_I7 | IAP_F_WM), 1317 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1318 IAP_F_I7 | IAP_F_WM), 1319 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1320 1321 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1322 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1323 1324 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1325 1326 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1327 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1328 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1329 IAP_F_SB), 1330 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1331 IAP_F_SB), 1332 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1333 IAP_F_SB), 1334 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB), 1335 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB), 1336 1337 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1338 IAP_F_I7 | IAP_F_WM), 1339 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1340 IAP_F_I7 | IAP_F_WM), 1341 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1342 IAP_F_I7 | IAP_F_WM), 1343 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1344 IAP_F_I7 | IAP_F_WM), 1345 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1346 IAP_F_WM), 1347 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1348 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1349 1350 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1351 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1352 IAP_F_I7 | IAP_F_WM), 1353 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1354 IAP_F_I7 | IAP_F_WM), 1355 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1356 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB), 1357 1358 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1359 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB), 1360 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB), 1361 1362 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1363 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1364 1365 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1366 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1367 IAP_F_SB), 1368 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB), 1369 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB), 1370 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB), 1371 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB), 1372 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB), 1373 1374 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB), 1375 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1376 IAP_F_SB), 1377 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1378 IAP_F_SB), 1379 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1380 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB), 1381 1382 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1383 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1384 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1385 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1386 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1387 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1388 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1389 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1390 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1391 IAP_F_I7 | IAP_F_WM), 1392 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1393 1394 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1395 IAP_F_I7 | IAP_F_WM), 1396 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1397 IAP_F_SB), 1398 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1399 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1400 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1401 1402 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1403 IAP_F_I7 | IAP_F_WM), 1404 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1405 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1406 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1407 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1408 1409 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1410 1411 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1412 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1413 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1414 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1415 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1416 1417 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1418 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1419 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1420 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1421 1422 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1423 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1424 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1425 1426 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1427 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1428 1429 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1430 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1431 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1432 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1433 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1434 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1435 1436 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1437 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1438 IAP_F_WM), 1439 1440 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1441 1442 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1443 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1444 1445 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1446 1447 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1448 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1449 IAP_F_WM), 1450 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1451 1452 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1453 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1454 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1455 1456 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1457 1458 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1459 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1460 IAP_F_SB), 1461 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1462 IAP_F_SB), 1463 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1464 IAP_F_SB), 1465 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1466 IAP_F_SB), 1467 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1468 IAP_F_SB), 1469 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1470 IAP_F_SB), 1471 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1472 IAP_F_SB), 1473 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1474 IAP_F_SB), 1475 1476 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB), 1477 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1478 IAP_F_SB), 1479 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1480 IAP_F_SB), 1481 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1482 IAP_F_SB), 1483 1484 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1485 IAP_F_SB), 1486 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1487 IAP_F_SB), 1488 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1489 IAP_F_SB), 1490 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1491 IAP_F_SB), 1492 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB), 1493 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1494 1495 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1496 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1497 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1498 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1499 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1500 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1501 1502 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1503 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1504 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1505 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1506 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1507 IAP_F_SB), 1508 1509 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1510 1511 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1512 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1513 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1514 1515 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1516 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1517 1518 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1519 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1520 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1521 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1522 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1523 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1524 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1525}; 1526 1527static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1528 1529static pmc_value_t 1530iap_perfctr_value_to_reload_count(pmc_value_t v) 1531{ 1532 v &= (1ULL << core_iap_width) - 1; 1533 return (1ULL << core_iap_width) - v; 1534} 1535 1536static pmc_value_t 1537iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1538{ 1539 return (1ULL << core_iap_width) - rlc; 1540} 1541 1542static int 1543iap_pmc_has_overflowed(int ri) 1544{ 1545 uint64_t v; 1546 1547 /* 1548 * We treat a Core (i.e., Intel architecture v1) PMC as has 1549 * having overflowed if its MSB is zero. 1550 */ 1551 v = rdpmc(ri); 1552 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1553} 1554 1555/* 1556 * Check an event against the set of supported architectural events. 1557 * 1558 * Returns 1 if the event is architectural and unsupported on this 1559 * CPU. Returns 0 otherwise. 1560 */ 1561 1562static int 1563iap_architectural_event_is_unsupported(enum pmc_event pe) 1564{ 1565 enum core_arch_events ae; 1566 1567 switch (pe) { 1568 case PMC_EV_IAP_EVENT_3CH_00H: 1569 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1570 break; 1571 case PMC_EV_IAP_EVENT_C0H_00H: 1572 ae = CORE_AE_INSTRUCTION_RETIRED; 1573 break; 1574 case PMC_EV_IAP_EVENT_3CH_01H: 1575 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1576 break; 1577 case PMC_EV_IAP_EVENT_2EH_4FH: 1578 ae = CORE_AE_LLC_REFERENCE; 1579 break; 1580 case PMC_EV_IAP_EVENT_2EH_41H: 1581 ae = CORE_AE_LLC_MISSES; 1582 break; 1583 case PMC_EV_IAP_EVENT_C4H_00H: 1584 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1585 break; 1586 case PMC_EV_IAP_EVENT_C5H_00H: 1587 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1588 break; 1589 1590 default: /* Non architectural event. */ 1591 return (0); 1592 } 1593 1594 return ((core_architectural_events & (1 << ae)) == 0); 1595} 1596 1597static int 1598iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1599{ 1600 uint32_t mask; 1601 1602 switch (pe) { 1603 /* 1604 * Events valid only on counter 0, 1. 1605 */ 1606 case PMC_EV_IAP_EVENT_40H_01H: 1607 case PMC_EV_IAP_EVENT_40H_02H: 1608 case PMC_EV_IAP_EVENT_40H_04H: 1609 case PMC_EV_IAP_EVENT_40H_08H: 1610 case PMC_EV_IAP_EVENT_40H_0FH: 1611 case PMC_EV_IAP_EVENT_41H_02H: 1612 case PMC_EV_IAP_EVENT_41H_04H: 1613 case PMC_EV_IAP_EVENT_41H_08H: 1614 case PMC_EV_IAP_EVENT_42H_01H: 1615 case PMC_EV_IAP_EVENT_42H_02H: 1616 case PMC_EV_IAP_EVENT_42H_04H: 1617 case PMC_EV_IAP_EVENT_42H_08H: 1618 case PMC_EV_IAP_EVENT_43H_01H: 1619 case PMC_EV_IAP_EVENT_43H_02H: 1620 case PMC_EV_IAP_EVENT_51H_01H: 1621 case PMC_EV_IAP_EVENT_51H_02H: 1622 case PMC_EV_IAP_EVENT_51H_04H: 1623 case PMC_EV_IAP_EVENT_51H_08H: 1624 case PMC_EV_IAP_EVENT_63H_01H: 1625 case PMC_EV_IAP_EVENT_63H_02H: 1626 mask = 0x3; 1627 break; 1628 1629 default: 1630 mask = ~0; /* Any row index is ok. */ 1631 } 1632 1633 return (mask & (1 << ri)); 1634} 1635 1636static int 1637iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1638{ 1639 uint32_t mask; 1640 1641 switch (pe) { 1642 /* 1643 * Events valid only on counter 0. 1644 */ 1645 case PMC_EV_IAP_EVENT_60H_01H: 1646 case PMC_EV_IAP_EVENT_60H_02H: 1647 case PMC_EV_IAP_EVENT_60H_04H: 1648 case PMC_EV_IAP_EVENT_60H_08H: 1649 case PMC_EV_IAP_EVENT_B3H_01H: 1650 case PMC_EV_IAP_EVENT_B3H_02H: 1651 case PMC_EV_IAP_EVENT_B3H_04H: 1652 mask = 0x1; 1653 break; 1654 1655 /* 1656 * Events valid only on counter 0, 1. 1657 */ 1658 case PMC_EV_IAP_EVENT_4CH_01H: 1659 case PMC_EV_IAP_EVENT_4EH_01H: 1660 case PMC_EV_IAP_EVENT_4EH_02H: 1661 case PMC_EV_IAP_EVENT_4EH_04H: 1662 case PMC_EV_IAP_EVENT_51H_01H: 1663 case PMC_EV_IAP_EVENT_51H_02H: 1664 case PMC_EV_IAP_EVENT_51H_04H: 1665 case PMC_EV_IAP_EVENT_51H_08H: 1666 case PMC_EV_IAP_EVENT_63H_01H: 1667 case PMC_EV_IAP_EVENT_63H_02H: 1668 mask = 0x3; 1669 break; 1670 1671 default: 1672 mask = ~0; /* Any row index is ok. */ 1673 } 1674 1675 return (mask & (1 << ri)); 1676} 1677 1678static int 1679iap_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri) 1680{ 1681 uint32_t mask; 1682 1683 switch (pe) { 1684 /* 1685 * Events valid only on counter 2. 1686 */ 1687 case PMC_EV_IAP_EVENT_48H_01H: 1688 mask = 0x2; 1689 break; 1690 default: 1691 mask = ~0; /* Any row index is ok. */ 1692 } 1693 1694 return (mask & (1 << ri)); 1695} 1696 1697static int 1698iap_event_ok_on_counter(enum pmc_event pe, int ri) 1699{ 1700 uint32_t mask; 1701 1702 switch (pe) { 1703 /* 1704 * Events valid only on counter 0. 1705 */ 1706 case PMC_EV_IAP_EVENT_10H_00H: 1707 case PMC_EV_IAP_EVENT_14H_00H: 1708 case PMC_EV_IAP_EVENT_18H_00H: 1709 case PMC_EV_IAP_EVENT_B3H_01H: 1710 case PMC_EV_IAP_EVENT_B3H_02H: 1711 case PMC_EV_IAP_EVENT_B3H_04H: 1712 case PMC_EV_IAP_EVENT_C1H_00H: 1713 case PMC_EV_IAP_EVENT_CBH_01H: 1714 case PMC_EV_IAP_EVENT_CBH_02H: 1715 mask = (1 << 0); 1716 break; 1717 1718 /* 1719 * Events valid only on counter 1. 1720 */ 1721 case PMC_EV_IAP_EVENT_11H_00H: 1722 case PMC_EV_IAP_EVENT_12H_00H: 1723 case PMC_EV_IAP_EVENT_13H_00H: 1724 mask = (1 << 1); 1725 break; 1726 1727 default: 1728 mask = ~0; /* Any row index is ok. */ 1729 } 1730 1731 return (mask & (1 << ri)); 1732} 1733 1734static int 1735iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1736 const struct pmc_op_pmcallocate *a) 1737{ 1738 int n, model; 1739 enum pmc_event ev; 1740 struct iap_event_descr *ie; 1741 uint32_t c, caps, config, cpuflag, evsel, mask; 1742 1743 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1744 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1745 KASSERT(ri >= 0 && ri < core_iap_npmc, 1746 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1747 1748 /* check requested capabilities */ 1749 caps = a->pm_caps; 1750 if ((IAP_PMC_CAPS & caps) != caps) 1751 return (EPERM); 1752 1753 ev = pm->pm_event; 1754 1755 if (iap_architectural_event_is_unsupported(ev)) 1756 return (EOPNOTSUPP); 1757 1758 /* 1759 * A small number of events are not supported in all the 1760 * processors based on a given microarchitecture. 1761 */ 1762 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 1763 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 1764 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 1765 return (EINVAL); 1766 } 1767 1768 switch (core_cputype) { 1769 case PMC_CPU_INTEL_COREI7: 1770 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1771 return (EINVAL); 1772 break; 1773 case PMC_CPU_INTEL_SANDYBRIDGE: 1774 if (iap_event_sandybridge_ok_on_counter(ev, ri) == 0) 1775 return (EINVAL); 1776 break; 1777 case PMC_CPU_INTEL_WESTMERE: 1778 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1779 return (EINVAL); 1780 break; 1781 default: 1782 if (iap_event_ok_on_counter(ev, ri) == 0) 1783 return (EINVAL); 1784 } 1785 1786 /* 1787 * Look for an event descriptor with matching CPU and event id 1788 * fields. 1789 */ 1790 1791 switch (core_cputype) { 1792 default: 1793 case PMC_CPU_INTEL_ATOM: 1794 cpuflag = IAP_F_CA; 1795 break; 1796 case PMC_CPU_INTEL_CORE: 1797 cpuflag = IAP_F_CC; 1798 break; 1799 case PMC_CPU_INTEL_CORE2: 1800 cpuflag = IAP_F_CC2; 1801 break; 1802 case PMC_CPU_INTEL_CORE2EXTREME: 1803 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1804 break; 1805 case PMC_CPU_INTEL_COREI7: 1806 cpuflag = IAP_F_I7; 1807 break; 1808 case PMC_CPU_INTEL_SANDYBRIDGE: 1809 cpuflag = IAP_F_SB; 1810 break; 1811 case PMC_CPU_INTEL_WESTMERE: 1812 cpuflag = IAP_F_WM; 1813 break; 1814 } 1815 1816 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1817 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1818 break; 1819 1820 if (n == niap_events) 1821 return (EINVAL); 1822 1823 /* 1824 * A matching event descriptor has been found, so start 1825 * assembling the contents of the event select register. 1826 */ 1827 evsel = ie->iap_evcode; 1828 1829 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1830 1831 /* 1832 * If the event uses a fixed umask value, reject any umask 1833 * bits set by the user. 1834 */ 1835 if (ie->iap_flags & IAP_F_FM) { 1836 1837 if (IAP_UMASK(config) != 0) 1838 return (EINVAL); 1839 1840 evsel |= (ie->iap_umask << 8); 1841 1842 } else { 1843 1844 /* 1845 * Otherwise, the UMASK value needs to be taken from 1846 * the MD fields of the allocation request. Reject 1847 * requests that specify reserved bits. 1848 */ 1849 1850 mask = 0; 1851 1852 if (ie->iap_umask & IAP_M_CORE) { 1853 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1854 c != IAP_CORE_THIS) 1855 return (EINVAL); 1856 mask |= IAP_F_CORE; 1857 } 1858 1859 if (ie->iap_umask & IAP_M_AGENT) 1860 mask |= IAP_F_AGENT; 1861 1862 if (ie->iap_umask & IAP_M_PREFETCH) { 1863 1864 if ((c = (config & IAP_F_PREFETCH)) == 1865 IAP_PREFETCH_RESERVED) 1866 return (EINVAL); 1867 1868 mask |= IAP_F_PREFETCH; 1869 } 1870 1871 if (ie->iap_umask & IAP_M_MESI) 1872 mask |= IAP_F_MESI; 1873 1874 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 1875 mask |= IAP_F_SNOOPRESPONSE; 1876 1877 if (ie->iap_umask & IAP_M_SNOOPTYPE) 1878 mask |= IAP_F_SNOOPTYPE; 1879 1880 if (ie->iap_umask & IAP_M_TRANSITION) 1881 mask |= IAP_F_TRANSITION; 1882 1883 /* 1884 * If bits outside of the allowed set of umask bits 1885 * are set, reject the request. 1886 */ 1887 if (config & ~mask) 1888 return (EINVAL); 1889 1890 evsel |= (config & mask); 1891 1892 } 1893 1894 /* 1895 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 1896 */ 1897 if (core_cputype == PMC_CPU_INTEL_ATOM || 1898 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE) 1899 evsel |= (config & IAP_ANY); 1900 else if (config & IAP_ANY) 1901 return (EINVAL); 1902 1903 /* 1904 * Check offcore response configuration. 1905 */ 1906 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 1907 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 1908 ev != PMC_EV_IAP_EVENT_BBH_01H) 1909 return (EINVAL); 1910 if (core_cputype == PMC_CPU_INTEL_COREI7 && 1911 ev == PMC_EV_IAP_EVENT_BBH_01H) 1912 return (EINVAL); 1913 if (a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK) 1914 return (EINVAL); 1915 pm->pm_md.pm_iap.pm_iap_rsp = 1916 a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK; 1917 } 1918 1919 if (caps & PMC_CAP_THRESHOLD) 1920 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 1921 if (caps & PMC_CAP_USER) 1922 evsel |= IAP_USR; 1923 if (caps & PMC_CAP_SYSTEM) 1924 evsel |= IAP_OS; 1925 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 1926 evsel |= (IAP_OS | IAP_USR); 1927 if (caps & PMC_CAP_EDGE) 1928 evsel |= IAP_EDGE; 1929 if (caps & PMC_CAP_INVERT) 1930 evsel |= IAP_INV; 1931 if (caps & PMC_CAP_INTERRUPT) 1932 evsel |= IAP_INT; 1933 1934 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 1935 1936 return (0); 1937} 1938 1939static int 1940iap_config_pmc(int cpu, int ri, struct pmc *pm) 1941{ 1942 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1943 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1944 1945 KASSERT(ri >= 0 && ri < core_iap_npmc, 1946 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1947 1948 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 1949 1950 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 1951 cpu)); 1952 1953 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 1954 1955 return (0); 1956} 1957 1958static int 1959iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 1960{ 1961 int error; 1962 struct pmc_hw *phw; 1963 char iap_name[PMC_NAME_MAX]; 1964 1965 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 1966 1967 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 1968 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 1969 NULL)) != 0) 1970 return (error); 1971 1972 pi->pm_class = PMC_CLASS_IAP; 1973 1974 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 1975 pi->pm_enabled = TRUE; 1976 *ppmc = phw->phw_pmc; 1977 } else { 1978 pi->pm_enabled = FALSE; 1979 *ppmc = NULL; 1980 } 1981 1982 return (0); 1983} 1984 1985static int 1986iap_get_config(int cpu, int ri, struct pmc **ppm) 1987{ 1988 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1989 1990 return (0); 1991} 1992 1993static int 1994iap_get_msr(int ri, uint32_t *msr) 1995{ 1996 KASSERT(ri >= 0 && ri < core_iap_npmc, 1997 ("[iap,%d] ri %d out of range", __LINE__, ri)); 1998 1999 *msr = ri; 2000 2001 return (0); 2002} 2003 2004static int 2005iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2006{ 2007 struct pmc *pm; 2008 pmc_value_t tmp; 2009 2010 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2011 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2012 KASSERT(ri >= 0 && ri < core_iap_npmc, 2013 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2014 2015 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2016 2017 KASSERT(pm, 2018 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2019 ri)); 2020 2021 tmp = rdpmc(ri); 2022 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2023 *v = iap_perfctr_value_to_reload_count(tmp); 2024 else 2025 *v = tmp & ((1ULL << core_iap_width) - 1); 2026 2027 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2028 ri, *v); 2029 2030 return (0); 2031} 2032 2033static int 2034iap_release_pmc(int cpu, int ri, struct pmc *pm) 2035{ 2036 (void) pm; 2037 2038 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2039 pm); 2040 2041 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2042 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2043 KASSERT(ri >= 0 && ri < core_iap_npmc, 2044 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2045 2046 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2047 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2048 2049 return (0); 2050} 2051 2052static int 2053iap_start_pmc(int cpu, int ri) 2054{ 2055 struct pmc *pm; 2056 uint32_t evsel; 2057 struct core_cpu *cc; 2058 2059 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2060 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2061 KASSERT(ri >= 0 && ri < core_iap_npmc, 2062 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2063 2064 cc = core_pcpu[cpu]; 2065 pm = cc->pc_corepmcs[ri].phw_pmc; 2066 2067 KASSERT(pm, 2068 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2069 __LINE__, cpu, ri)); 2070 2071 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2072 2073 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2074 2075 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2076 cpu, ri, IAP_EVSEL0 + ri, evsel); 2077 2078 /* Event specific configuration. */ 2079 switch (pm->pm_event) { 2080 case PMC_EV_IAP_EVENT_B7H_01H: 2081 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2082 break; 2083 case PMC_EV_IAP_EVENT_BBH_01H: 2084 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2085 break; 2086 default: 2087 break; 2088 } 2089 2090 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2091 2092 if (core_cputype == PMC_CPU_INTEL_CORE) 2093 return (0); 2094 2095 do { 2096 cc->pc_resync = 0; 2097 cc->pc_globalctrl |= (1ULL << ri); 2098 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2099 } while (cc->pc_resync != 0); 2100 2101 return (0); 2102} 2103 2104static int 2105iap_stop_pmc(int cpu, int ri) 2106{ 2107 struct pmc *pm; 2108 struct core_cpu *cc; 2109 uint64_t msr; 2110 2111 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2112 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2113 KASSERT(ri >= 0 && ri < core_iap_npmc, 2114 ("[core,%d] illegal row index %d", __LINE__, ri)); 2115 2116 cc = core_pcpu[cpu]; 2117 pm = cc->pc_corepmcs[ri].phw_pmc; 2118 2119 KASSERT(pm, 2120 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2121 cpu, ri)); 2122 2123 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2124 2125 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2126 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2127 2128 if (core_cputype == PMC_CPU_INTEL_CORE) 2129 return (0); 2130 2131 msr = 0; 2132 do { 2133 cc->pc_resync = 0; 2134 cc->pc_globalctrl &= ~(1ULL << ri); 2135 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2136 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2137 } while (cc->pc_resync != 0); 2138 2139 return (0); 2140} 2141 2142static int 2143iap_write_pmc(int cpu, int ri, pmc_value_t v) 2144{ 2145 struct pmc *pm; 2146 struct core_cpu *cc; 2147 2148 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2149 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2150 KASSERT(ri >= 0 && ri < core_iap_npmc, 2151 ("[core,%d] illegal row index %d", __LINE__, ri)); 2152 2153 cc = core_pcpu[cpu]; 2154 pm = cc->pc_corepmcs[ri].phw_pmc; 2155 2156 KASSERT(pm, 2157 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2158 cpu, ri)); 2159 2160 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2161 IAP_PMC0 + ri, v); 2162 2163 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2164 v = iap_reload_count_to_perfctr_value(v); 2165 2166 /* 2167 * Write the new value to the counter. The counter will be in 2168 * a stopped state when the pcd_write() entry point is called. 2169 */ 2170 2171 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2172 2173 return (0); 2174} 2175 2176 2177static void 2178iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2179 int flags) 2180{ 2181 struct pmc_classdep *pcd; 2182 2183 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2184 2185 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2186 2187 /* Remember the set of architectural events supported. */ 2188 core_architectural_events = ~flags; 2189 2190 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2191 2192 pcd->pcd_caps = IAP_PMC_CAPS; 2193 pcd->pcd_class = PMC_CLASS_IAP; 2194 pcd->pcd_num = npmc; 2195 pcd->pcd_ri = md->pmd_npmc; 2196 pcd->pcd_width = pmcwidth; 2197 2198 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2199 pcd->pcd_config_pmc = iap_config_pmc; 2200 pcd->pcd_describe = iap_describe; 2201 pcd->pcd_get_config = iap_get_config; 2202 pcd->pcd_get_msr = iap_get_msr; 2203 pcd->pcd_pcpu_fini = core_pcpu_fini; 2204 pcd->pcd_pcpu_init = core_pcpu_init; 2205 pcd->pcd_read_pmc = iap_read_pmc; 2206 pcd->pcd_release_pmc = iap_release_pmc; 2207 pcd->pcd_start_pmc = iap_start_pmc; 2208 pcd->pcd_stop_pmc = iap_stop_pmc; 2209 pcd->pcd_write_pmc = iap_write_pmc; 2210 2211 md->pmd_npmc += npmc; 2212} 2213 2214static int 2215core_intr(int cpu, struct trapframe *tf) 2216{ 2217 pmc_value_t v; 2218 struct pmc *pm; 2219 struct core_cpu *cc; 2220 int error, found_interrupt, ri; 2221 uint64_t msr; 2222 2223 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2224 TRAPF_USERMODE(tf)); 2225 2226 found_interrupt = 0; 2227 cc = core_pcpu[cpu]; 2228 2229 for (ri = 0; ri < core_iap_npmc; ri++) { 2230 2231 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2232 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2233 continue; 2234 2235 if (!iap_pmc_has_overflowed(ri)) 2236 continue; 2237 2238 found_interrupt = 1; 2239 2240 if (pm->pm_state != PMC_STATE_RUNNING) 2241 continue; 2242 2243 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2244 TRAPF_USERMODE(tf)); 2245 2246 v = pm->pm_sc.pm_reloadcount; 2247 v = iaf_reload_count_to_perfctr_value(v); 2248 2249 /* 2250 * Stop the counter, reload it but only restart it if 2251 * the PMC is not stalled. 2252 */ 2253 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2254 wrmsr(IAP_EVSEL0 + ri, msr); 2255 wrmsr(IAP_PMC0 + ri, v); 2256 2257 if (error) 2258 continue; 2259 2260 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2261 IAP_EN)); 2262 } 2263 2264 if (found_interrupt) 2265 lapic_reenable_pmc(); 2266 2267 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2268 &pmc_stats.pm_intr_ignored, 1); 2269 2270 return (found_interrupt); 2271} 2272 2273static int 2274core2_intr(int cpu, struct trapframe *tf) 2275{ 2276 int error, found_interrupt, n; 2277 uint64_t flag, intrstatus, intrenable, msr; 2278 struct pmc *pm; 2279 struct core_cpu *cc; 2280 pmc_value_t v; 2281 2282 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2283 TRAPF_USERMODE(tf)); 2284 2285 /* 2286 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2287 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2288 * the current set of interrupting PMCs and process these 2289 * after stopping them. 2290 */ 2291 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2292 intrenable = intrstatus & core_pmcmask; 2293 2294 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2295 (uintmax_t) intrstatus); 2296 2297 found_interrupt = 0; 2298 cc = core_pcpu[cpu]; 2299 2300 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2301 2302 cc->pc_globalctrl &= ~intrenable; 2303 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2304 2305 /* 2306 * Stop PMCs and clear overflow status bits. 2307 */ 2308 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2309 wrmsr(IA_GLOBAL_CTRL, msr); 2310 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2311 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2312 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2313 2314 /* 2315 * Look for interrupts from fixed function PMCs. 2316 */ 2317 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2318 n++, flag <<= 1) { 2319 2320 if ((intrstatus & flag) == 0) 2321 continue; 2322 2323 found_interrupt = 1; 2324 2325 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2326 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2327 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2328 continue; 2329 2330 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2331 TRAPF_USERMODE(tf)); 2332 if (error) 2333 intrenable &= ~flag; 2334 2335 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2336 2337 /* Reload sampling count. */ 2338 wrmsr(IAF_CTR0 + n, v); 2339 2340 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2341 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2342 } 2343 2344 /* 2345 * Process interrupts from the programmable counters. 2346 */ 2347 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2348 if ((intrstatus & flag) == 0) 2349 continue; 2350 2351 found_interrupt = 1; 2352 2353 pm = cc->pc_corepmcs[n].phw_pmc; 2354 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2355 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2356 continue; 2357 2358 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2359 TRAPF_USERMODE(tf)); 2360 if (error) 2361 intrenable &= ~flag; 2362 2363 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2364 2365 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2366 (uintmax_t) v); 2367 2368 /* Reload sampling count. */ 2369 wrmsr(IAP_PMC0 + n, v); 2370 } 2371 2372 /* 2373 * Reenable all non-stalled PMCs. 2374 */ 2375 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2376 (uintmax_t) intrenable); 2377 2378 cc->pc_globalctrl |= intrenable; 2379 2380 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2381 2382 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2383 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2384 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2385 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2386 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2387 2388 if (found_interrupt) 2389 lapic_reenable_pmc(); 2390 2391 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2392 &pmc_stats.pm_intr_ignored, 1); 2393 2394 return (found_interrupt); 2395} 2396 2397int 2398pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2399{ 2400 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2401 int ipa_version, flags, nflags; 2402 2403 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2404 2405 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2406 2407 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2408 md->pmd_cputype, maxcpu, ipa_version); 2409 2410 if (ipa_version < 1 || ipa_version > 3) { 2411 /* Unknown PMC architecture. */ 2412 printf("hwpc_core: unknown PMC architecture: %d\n", 2413 ipa_version); 2414 return (EPROGMISMATCH); 2415 } 2416 2417 core_cputype = md->pmd_cputype; 2418 2419 core_pmcmask = 0; 2420 2421 /* 2422 * Initialize programmable counters. 2423 */ 2424 KASSERT(ipa_version >= 1, 2425 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2426 2427 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2428 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2429 2430 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2431 2432 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2433 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2434 2435 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2436 2437 /* 2438 * Initialize fixed function counters, if present. 2439 */ 2440 if (core_cputype != PMC_CPU_INTEL_CORE) { 2441 KASSERT(ipa_version >= 2, 2442 ("[core,%d] ipa_version %d too small", __LINE__, 2443 ipa_version)); 2444 2445 core_iaf_ri = core_iap_npmc; 2446 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2447 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2448 2449 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2450 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2451 } 2452 2453 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2454 core_iaf_ri); 2455 2456 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2457 M_ZERO | M_WAITOK); 2458 2459 /* 2460 * Choose the appropriate interrupt handler. 2461 */ 2462 if (ipa_version == 1) 2463 md->pmd_intr = core_intr; 2464 else 2465 md->pmd_intr = core2_intr; 2466 2467 md->pmd_pcpu_fini = NULL; 2468 md->pmd_pcpu_init = NULL; 2469 2470 return (0); 2471} 2472 2473void 2474pmc_core_finalize(struct pmc_mdep *md) 2475{ 2476 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2477 2478 free(core_pcpu, M_PMC); 2479 core_pcpu = NULL; 2480} 2481